| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 132 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
257 EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
260 unsigned NumDestElts = NVT.getVectorNumElements();
266 return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
279 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
280 return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
529 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
530 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
532 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
553 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StSize.getFixedSize())
[all...] |
| LegalizeTypes.cpp | 979 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Pair.getValueType());
980 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
982 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
993 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
996 EVT ShiftAmtVT = TLI.getShiftAmountTy(NVT, DAG.getDataLayout(), false);
997 Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo);
998 Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
999 Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi,
1001 return DAG.getNode(ISD::OR, dlHi, NVT, Lo, Hi);
|
| LegalizeTypesGeneric.cpp | 107 EVT NVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems);
110 while (!isTypeLegal(NVT)) {
117 NVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems);
120 if (isTypeLegal(NVT)) {
121 SDValue CastInOp = DAG.getNode(ISD::BITCAST, dl, NVT, InOp);
257 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
262 assert(NVT.isByteSized() && "Expanded type not byte sized!");
264 Lo = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
269 unsigned IncrementSize = NVT.getSizeInBits() / 8;
272 NVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(IncrementSize)
[all...] |
| LegalizeVectorOps.cpp | 604 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
614 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
615 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j));
617 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(j));
623 DAG.getNode(Node->getOpcode(), dl, NVT, Operands, Node->getFlags());
625 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
627 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
641 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT)
[all...] |
| LegalizeFloatTypes.cpp | 158 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
167 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Op,
177 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
188 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Ops,
253 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
254 unsigned Size = NVT.getSizeInBits();
259 SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT);
261 return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
431 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
449 NVT, Ops, CallOptions, SDLoc(N), Chain)
[all...] |
| LegalizeIntegerTypes.cpp | 289 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
292 // otherwise just use the promoted result type (NVT).
294 SVT = NVT;
460 EVT NVT = Op.getValueType();
467 if (!OVT.isVector() && !TLI.isOperationLegalOrCustom(ISD::BSWAP, NVT)) {
469 return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
472 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
473 EVT ShiftVT = getShiftAmountTyForConstant(NVT, TLI, DAG);
474 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op)
[all...] |
| LegalizeVectorTypes.cpp | 559 EVT NVT = N->getValueType(0).getVectorElementType();
581 return DAG.getNode(ExtendCode, DL, NVT, Res);
773 EVT NVT = VT.getVectorElementType();
784 Res = DAG.getNode(ExtendCode, DL, NVT, Res);
2093 EVT NVT = OVT.getHalfNumVectorElementsVT(*DAG.getContext());
2100 DAG.getDataLayout().getABITypeAlign(NVT.getTypeForEVT(*DAG.getContext()));
2102 Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, SV, Alignment.value());
2103 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, SV, Alignment.value());
5518 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
5519 /// input vector must have the same element type as NVT
[all...] |
| DAGCombiner.cpp | 12060 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, NewEltCnt);
12061 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
12064 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
12070 DAG.getBitcast(NVT, N0.getOperand(0)),
19818 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy, VNTNumElms);
19819 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
19822 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), NVT, Scalar);
20176 EVT NVT = N->getValueType(0);
20182 return DAG.getUNDEF(NVT);
20184 if (TLI.isOperationLegalOrCustomOrPromote(ISD::LOAD, NVT))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 935 MVT NVT = TransformToType[SVT.SimpleTy];
940 (NVT.isVector() ||
941 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
948 return LegalizeKind(LA, NVT);
957 EVT NVT = VT.getRoundIntegerType(Context);
958 assert(NVT != VT && "Unable to round integer VT");
959 LegalizeKind NextStep = getTypeConversion(Context, NVT);
964 return LegalizeKind(TypePromoteInteger, NVT);
987 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
988 return LegalizeKind(TypeWidenVector, NVT);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 3383 MVT NVT = Node->getSimpleValueType(0);
3386 if (NVT != MVT::i32 && NVT != MVT::i64)
3430 auto isAllOnes = [this, peekThroughOneUseTruncation, NVT](SDValue V) {
3434 NVT.getSizeInBits()));
3443 // The -1 only has to be all-ones for the final Node's NVT.
3450 // The -1 only has to be all-ones for the final Node's NVT.
3559 if (NVT != MVT::i32) {
3561 NBits = CurDAG->getNode(ISD::ANY_EXTEND, DL, NVT, NBits);
3565 SDValue Extract = CurDAG->getNode(X86ISD::BZHI, DL, NVT, X, NBits)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetLowering.h | 1376 MVT NVT = VT;
1378 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1379 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1381 } while (!isTypeLegal(NVT) ||
1382 getOperationAction(Op, NVT) == Promote);
1383 return NVT;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 4362 LLT NVT = HalfTy;
4369 Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
4371 Lo = MIRBuilder.buildConstant(NVT, 0);
4372 Hi = MIRBuilder.buildShl(NVT, InL,
4375 Lo = MIRBuilder.buildConstant(NVT, 0);
4378 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
4380 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
4382 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
4383 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
4387 Lo = Hi = MIRBuilder.buildConstant(NVT, 0)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 9872 MVT NVT = MVT::i32;
9875 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
9876 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
9877 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
9879 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3);
|
