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    Searched defs:NewOpc (Results 1 - 25 of 43) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostSelectOptimize.cpp 143 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode());
147 if (InsideCmpRange && NewOpc) {
151 II.setDesc(TII->get(NewOpc));
AArch64PostLegalizerLowering.cpp 503 unsigned NewOpc =
507 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef});
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86EvexToVex.cpp 149 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc,
151 (void)NewOpc;
158 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
174 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
175 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
260 unsigned NewOpc = I->VexOpcode;
268 if (!performCustomAdjustments(MI, NewOpc, ST)
    [all...]
X86FixupLEAs.cpp 598 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode());
604 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
610 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
636 unsigned NewOpc =
638 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
642 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset);
643 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
670 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode());
671 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
693 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode())
    [all...]
X86InstructionSelector.cpp 530 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign());
531 if (NewOpc == Opc)
537 I.setDesc(TII.get(NewOpc));
572 unsigned NewOpc = getLeaOP(Ty, STI);
573 I.setDesc(TII.get(NewOpc));
623 unsigned NewOpc = getLeaOP(Ty, STI);
625 I.setDesc(TII.get(NewOpc));
655 unsigned NewOpc;
658 NewOpc = X86::MOV8ri;
661 NewOpc = X86::MOV16ri
    [all...]
X86MCInstLower.cpp 517 unsigned NewOpc;
520 case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break;
521 case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break;
522 case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break;
523 case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break;
525 OutMI.setOpcode(NewOpc);
549 unsigned NewOpc;
552 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
553 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
554 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CondBrTuning.cpp 100 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit);
106 TII->get(NewOpc), NewDestReg);
AArch64AdvSIMDScalarPass.cpp 292 unsigned NewOpc = getTransformOpcode(OldOpc);
293 assert(OldOpc != NewOpc && "transform an instruction to itself?!");
362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst)
AArch64InstrInfo.cpp 1450 unsigned NewOpc = convertToNonFlagSettingOpc(CmpInstr);
1451 if (NewOpc == Opc)
1453 const MCInstrDesc &MCID = get(NewOpc);
1730 unsigned NewOpc = sForm(*MI);
1731 if (NewOpc == AArch64::INSTRUCTION_LIST_END)
1738 MI->setDesc(get(NewOpc));
4586 unsigned NewOpc = convertToNonFlagSettingOpc(Root);
4589 if (NewOpc == Opc)
4591 Opc = NewOpc;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUPostLegalizerCombiner.cpp 235 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8;
245 assert(MI.getOpcode() != NewOpc);
246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags());
SIFoldOperands.cpp 158 unsigned NewOpc = macToMad(Opc);
159 if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
164 const MCInstrDesc &MadDesc = TII->get(NewOpc);
352 unsigned NewOpc = macToMad(Opc);
353 if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
356 MI->setDesc(TII->get(NewOpc));
671 unsigned NewOpc = AMDGPU::getFlatScratchInstSSfromSV(UseMI->getOpcode());
672 UseMI->setDesc(TII->get(NewOpc));
SIRegisterInfo.cpp 1651 unsigned NewOpc = AMDGPU::getFlatScratchInstSTfromSS(Opc);
1654 MI->setDesc(TII->get(NewOpc));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonGenPredicate.cpp 389 unsigned NewOpc = getPredForm(Opc);
391 if (NewOpc == 0) {
394 NewOpc = Hexagon::C2_not;
397 NewOpc = TargetOpcode::COPY;
424 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
HexagonRDFOpt.cpp 224 unsigned OpNum, NewOpc;
227 NewOpc = Hexagon::L2_loadri_io;
231 NewOpc = Hexagon::L2_loadrd_io;
235 NewOpc = Hexagon::V6_vL32b_ai;
239 NewOpc = Hexagon::S2_storeri_io;
243 NewOpc = Hexagon::S2_storerd_io;
247 NewOpc = Hexagon::V6_vS32b_ai;
273 MI.setDesc(HII.get(NewOpc));
HexagonCopyToCombine.cpp 874 unsigned NewOpc;
876 NewOpc = Hexagon::A2_combinew;
879 NewOpc = Hexagon::V6_vcombine;
883 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiMemAluCombiner.cpp 252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm());
255 assert(NewOpc != 0 && "Unknown merged node opcode");
259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsBranchExpansion.cpp 337 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
338 const MCInstrDesc &NewDesc = TII->get(NewOpc);
MipsInstructionSelector.cpp 450 // %LoadResult/%StoreSrc = NewOpc %BaseAddr(p0), 16_bit_signed_immediate
497 const unsigned NewOpc = selectLoadStoreOpCode(I, MRI);
498 if (NewOpc == I.getOpcode())
501 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineLICM.cpp 1239 unsigned NewOpc =
1244 if (NewOpc == 0) return nullptr;
1245 const MCInstrDesc &MID = TII->get(NewOpc);
TwoAddressInstructionPass.cpp 1206 unsigned NewOpc =
1211 if (NewOpc != 0) {
1212 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 684 unsigned NewOpc = Node->getOpcode();
687 if (NewOpc == ISD::FP_TO_UINT &&
689 NewOpc = ISD::FP_TO_SINT;
691 if (NewOpc == ISD::STRICT_FP_TO_UINT &&
693 NewOpc = ISD::STRICT_FP_TO_SINT;
698 Promoted = DAG.getNode(NewOpc, dl, {NVT, MVT::Other},
702 Promoted = DAG.getNode(NewOpc, dl, NVT, Node->getOperand(0));
709 NewOpc = ISD::AssertZext;
711 NewOpc = ISD::AssertSext;
713 Promoted = DAG.getNode(NewOpc, dl, NVT, Promoted
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 899 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
900 if (NewOpc == I.getOpcode())
902 I.setDesc(TII.get(NewOpc));
1095 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
1096 if (NewOpc == G_LOAD || NewOpc == G_STORE)
1099 if (ValSize == 1 && NewOpc == Opcodes.STORE8) {
1117 I.setDesc(TII.get(NewOpc));
1119 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH
    [all...]
ARMLoadStoreOptimizer.cpp 1346 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
1347 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1498 unsigned NewOpc;
1500 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1502 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1508 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1510 (!isAM5 && !isLegalAddressImm(NewOpc, Offset, TII))) {
1511 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1512 if (isAM5 || !isLegalAddressImm(NewOpc, Offset, TII))
1528 auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
    [all...]
ARMConstantIslandPass.cpp 1787 unsigned NewOpc = 0;
1794 NewOpc = ARM::tLEApcrel;
1801 NewOpc = ARM::tLDRpci;
1808 if (!NewOpc)
1821 U.MI->setDesc(TII->get(NewOpc));
1838 unsigned NewOpc = 0;
1844 NewOpc = ARM::tB;
1849 NewOpc = ARM::tBcc;
1854 if (NewOpc) {
1859 Br.MI->setDesc(TII->get(NewOpc));
    [all...]
ARMExpandPseudoInsts.cpp 1915 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq;
1916 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
1925 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq;
1926 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
1935 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq;
1937 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
1955 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2132 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD;
2133 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
2186 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16
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