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    Searched defs:Not (Results 1 - 14 of 14) sorted by relevancy

  /src/external/gpl3/gdb.old/dist/gdbsupport/
traits.h 16 along with this program. If not, see <http://www.gnu.org/licenses/>. */
58 /* Detect whether Op<Args...> is a valid type, use Default if not. */
96 struct Not : public std::integral_constant<bool, !Predicate::value>
  /src/external/apache2/llvm/dist/clang/include/clang/Analysis/Analyses/
ThreadSafetyLogical.h 27 Not
82 class Not : public LExpr {
86 Not(LExpr *Exp) : LExpr(LExpr::Not), Exp(Exp) {}
91 static bool classof(const LExpr *E) { return E->kind() == LExpr::Not; }
  /src/external/lgpl3/mpfr/dist/tests/
tget_sj.c 19 along with the GNU MPFR Library; see the file COPYING.LESSER. If not, see
313 const char *Not = s == 0 ? "" : " not";
323 "but the erange flag is%s set.\n", Not, Not);
tset_si.c 19 along with the GNU MPFR Library; see the file COPYING.LESSER. If not, see
74 PRINT_ERROR ("mpfr_set_ui_2exp and overflow (overflow flag not set)");
81 PRINT_ERROR ("mpfr_set_si_2exp (pos) and overflow (overflow flag not set)");
88 PRINT_ERROR ("mpfr_set_si_2exp (neg) and overflow (overflow flag not set)");
315 const char *Not = s == 0 ? "" : " not";
322 s, Not, Not);
394 j mod 1 != 0, i.e. the last two bits are not 00. */
461 /* FIXME: Comparing against mpfr_get_si/ui is not ideal, it'd be better t
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  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
ConstraintElimination.cpp 219 bool Not;
228 ConstraintOrBlock(DomTreeNode *DTN, CmpInst *Condition, bool Not)
230 Not(Not), Condition(Condition) {}
427 if (CB.Not && CI)
430 if (CB.Not) {
449 LLVM_DEBUG(dbgs() << "Adding " << *CB.Condition << " " << CB.Not << "\n");
461 DFSInStack.emplace_back(CB.NumIn, CB.NumOut, CB.Condition, CB.Not);
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
RISCVCompressInstEmitter.cpp 147 assert((R != nullptr) && "Register not defined!!");
156 // Only source instruction operands are allowed to not match Input Dag
168 // At this point either or both types are not registers, reject the pattern.
215 "' is not in register class '" +
230 "' which does not match the type '" +
328 " defined in Input Dag but not used in"
422 "' is not a 32 bit wide instruction!");
435 "' is not a 16 bit wide instruction!");
491 if (NotArg->getOperator()->getAsString() != "not" ||
678 StringRef Not = Op.first ? "!" : ""
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  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyFastISel.cpp 157 unsigned getRegForI1Value(const Value *V, bool &Not);
213 // another block, otherwise it may not have a virtual register assigned.
418 unsigned WebAssemblyFastISel::getRegForI1Value(const Value *V, bool &Not) {
422 Not = ICmp->isTrueWhenEqual();
428 Not = true;
432 Not = false;
448 // not a DAG ISel fallback.
911 bool Not;
912 unsigned CondReg = getRegForI1Value(Select->getCondition(), Not);
924 if (Not)
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  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineAddSub.cpp 60 // operators inevitably call FAddendCoef's constructor which is not cheap.
346 // Legend: A and B are not constant, C is constant
431 // Currently we are not able to handle vector type.
556 // Set null such that next iteration of the outer loop will not process
764 // ADD(XOR(OR(Z, NOT(C)), C)), 1) == NEG(AND(Z, C))
789 // X = XOR(Y, C1), Y = OR(Z, C2), C2 = NOT(C1) ==> X == NOT(AND(Z, C1))
795 // X = XOR(Y, C1), Y = AND(Z, C2), C2 == C1 ==> X == NOT(OR(Z, ~C1))
882 // add (sub X, Y), -1 --> add (not Y), X
916 // If wrapping is not allowed, then the addition must set the sign bit
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InstCombineAndOrXor.cpp 119 /// whether to treat V, Lo, and Hi as signed or not.
124 "Lo is not < Hi in range emission code!");
161 /// "Mixed" declares that (A & B) == C and C might or might not contain any
165 /// "Not" means that in above descriptions "==" should be replaced by "!=".
272 // vectors are not (yet?) supported. Don't support pointers either.
439 // 1. mask B covers only a single bit that's not covered by mask D, that is,
473 // covered by B but not D, in which case we can't deduce much from it, so
495 // D. If B is a superset of (or equal to) D, since E is not zero, LHS is
731 // This simplification is only valid if the upper range is not negative.
954 // Else, if it does not, then all is ok as-is
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 301 // Mips does not have i1 type, so use i32 for
399 // Operations not directly supported by Mips.
508 // These libcalls are not available in 32-bit.
550 // We do not generate PIC, the ABI is not O32, XGOT is being used.
641 // Returns Op if setcc is not a floating point comparison.
751 // Could not optimize.
815 // Return if the shifted mask does not start at bit 0 or the sum of its size
840 // SMSize is 'location' (position) in this case, not size.
905 // Return if the shift amount and the first bit position of mask are not th
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  /src/external/apache2/llvm/dist/llvm/utils/unittest/googlemock/include/gmock/
gmock-matchers.h 19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 // GOOGLETEST_CM0002 DO NOT DELETE
73 /* Symbol involving type with internal linkage not defined */)
114 // and MUST NOT BE USED IN USER CODE!!!
120 // class/struct templates to be partially specialized, but not
125 // Matcher but is not one yet; for example, Eq(value)) or a value (for
211 // Do not allow implicitly converting base*/& to derived*/&.
213 // Do not trigger if only one of them is a pointer. That implies a
214 // regular conversion and not a down_cast
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 43 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
365 // GPU does not have divrem function for signed or unsigned.
369 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
384 // The hardware supports 32-bit FSHR, but not FSHL.
387 // The hardware supports 32-bit ROTR, but not ROTL.
739 // Do not shrink an aligned scalar load to sub-dword.
822 // Negating a fma is not free if it has users without source mods.
842 // Packed operations do not have a fabs modifier.
925 // not profitable, and may actually be harmful.
962 llvm_unreachable("kernels should not be handled here")
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SIInstrInfo.cpp 82 /// operand \p Op, or if both nodes do not have this operand.
431 // If the mem ops (to be clustered) do not have the same base ptr, then they
432 // should not be clustered
439 // If only one base op is empty, they do not have the same base ptr
444 // loaded together by all clustered mem ops should not exceed 8. This is an
454 // (5) LoadSize >= 17: do not cluster
469 // This might be deprecated so it might not be worth that much effort to fix.
496 /// Handle copying from SGPR to AGPR, or from AGPR to AGPR. It is not possible
523 // Check that register source operand if not clobbered before MI.
1054 "Not a VGPR32 reg")
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 12 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
159 /// The worklist will not contain duplicates but may contain null entries
170 /// considered a new worklist entry. As we keep do not add duplicate nodes
177 /// which have not yet been combined to the worklist.
217 // Before we do any work, remove nodes that are not in use.
286 return; // Not in the worklist.
631 // chained stores that do not overlap and can be parallelized.
722 /// Returns 0 if there are not at least 2 consecutive stores to try merging.
763 /// legal (but not custom) after legalization.
777 assert(LHSTy.isInteger() && "Shift amount is not an integer type!")
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