HomeSort by: relevance | last modified time | path
    Searched defs:NumLanes (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIMachineFunctionInfo.cpp 260 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
288 unsigned NumLanes = Size / 4;
290 if (NumLanes > WaveSize)
298 for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
378 unsigned NumLanes = Size / 4;
379 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
407 for (unsigned I = 0; I < NumLanes; ++I) {
AMDGPURegisterBankInfo.cpp 1940 unsigned NumLanes = DstRegs.size();
1941 if (!NumLanes)
1942 NumLanes = 1;
1947 SmallVector<Register, 2> Res(NumLanes);
1948 for (unsigned L = 0; L < NumLanes; ++L)
1957 for (unsigned L = 0; L < NumLanes; ++L) {
1959 UnmergeToEltTy.getReg(I * NumLanes + L), Res[L]);
1968 for (unsigned L = 0; L < NumLanes; ++L) {
1969 Register DstReg = (NumLanes == 1) ? MI.getOperand(0).getReg() : DstRegs[L];
2025 unsigned NumLanes = InsRegs.size()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86ShuffleDecode.cpp 149 unsigned NumLanes = Size / 128;
150 if (NumLanes == 0) NumLanes = 1; // Handle MMX
151 unsigned NumLaneElts = NumElts / NumLanes;
220 unsigned NumLanes = (NumElts * ScalarBits) / 128;
221 if (NumLanes == 0) NumLanes = 1; // Handle MMX
222 unsigned NumLaneElts = NumElts / NumLanes;
236 unsigned NumLanes = (NumElts * ScalarBits) / 128;
237 if (NumLanes == 0 ) NumLanes = 1; // Handle MM
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InterleavedAccess.cpp 481 unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1);
482 unsigned NumLaneElts = NumElts / NumLanes;
X86MCInstLower.cpp 2225 int NumLanes = 1;
2226 // Override NumLanes for the broadcast instructions.
2228 case X86::VBROADCASTF128: NumLanes = 2; break;
2229 case X86::VBROADCASTI128: NumLanes = 2; break;
2230 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break;
2231 case X86::VBROADCASTF32X4rm: NumLanes = 4; break;
2232 case X86::VBROADCASTF32X8rm: NumLanes = 2; break;
2233 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break;
2234 case X86::VBROADCASTF64X2rm: NumLanes = 4; break;
2235 case X86::VBROADCASTF64X4rm: NumLanes = 2; break
    [all...]
X86InstCombineIntrinsic.cpp 449 unsigned NumLanes = ResTy->getPrimitiveSizeInBits() / 128;
454 unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes;
492 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
1954 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128;
1955 unsigned VWidthPerLane = VWidth / NumLanes;
1956 unsigned InnerVWidthPerLane = InnerVWidth / NumLanes;
1964 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
1979 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 1982 size_t NumLanes = Op.getSimpleValueType().getVectorNumElements();
1990 for (size_t i = 0; i < NumLanes; ++i) {
  /src/external/apache2/llvm/dist/llvm/lib/IR/
AutoUpgrade.cpp 2469 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128;
2471 unsigned ControlBitsMask = NumLanes - 1;
2472 unsigned NumControlBits = NumLanes / 2;
2475 for (unsigned l = 0; l != NumLanes; ++l) {
2478 if (l >= NumLanes / 2)
2479 LaneMask += NumLanes;
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
SLPVectorizer.cpp 938 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes;
1263 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes;
1301 unsigned NumLanes = VL.size();
1303 OpsVec[OpIdx].resize(NumLanes);
1304 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
1392 unsigned NumLanes = getNumLanes();
1451 for (unsigned Distance = 1; Distance != NumLanes; ++Distance) {
1455 if (Lane < 0 || Lane >= (int)NumLanes)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 12435 unsigned NumLanes = Op.getValueType().getVectorNumElements();
12436 switch (NumLanes) {
12508 unsigned NumLanes = Op.getValueType().getVectorNumElements();
12509 switch (NumLanes) {
16310 uint64_t NumLanes = ResVT.getVectorElementCount().getKnownMinValue();
16311 SDValue ExtIdx = DAG.getVectorIdxConstant(IdxConst * NumLanes, DL);
16327 uint64_t NumLanes =
16330 if ((TupleLanes % NumLanes) != 0)
16333 uint64_t NumVecs = TupleLanes / NumLanes;
16340 SDValue ExtIdx = DAG.getVectorIdxConstant(I * NumLanes, DL)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 15469 unsigned NumLanes = Op.getValueType().getVectorNumElements();
15470 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) {
15489 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
15527 unsigned NumLanes = Op.getValueType().getVectorNumElements();
15528 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) {
15547 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,

Completed in 126 milliseconds