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    Searched defs:NumOps (Results 1 - 25 of 53) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVMCInstLower.cpp 151 int NumOps = MI->getNumExplicitOperands();
158 if (RISCVII::hasVLOp(TSFlags) && OpNo == (NumOps - 2))
160 if (RISCVII::hasSEWOp(TSFlags) && OpNo == (NumOps - 1))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CallingConvLower.cpp 133 unsigned NumOps = Outs.size();
134 for (unsigned i = 0; i != NumOps; ++i) {
151 unsigned NumOps = ArgVTs.size();
152 for (unsigned i = 0; i != NumOps; ++i) {
MachineRegisterInfo.cpp 231 unsigned NumOps = MI->getNumOperands();
232 if (!(MO >= MO0 && MO < MO0+NumOps)) {
326 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
335 unsigned NumOps) {
336 assert(Src != Dst && NumOps && "Noop moveOperands");
340 if (Dst >= Src && Dst < Src + NumOps) {
342 Dst += NumOps - 1;
343 Src += NumOps - 1;
372 } while (--NumOps);
FixupStatepointCallerSaved.cpp 478 unsigned NumOps = MI.getNumOperands();
505 NewIndices.push_back(NumOps);
531 assert(NewIndices[OldDef] < NumOps);
MachineInstr.cpp 124 if (unsigned NumOps = MCID->getNumOperands() +
126 CapOperands = OperandCapacity::get(NumOps);
192 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
195 unsigned NumOps, MachineRegisterInfo *MRI) {
197 return MRI->moveOperands(Dst, Src, NumOps);
200 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
820 unsigned NumOps;
822 i += NumOps) {
827 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
828 if (i + NumOps > OpIdx)
    [all...]
TwoAddressInstructionPass.cpp 361 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
1320 unsigned NumOps = MI->getNumOperands();
1322 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCTargetDesc.cpp 142 unsigned NumOps = Inst.getNumOperands();
143 if (NumOps == 0)
145 switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
151 Target = Region + Inst.getOperand(NumOps - 1).getImm();
156 Target = Addr + Inst.getOperand(NumOps - 1).getImm();
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 202 unsigned NumOps = Node->getNumOperands();
203 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
204 Chain = Node->getOperand(NumOps-1);
ScheduleDAGFast.cpp 485 unsigned NumOps = Node->getNumOperands();
486 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
487 --NumOps; // Ignore the glue operand.
489 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
673 unsigned NumOps = N->getNumOperands();
674 if (unsigned NumLeft = NumOps) {
680 if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {
ScheduleDAGRRList.cpp 1365 unsigned NumOps = Node->getNumOperands();
1366 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1367 --NumOps; // Ignore the glue operand.
1369 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
2824 unsigned NumOps = MCID.getNumOperands() - NumRes;
2825 for (unsigned i = 0; i != NumOps; ++i) {
3069 unsigned NumOps = MCID.getNumOperands() - NumRes;
3070 for (unsigned j = 0; j != NumOps; ++j) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
GISelKnownBits.cpp 455 unsigned NumOps = MI.getNumOperands();
458 for (unsigned I = 0; I != NumOps - 1; ++I) {
469 unsigned NumOps = MI.getNumOperands();
470 Register SrcReg = MI.getOperand(NumOps - 1).getReg();
479 for (; DstIdx != NumOps - 1 && MI.getOperand(DstIdx).getReg() != R;
Utils.cpp 881 const unsigned NumOps = MI.getNumOperands();
882 for (unsigned I = 1; I != NumOps; ++I) {
897 const unsigned NumOps = MI.getNumOperands();
899 for (unsigned I = 1; I != NumOps; ++I) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonGenPredicate.cpp 374 unsigned NumOps = MI->getNumOperands();
375 for (unsigned i = 0; i < NumOps; ++i) {
411 NumOps = 2;
427 for (unsigned i = 1; i < NumOps; ++i) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 160 unsigned NumOps = N->getNumOperands();
171 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
176 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
221 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallFrameOptimization.cpp 563 unsigned NumOps = DefMov->getDesc().getNumOperands();
564 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
X86FloatingPoint.cpp 1121 unsigned NumOps = MI.getDesc().getNumOperands();
1122 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
1126 unsigned Reg = getFPReg(MI.getOperand(NumOps - 1));
1154 MI.RemoveOperand(NumOps - 1); // Remove explicit ST(0) operand
1182 unsigned NumOps = MI.getDesc().getNumOperands();
1183 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1530 unsigned NumOps = 0;
1535 i != e && MI.getOperand(i).isImm(); i += 1 + NumOps) {
1538 NumOps = InlineAsm::getNumOperandRegisters(Flags)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
AMDGPUEmitPrintf.cpp 223 auto NumOps = Args.size();
224 assert(NumOps >= 1);
231 Desc = appendString(Builder, Desc, Fmt, NumOps == 1);
236 for (unsigned int i = 1; i != NumOps; ++i) {
237 bool IsLast = i == NumOps - 1;
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenInstruction.cpp 81 unsigned NumOps = 1;
106 NumOps = NumArgs;
139 MIOperandNo, NumOps, MIOpInfo);
140 MIOperandNo += NumOps;
DAGISelMatcherEmitter.cpp 488 unsigned NumOps = cast<CheckPredicateMatcher>(N)->getNumOperands();
489 OS << "OPC_CheckPredicateWithOperands, " << NumOps << "/*#Ops*/, ";
490 for (unsigned i = 0; i < NumOps; ++i)
492 OperandBytes = 1 + NumOps;
953 unsigned NumOps = P.getNumOperands();
956 ++NumOps; // Get the chained node too.
961 OS << " Result.resize(NextRes+" << NumOps << ");\n";
979 for (unsigned i = 0; i != NumOps; ++i)
  /src/sys/external/bsd/acpica/dist/debugger/
dbdisply.c 427 UINT32 NumOps = 0;
467 NumOps++;
510 NumOps, NumOperators, NumOperands);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUPrintfRuntimeBinding.cpp 103 size_t NumOps) const {
156 unsigned NumOps = CI->getNumArgOperands();
198 getConversionSpecifiers(OpConvSpecifiers, Str, NumOps - 1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 817 unsigned NumOps = MCID.getNumOperands();
818 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
819 if (HasCC && MI->getOperand(NumOps-1).isDead())
839 unsigned NumOps = MCID.getNumOperands();
841 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
909 unsigned NumOps = MCID.getNumOperands();
910 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
911 if (HasCC && MI->getOperand(NumOps-1).isDead())
946 unsigned NumOps = MCID.getNumOperands();
948 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZTargetTransformInfo.cpp 1105 unsigned NumOps =
1109 if (((!Src->isVectorTy() && NumOps == 1) || ST->hasVectorEnhancements2()) &&
1127 NumOps *= 2;
1129 return NumOps;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h 1048 unsigned NumOps = Desc.getNumOperands();
1055 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
1059 if (NumOps == 8 &&
1065 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
1070 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
X86MCCodeEmitter.cpp 884 unsigned NumOps = Desc.getNumOperands();
1045 unsigned RcOperand = NumOps - 1;
1219 unsigned NumOps = MI.getNumOperands();
1223 for (unsigned i = CurOp; i != NumOps; ++i) {
1420 unsigned NumOps = Desc.getNumOperands();
1460 OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
1462 --NumOps; // Drop the operand from the end.
1553 --NumOps;
1802 if (CurOp != NumOps) {
1813 while (CurOp != NumOps && NumOps - CurOp <= 2)
    [all...]

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