1 /* $NetBSD: disasm_int.h,v 1.2 2016/08/05 16:45:50 scole Exp $ */ 2 3 /*- 4 * Copyright (c) 2000-2006 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: releng/10.1/sys/ia64/disasm/disasm_int.h 159916 2006-06-24 19:21:11Z marcel $ 29 */ 30 31 #ifndef _DISASM_INT_H_ 32 #define _DISASM_INT_H_ 33 34 #ifdef _DISASM_H_ 35 #error Include disasm_int.h before disasm.h 36 #endif 37 38 /* 39 * Instruction bundle specifics. 40 */ 41 #define TMPL_BITS 5 42 #define SLOT_BITS 41 43 #define SLOT_COUNT 3 44 45 #define BUNDLE_SIZE (SLOT_COUNT * SLOT_BITS + TMPL_BITS) 46 #define BUNDLE_BYTES ((BUNDLE_SIZE+7) >> 3) 47 #define TMPL_MASK ((1 << TMPL_BITS) - 1) 48 #define SLOT_MASK ((1ULL << SLOT_BITS) - 1ULL) 49 #define TMPL(p) (*(const uint8_t*)(p) & TMPL_MASK) 50 #define _U32(p,i) ((uint64_t)(((const uint32_t*)(p))[i])) 51 #define _SLOT(p,i) (_U32(p,i) | (_U32(p,(i)+1)<<32)) 52 #define SLOT(p,i) ((_SLOT(p,i) >> (TMPL_BITS+((i)<<3)+(i))) & SLOT_MASK) 53 54 /* 55 * Instruction specifics 56 */ 57 #define _FLD64(i,o,l) ((i >> o) & ((1LL << l) - 1LL)) 58 #define FIELD(i,o,l) ((uint32_t)_FLD64(i,o,l)) 59 #define OPCODE(i) FIELD(i, 37, 4) 60 #define QP_BITS 6 61 #define QP(i) FIELD(i, 0, QP_BITS) 62 #define REG_BITS 7 63 #define REG(i,r) FIELD(i, ((r) - 1) * REG_BITS + QP_BITS, REG_BITS) 64 65 /* 66 * Opcodes used internally as sentinels to denote either a lack of more 67 * specific information or to preserve the additional state/information 68 * we already have and need to pass around for later use. 69 */ 70 #define ASM_ADDITIONAL_OPCODES \ 71 ASM_OP_INTERNAL_OPCODES, \ 72 ASM_OP_BR_CALL, ASM_OP_BR_CEXIT, ASM_OP_BR_CLOOP, \ 73 ASM_OP_BR_COND, ASM_OP_BR_CTOP, ASM_OP_BR_IA, ASM_OP_BR_RET, \ 74 ASM_OP_BR_WEXIT, ASM_OP_BR_WTOP, \ 75 ASM_OP_BREAK_B, ASM_OP_BREAK_F, ASM_OP_BREAK_I, ASM_OP_BREAK_M, \ 76 ASM_OP_BREAK_X, \ 77 ASM_OP_BRL_COND, ASM_OP_BRL_CALL, \ 78 ASM_OP_BRP_, ASM_OP_BRP_RET, \ 79 ASM_OP_BSW_0, ASM_OP_BSW_1, \ 80 ASM_OP_CHK_A_CLR, ASM_OP_CHK_A_NC, ASM_OP_CHK_S, \ 81 ASM_OP_CHK_S_I, ASM_OP_CHK_S_M, \ 82 ASM_OP_CLRRRB_, ASM_OP_CLRRRB_PR, \ 83 ASM_OP_CMP_EQ, ASM_OP_CMP_EQ_AND, ASM_OP_CMP_EQ_OR, \ 84 ASM_OP_CMP_EQ_OR_ANDCM, ASM_OP_CMP_EQ_UNC, ASM_OP_CMP_GE_AND, \ 85 ASM_OP_CMP_GE_OR, ASM_OP_CMP_GE_OR_ANDCM, ASM_OP_CMP_GT_AND, \ 86 ASM_OP_CMP_GT_OR, ASM_OP_CMP_GT_OR_ANDCM, ASM_OP_CMP_LE_AND, \ 87 ASM_OP_CMP_LE_OR, ASM_OP_CMP_LE_OR_ANDCM, ASM_OP_CMP_LT, \ 88 ASM_OP_CMP_LT_AND, ASM_OP_CMP_LT_OR, ASM_OP_CMP_LT_OR_ANDCM, \ 89 ASM_OP_CMP_LT_UNC, ASM_OP_CMP_LTU, ASM_OP_CMP_LTU_UNC, \ 90 ASM_OP_CMP_NE_AND, ASM_OP_CMP_NE_OR, ASM_OP_CMP_NE_OR_ANDCM, \ 91 ASM_OP_CMP4_EQ, ASM_OP_CMP4_EQ_AND, ASM_OP_CMP4_EQ_OR, \ 92 ASM_OP_CMP4_EQ_OR_ANDCM, ASM_OP_CMP4_EQ_UNC, ASM_OP_CMP4_GE_AND,\ 93 ASM_OP_CMP4_GE_OR, ASM_OP_CMP4_GE_OR_ANDCM, ASM_OP_CMP4_GT_AND, \ 94 ASM_OP_CMP4_GT_OR, ASM_OP_CMP4_GT_OR_ANDCM, ASM_OP_CMP4_LE_AND, \ 95 ASM_OP_CMP4_LE_OR, ASM_OP_CMP4_LE_OR_ANDCM, ASM_OP_CMP4_LT, \ 96 ASM_OP_CMP4_LT_AND, ASM_OP_CMP4_LT_OR, ASM_OP_CMP4_LT_OR_ANDCM, \ 97 ASM_OP_CMP4_LT_UNC, ASM_OP_CMP4_LTU, ASM_OP_CMP4_LTU_UNC, \ 98 ASM_OP_CMP4_NE_AND, ASM_OP_CMP4_NE_OR, ASM_OP_CMP4_NE_OR_ANDCM, \ 99 ASM_OP_CMP8XCHG16_ACQ, ASM_OP_CMP8XCHG16_REL, \ 100 ASM_OP_CMPXCHG1_ACQ, ASM_OP_CMPXCHG1_REL, \ 101 ASM_OP_CMPXCHG2_ACQ, ASM_OP_CMPXCHG2_REL, \ 102 ASM_OP_CMPXCHG4_ACQ, ASM_OP_CMPXCHG4_REL, \ 103 ASM_OP_CMPXCHG8_ACQ, ASM_OP_CMPXCHG8_REL, \ 104 ASM_OP_CZX1_L, ASM_OP_CZX1_R, \ 105 ASM_OP_CZX2_L, ASM_OP_CZX2_R, \ 106 ASM_OP_DEP_, ASM_OP_DEP_Z, \ 107 ASM_OP_FC_, ASM_OP_FC_I, \ 108 ASM_OP_FCLASS_M, \ 109 ASM_OP_FCVT_FX, ASM_OP_FCVT_FX_TRUNC, ASM_OP_FCVT_FXU, \ 110 ASM_OP_FCVT_FXU_TRUNC, ASM_OP_FCVT_XF, \ 111 ASM_OP_FETCHADD4_ACQ, ASM_OP_FETCHADD4_REL, \ 112 ASM_OP_FETCHADD8_ACQ, ASM_OP_FETCHADD8_REL, \ 113 ASM_OP_FMA_, ASM_OP_FMA_D, ASM_OP_FMA_S, \ 114 ASM_OP_FMERGE_NS, ASM_OP_FMERGE_S, ASM_OP_FMERGE_SE, \ 115 ASM_OP_FMIX_L, ASM_OP_FMIX_LR, ASM_OP_FMIX_R, \ 116 ASM_OP_FMS_, ASM_OP_FMS_D, ASM_OP_FMS_S, \ 117 ASM_OP_FNMA_, ASM_OP_FNMA_D, ASM_OP_FNMA_S, \ 118 ASM_OP_FPCMP_EQ, ASM_OP_FPCMP_LE, ASM_OP_FPCMP_LT, \ 119 ASM_OP_FPCMP_NEQ, ASM_OP_FPCMP_NLE, ASM_OP_FPCMP_NLT, \ 120 ASM_OP_FPCMP_ORD, ASM_OP_FPCMP_UNORD, \ 121 ASM_OP_FPCVT_FX, ASM_OP_FPCVT_FX_TRUNC, ASM_OP_FPCVT_FXU, \ 122 ASM_OP_FPCVT_FXU_TRUNC, \ 123 ASM_OP_FPMERGE_NS, ASM_OP_FPMERGE_S, ASM_OP_FPMERGE_SE, \ 124 ASM_OP_FSWAP_, ASM_OP_FSWAP_NL, ASM_OP_FSWAP_NR, \ 125 ASM_OP_FSXT_L, ASM_OP_FSXT_R, \ 126 ASM_OP_GETF_D, ASM_OP_GETF_EXP, ASM_OP_GETF_S, ASM_OP_GETF_SIG, \ 127 ASM_OP_HINT_B, ASM_OP_HINT_F, ASM_OP_HINT_I, ASM_OP_HINT_M, \ 128 ASM_OP_HINT_X, \ 129 ASM_OP_INVALA_, ASM_OP_INVALA_E, \ 130 ASM_OP_ITC_D, ASM_OP_ITC_I, \ 131 ASM_OP_ITR_D, ASM_OP_ITR_I, \ 132 ASM_OP_LD1_, ASM_OP_LD1_A, ASM_OP_LD1_ACQ, ASM_OP_LD1_BIAS, \ 133 ASM_OP_LD1_C_CLR, ASM_OP_LD1_C_CLR_ACQ, ASM_OP_LD1_C_NC, \ 134 ASM_OP_LD1_S, ASM_OP_LD1_SA, \ 135 ASM_OP_LD16_, ASM_OP_LD16_ACQ, \ 136 ASM_OP_LD2_, ASM_OP_LD2_A, ASM_OP_LD2_ACQ, ASM_OP_LD2_BIAS, \ 137 ASM_OP_LD2_C_CLR, ASM_OP_LD2_C_CLR_ACQ, ASM_OP_LD2_C_NC, \ 138 ASM_OP_LD2_S, ASM_OP_LD2_SA, \ 139 ASM_OP_LD4_, ASM_OP_LD4_A, ASM_OP_LD4_ACQ, ASM_OP_LD4_BIAS, \ 140 ASM_OP_LD4_C_CLR, ASM_OP_LD4_C_CLR_ACQ, ASM_OP_LD4_C_NC, \ 141 ASM_OP_LD4_S, ASM_OP_LD4_SA, \ 142 ASM_OP_LD8_, ASM_OP_LD8_A, ASM_OP_LD8_ACQ, ASM_OP_LD8_BIAS, \ 143 ASM_OP_LD8_C_CLR, ASM_OP_LD8_C_CLR_ACQ, ASM_OP_LD8_C_NC, \ 144 ASM_OP_LD8_FILL, ASM_OP_LD8_S, ASM_OP_LD8_SA, \ 145 ASM_OP_LDF_FILL, \ 146 ASM_OP_LDF8_, ASM_OP_LDF8_A, ASM_OP_LDF8_C_CLR, \ 147 ASM_OP_LDF8_C_NC, ASM_OP_LDF8_S, ASM_OP_LDF8_SA, \ 148 ASM_OP_LDFD_, ASM_OP_LDFD_A, ASM_OP_LDFD_C_CLR, \ 149 ASM_OP_LDFD_C_NC, ASM_OP_LDFD_S, ASM_OP_LDFD_SA, \ 150 ASM_OP_LDFE_, ASM_OP_LDFE_A, ASM_OP_LDFE_C_CLR, \ 151 ASM_OP_LDFE_C_NC, ASM_OP_LDFE_S, ASM_OP_LDFE_SA, \ 152 ASM_OP_LDFP8_, ASM_OP_LDFP8_A, ASM_OP_LDFP8_C_CLR, \ 153 ASM_OP_LDFP8_C_NC, ASM_OP_LDFP8_S, ASM_OP_LDFP8_SA, \ 154 ASM_OP_LDFPD_, ASM_OP_LDFPD_A, ASM_OP_LDFPD_C_CLR, \ 155 ASM_OP_LDFPD_C_NC, ASM_OP_LDFPD_S, ASM_OP_LDFPD_SA, \ 156 ASM_OP_LDFPS_, ASM_OP_LDFPS_A, ASM_OP_LDFPS_C_CLR, \ 157 ASM_OP_LDFPS_C_NC, ASM_OP_LDFPS_S, ASM_OP_LDFPS_SA, \ 158 ASM_OP_LDFS_, ASM_OP_LDFS_A, ASM_OP_LDFS_C_CLR, \ 159 ASM_OP_LDFS_C_NC, ASM_OP_LDFS_S, ASM_OP_LDFS_SA, \ 160 ASM_OP_LFETCH_, ASM_OP_LFETCH_EXCL, ASM_OP_LFETCH_FAULT, \ 161 ASM_OP_LFETCH_FAULT_EXCL, \ 162 ASM_OP_MF_, ASM_OP_MF_A, \ 163 ASM_OP_MIX1_L, ASM_OP_MIX1_R, \ 164 ASM_OP_MIX2_L, ASM_OP_MIX2_R, \ 165 ASM_OP_MIX4_L, ASM_OP_MIX4_R, \ 166 ASM_OP_MOV_, ASM_OP_MOV_CPUID, ASM_OP_MOV_DBR, ASM_OP_MOV_I, \ 167 ASM_OP_MOV_IBR, ASM_OP_MOV_IP, ASM_OP_MOV_M, ASM_OP_MOV_MSR, \ 168 ASM_OP_MOV_PKR, ASM_OP_MOV_PMC, ASM_OP_MOV_PMD, ASM_OP_MOV_PR, \ 169 ASM_OP_MOV_PSR, ASM_OP_MOV_PSR_L, ASM_OP_MOV_PSR_UM, \ 170 ASM_OP_MOV_RET, ASM_OP_MOV_RR, \ 171 ASM_OP_NOP_B, ASM_OP_NOP_F, ASM_OP_NOP_I, ASM_OP_NOP_M, \ 172 ASM_OP_NOP_X, \ 173 ASM_OP_PACK2_SSS, ASM_OP_PACK2_USS, \ 174 ASM_OP_PACK4_SSS, \ 175 ASM_OP_PADD1_, ASM_OP_PADD1_SSS, ASM_OP_PADD1_UUS, \ 176 ASM_OP_PADD1_UUU, \ 177 ASM_OP_PADD2_, ASM_OP_PADD2_SSS, ASM_OP_PADD2_UUS, \ 178 ASM_OP_PADD2_UUU, \ 179 ASM_OP_PAVG1_, ASM_OP_PAVG1_RAZ, \ 180 ASM_OP_PAVG2_, ASM_OP_PAVG2_RAZ, \ 181 ASM_OP_PCMP1_EQ, ASM_OP_PCMP1_GT, \ 182 ASM_OP_PCMP2_EQ, ASM_OP_PCMP2_GT, \ 183 ASM_OP_PCMP4_EQ, ASM_OP_PCMP4_GT, \ 184 ASM_OP_PMAX1_U, \ 185 ASM_OP_PMIN1_U, \ 186 ASM_OP_PMPY2_L, ASM_OP_PMPY2_R, \ 187 ASM_OP_PMPYSHR2_, ASM_OP_PMPYSHR2_U, \ 188 ASM_OP_PROBE_R, ASM_OP_PROBE_R_FAULT, ASM_OP_PROBE_RW_FAULT, \ 189 ASM_OP_PROBE_W, ASM_OP_PROBE_W_FAULT, \ 190 ASM_OP_PSHR2_, ASM_OP_PSHR2_U, \ 191 ASM_OP_PSHR4_, ASM_OP_PSHR4_U, \ 192 ASM_OP_PSUB1_, ASM_OP_PSUB1_SSS, ASM_OP_PSUB1_UUS, \ 193 ASM_OP_PSUB1_UUU, \ 194 ASM_OP_PSUB2_, ASM_OP_PSUB2_SSS, ASM_OP_PSUB2_UUS, \ 195 ASM_OP_PSUB2_UUU, \ 196 ASM_OP_PTC_E, ASM_OP_PTC_G, ASM_OP_PTC_GA, ASM_OP_PTC_L, \ 197 ASM_OP_PTR_D, ASM_OP_PTR_I, \ 198 ASM_OP_SETF_EXP, ASM_OP_SETF_D, ASM_OP_SETF_S, ASM_OP_SETF_SIG, \ 199 ASM_OP_SHR_, ASM_OP_SHR_U, \ 200 ASM_OP_SRLZ_D, ASM_OP_SRLZ_I, \ 201 ASM_OP_ST1_, ASM_OP_ST1_REL, \ 202 ASM_OP_ST16_, ASM_OP_ST16_REL, \ 203 ASM_OP_ST2_, ASM_OP_ST2_REL, \ 204 ASM_OP_ST4_, ASM_OP_ST4_REL, \ 205 ASM_OP_ST8_, ASM_OP_ST8_REL, ASM_OP_ST8_SPILL, \ 206 ASM_OP_STF_SPILL, \ 207 ASM_OP_SYNC_I, \ 208 ASM_OP_TBIT_NZ_AND, ASM_OP_TBIT_NZ_OR, ASM_OP_TBIT_NZ_OR_ANDCM, \ 209 ASM_OP_TBIT_Z, ASM_OP_TBIT_Z_AND, ASM_OP_TBIT_Z_OR, \ 210 ASM_OP_TBIT_Z_OR_ANDCM, ASM_OP_TBIT_Z_UNC, \ 211 ASM_OP_TF_NZ_AND, ASM_OP_TF_NZ_OR, ASM_OP_TF_NZ_OR_ANDCM, \ 212 ASM_OP_TF_Z, ASM_OP_TF_Z_AND, ASM_OP_TF_Z_OR, \ 213 ASM_OP_TF_Z_OR_ANDCM, ASM_OP_TF_Z_UNC, \ 214 ASM_OP_TNAT_NZ_AND, ASM_OP_TNAT_NZ_OR, ASM_OP_TNAT_NZ_OR_ANDCM, \ 215 ASM_OP_TNAT_Z, ASM_OP_TNAT_Z_AND, ASM_OP_TNAT_Z_OR, \ 216 ASM_OP_TNAT_Z_OR_ANDCM, ASM_OP_TNAT_Z_UNC, \ 217 ASM_OP_UNPACK1_H, ASM_OP_UNPACK1_L, \ 218 ASM_OP_UNPACK2_H, ASM_OP_UNPACK2_L, \ 219 ASM_OP_UNPACK4_H, ASM_OP_UNPACK4_L, \ 220 ASM_OP_VMSW_0, ASM_OP_VMSW_1, \ 221 ASM_OP_XMA_H, ASM_OP_XMA_HU, ASM_OP_XMA_L, \ 222 ASM_OP_NUMBER_OF_OPCODES 223 224 #endif /* _DISASM_INT_H_ */ 225
Indexes created Sat Sep 20 22:09:52 GMT 2025