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      1 /*	$NetBSD: openpicreg.h,v 1.8 2008/01/17 23:42:58 garbled Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 /*
     30  * GLOBAL/TIMER register (IDU base + 0x1000)
     31  */
     32 
     33 /* feature reporting reg 0 */
     34 #define OPENPIC_FEATURE			0x1000
     35 
     36 /* global config reg 0 */
     37 #define OPENPIC_CONFIG			0x1020
     38 #define  OPENPIC_CONFIG_RESET			0x80000000
     39 #define  OPENPIC_CONFIG_8259_PASSTHRU_DISABLE	0x20000000
     40 
     41 /* interrupt configuration mode (direct or serial) */
     42 #define OPENPIC_ICR			0x1030
     43 #define  OPENPIC_ICR_SERIAL_MODE	(1 << 27)
     44 #define  OPENPIC_ICR_SERIAL_RATIO_MASK	(0x7 << 28)
     45 #define  OPENPIC_ICR_SERIAL_RATIO_SHIFT	28
     46 
     47 /* vendor ID */
     48 #define OPENPIC_VENDOR_ID		0x1080
     49 
     50 /* processor initialization reg */
     51 #define OPENPIC_PROC_INIT		0x1090
     52 
     53 /* IPI vector/priority reg */
     54 #define OPENPIC_IPI_VECTOR(ipi)		(0x10a0 + (ipi) * 0x10)
     55 
     56 /* spurious intr. vector */
     57 #define OPENPIC_SPURIOUS_VECTOR		0x10e0
     58 /* Timer frequency register */
     59 #define OPENPIC_TIMER_FREQ		0x10f0
     60 
     61 /* Timer current count register */
     62 #define OPENPIC_TIMER_CC(timer)		(0x1100 + (timer) * 0x40)
     63 /* Timer basecount register */
     64 #define OPENPIC_TIMER_BC(timer)		(0x1110 + (timer) * 0x40)
     65 /* Timer Vector/Priority register (uses imask,activity,priority and vector)*/
     66 #define OPENPIC_TIMER_VECTOR(timer)	(0x1120 + (timer) * 0x40)
     67 /* Timer destination register */
     68 #define OPENPIC_TIMER_DEST(timer)	(0x1130 + (timer) * 0x40)
     69 
     70 /*
     71  * INTERRUPT SOURCE register (IDU base + 0x10000)
     72  * ABOVE ONLY TRUE FOR NON-DISTRIBUTED OPENPICS!!
     73  */
     74 
     75 #define OPENPIC_DSRC_VECTOR_OFFSET(irq)		((irq) * 0x20)
     76 #define OPENPIC_DSRC_IDEST_OFFSET(irq)		((irq) * 0x20 + 0x10)
     77 
     78 
     79 /* interrupt vector/priority reg */
     80 #ifndef OPENPIC_SRC_VECTOR
     81 #define OPENPIC_SRC_VECTOR(irq)		(0x10000 + (irq) * 0x20)
     82 #endif
     83 #define  OPENPIC_SENSE_LEVEL			0x00400000
     84 #define  OPENPIC_SENSE_EDGE			0x00000000
     85 #define  OPENPIC_POLARITY_POSITIVE		0x00800000
     86 #define  OPENPIC_POLARITY_NEGATIVE		0x00000000
     87 #define  OPENPIC_IMASK				0x80000000
     88 #define  OPENPIC_ACTIVITY			0x40000000
     89 #define  OPENPIC_PRIORITY_MASK			0x000f0000
     90 #define  OPENPIC_PRIORITY_SHIFT			16
     91 #define  OPENPIC_VECTOR_MASK			0x000000ff
     92 
     93 /* interrupt destination CPU */
     94 #ifndef OPENPIC_IDEST
     95 #define OPENPIC_IDEST(irq)		(0x10010 + (irq) * 0x20)
     96 #endif
     97 
     98 /*
     99  * PROCESSOR register (IDU base + 0x20000)
    100  */
    101 
    102 /* IPI command reg */
    103 #define OPENPIC_IPI(cpu, ipi)		(0x20040 + (cpu) * 0x1000 + \
    104 					 (ipi) * 0x10)
    105 
    106 /* current task priority reg */
    107 #define OPENPIC_CPU_PRIORITY(cpu)	(0x20080 + (cpu) * 0x1000)
    108 #define  OPENPIC_CPU_PRIORITY_MASK		0x0000000f
    109 
    110 /* interrupt acknowledge reg */
    111 #define OPENPIC_IACK(cpu)		(0x200a0 + (cpu) * 0x1000)
    112 
    113 /* end of interrupt reg */
    114 #define OPENPIC_EOI(cpu)		(0x200b0 + (cpu) * 0x1000)
    115