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      1 /*	$NetBSD: orionreg.h,v 1.2 2013/09/28 05:46:51 kiyohara Exp $	*/
      2 /*
      3  * Copyright (c) 2007, 2008 KIYOHARA Takashi
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #ifndef _ORIONREG_H_
     29 #define _ORIONREG_H_
     30 
     31 #include <arm/marvell/mvsocreg.h>
     32 
     33 /*
     34  *        Ver  GbE SATA  USB  PCI PCIe IDMA XORE CESA
     35  * 1181:    1   -,   -,   -,   -,  x2,   ?,   -,   -
     36  * 1281:    2   -,   -,   -,   -,  x2,   ?,   -,   -
     37  * 5082:    1  x1,  x1,  x2,   -,  x1,   o,   -,   o
     38  * 5180N:   1  x1,   -,  x1,  x1,  x1,   o,   -,   -
     39  * 5181:    1  x1,   -,  x1,  x1,  x1,   o,   -,   o
     40  * 5182:    1  x1,  x1,  x2,  x1,  x1,   o,   o,   o
     41  * 5281:    2  x1,   -,  x1,  x1,  x1,   o,   -,   -
     42  * 6082:    1  x2?, x1,  x1,   -,  x1,   -,   -,   o
     43  * 6183:    1   ?,   -,  x?,   ?,   ?,   ?,   -,   -
     44  * 8660:    1  x1,   -,  x1,  x1,  x1,   o,   -,   -
     45  */
     46 
     47 #define ORION_UNITID_DDR		MVSOC_UNITID_DDR
     48 #define ORION_UNITID_DEVBUS		MVSOC_UNITID_DEVBUS
     49 #define ORION_UNITID_MLMB		MVSOC_UNITID_MLMB
     50 #define ORION_UNITID_PEX1		0x3			/* 1181 only */
     51 #define ORION_UNITID_PCI		0x3	/* PCI registers */
     52 #define ORION_UNITID_PEX		MVSOC_UNITID_PEX
     53 #define ORION_UNITID_USB0		0x5	/* USB registers Port0 */
     54 #define ORION_UNITID_IDMA		0x6	/* IDMA registers */
     55 #define ORION_UNITID_XOR		0x6	/* XOR registers */
     56 #define ORION_UNITID_GBE		0x7	/* Gigabit Ethernet registers */
     57 #define ORION_UNITID_SATA		0x8	/* SATA registers */
     58 #define ORION_UNITID_CRYPT		0x9	/* Cryptographic Engine reg */
     59 #define ORION_UNITID_SA			0x9	/* Security Accelerator reg */
     60 #define ORION_UNITID_USB1		0xa	/* USB registers Port1 */
     61 
     62 #define ORION_ATTR_DEVICE_CS0		0x1e
     63 #define ORION_ATTR_DEVICE_CS1		0x1d
     64 #define ORION_ATTR_DEVICE_CS2		0x1b
     65 #define ORION_ATTR_FLASH_CS		0x1b
     66 #define ORION_ATTR_BOOT_CS		0x0f
     67 #define ORION_ATTR_PEX_CFG		0x79	/* bug workaround ?? */
     68 #define ORION_ATTR_PEX_MEM		0x59
     69 #define ORION_ATTR_PEX_IO		0x51
     70 #define ORION_ATTR_PCI_MEM		0x59
     71 #define ORION_ATTR_PCI_IO		0x51
     72 #define ORION_ATTR_CRYPT		0x00
     73 
     74 /*
     75  * Interrupt numbers
     76  */
     77 #define ORION_IRQ_BRIDGE		0	/* Local to System Bridge */
     78 #define ORION_IRQ_HOST2CPU		1	/* Doorbell (Host-to-CPU) */
     79 #define ORION_IRQ_CPU2HOST		2	/* Doorbell (CPU-to-Host) */
     80 #define ORION_IRQ_UART0			3
     81 #define ORION_IRQ_UART1			4
     82 #define ORION_IRQ_TWSI			5	/* Two-Wire Serial Interface */
     83 #define ORION_IRQ_GPIO7_0		6	/* GPIO[7:0] */
     84 #define ORION_IRQ_GPIO15_8		7	/* GPIO[15:8] */
     85 #define ORION_IRQ_GPIO23_16		8	/* GPIO[23:16] not 1181 */
     86 #define ORION_IRQ_GPIO31_24		9	/* GPIO[31:24] not 1181 */
     87 #define ORION_IRQ_PEX0ERR		10	/* PCI Express error */
     88 #define ORION_IRQ_PEX0INT		11	/* PCIe INTA, B, C, D message */
     89 #define ORION_IRQ_PEX1ERR		12			/* 1181 only */
     90 #define ORION_IRQ_USBCNT1		12	/* USB Port1 controller (5182)*/
     91 #define ORION_IRQ_PEX1INT		13			/* 1181 only */
     92 #define ORION_IRQ_DEVERR		14	/* Device bus error */
     93 #define ORION_IRQ_PCIERR		15	/* PCI error */
     94 #define ORION_IRQ_USBBR			16	/* USB bridge Port0 or1 error */
     95 #define ORION_IRQ_USBCNT0		17	/* USB Port0 controller */
     96 #define ORION_IRQ_GBERX			18	/* GbE receive interrupt */
     97 #define ORION_IRQ_GBETX			19	/* GbE transmit interrupt */
     98 #define ORION_IRQ_GBEMISC		20	/* GbE miscellaneous intr */
     99 #define ORION_IRQ_GBESUM		21	/* GbE summary */
    100 #define ORION_IRQ_GBEERR		22	/* GbE error */
    101 #define ORION_IRQ_DMAERR		23	/* DMA or XOR error */
    102 #define ORION_IRQ_IDMA0			24	/* IDMA Channel0 completion */
    103 #define ORION_IRQ_IDMA1			25	/* IDMA Channel1 completion */
    104 #define ORION_IRQ_IDMA2			26	/* IDMA Channel2 completion */
    105 #define ORION_IRQ_IDMA3			27	/* IDMA Channel3 completion */
    106 #define ORION_IRQ_SECURITYINTR		28	/* Security accelerator intr */
    107 #define ORION_IRQ_SATAINTR		29	/* Serial-ATA interrupt */
    108 #define ORION_IRQ_XOR0			30	/* XOR engine 0 interrupt */
    109 #define ORION_IRQ_XOR1			31	/* XOR engine 1 interrupt */
    110 
    111 
    112 /*
    113  * Physical address of integrated peripherals
    114  */
    115 
    116 #define ORION_UNITID2PHYS(uid)	((ORION_UNITID_ ## uid) << 16)
    117 
    118 /*
    119  * Pin Multiplexing Interface Registers
    120  */
    121 #define ORION_PMI_BASE			(MVSOC_DEVBUS_BASE + 0x0000)
    122 #define ORION_PMI_SIZE			  0x100		/* XXXX */
    123 #define ORION_PMI_MPPCR0		   0x00
    124 #define ORION_PMI_MPPCR1		   0x04
    125 #define ORION_PMI_MPPCR2		   0x50
    126 #define ORION_PMI_DEVMULTICR		   0x08
    127 #define ORION_PMI_SAMPLE_AT_RESET	   0x10
    128 #define ORION_PMISMPL_ARMDDRCLK_MASK		0x0f
    129 #define ORION_PMISMPL_ARMDDRCLK_H_MASK		(1 << 23)
    130 #define ORION_PMISMPL_ARMDDRCLK_333_167		0x00
    131 #define ORION_PMISMPL_ARMDDRCLK_400_200		0x01
    132 #define ORION_PMISMPL_ARMDDRCLK_400_133		0x02
    133 #define ORION_PMISMPL_ARMDDRCLK_500_167		0x03
    134 #define ORION_PMISMPL_ARMDDRCLK_533_133		0x04
    135 #define ORION_PMISMPL_ARMDDRCLK_600_200		0x05
    136 #define ORION_PMISMPL_ARMDDRCLK_667_167		0x06
    137 #define ORION_PMISMPL_ARMDDRCLK_800_200		0x07
    138 #define ORION_PMISMPL_ARMDDRCLK_480_160		0x0c
    139 #define ORION_PMISMPL_ARMDDRCLK_550_183		0x0d
    140 #define ORION_PMISMPL_ARMDDRCLK_525_175		0x0e
    141 #define ORION_PMISMPL_ARMDDRCLK_466_233		0x11
    142 #define ORION_PMISMPL_ARMDDRCLK_500_250		0x12
    143 #define ORION_PMISMPL_ARMDDRCLK_533_266		0x13
    144 #define ORION_PMISMPL_ARMDDRCLK_600_300		0x14
    145 #define ORION_PMISMPL_ARMDDRCLK_450_150		0x15
    146 #define ORION_PMISMPL_ARMDDRCLK_533_178		0x16
    147 #define ORION_PMISMPL_ARMDDRCLK_575_192		0x17
    148 #define ORION_PMISMPL_ARMDDRCLK_700_175		0x18
    149 #define ORION_PMISMPL_ARMDDRCLK_733_183		0x19
    150 #define ORION_PMISMPL_ARMDDRCLK_750_187		0x1a
    151 #define ORION_PMISMPL_ARMDDRCLK_775_194		0x1b
    152 #define ORION_PMISMPL_ARMDDRCLK_500_125		0x1c
    153 #define ORION_PMISMPL_ARMDDRCLK_500_100		0x1d
    154 #define ORION_PMISMPL_ARMDDRCLK_600_150		0x1e
    155 #define ORION_PMISMPL_TCLK_MASK			0x3
    156 #define ORION_PMISMPL_TCLK_133			0x0
    157 #define ORION_PMISMPL_TCLK_150			0x1
    158 #define ORION_PMISMPL_TCLK_166			0x2
    159 
    160 /*
    161  * Mbus-L to Mbus Bridge Registers
    162  */
    163 /* CPU Address Map Registers */
    164 #define ORION_MLMB_NWINDOW		8
    165 #define ORION_MLMB_NREMAP		2
    166 
    167 /* Main Interrupt Controller Registers */
    168 #define ORION_MLMB_MICR			  0x200	/* Main Interrupt Cause reg */
    169 #define ORION_MLMB_MIRQIMR		  0x204	/* Main IRQ Interrupt Mask */
    170 #define ORION_MLMB_MFIQIMR		  0x208	/* Main FIQ Interrupt Mask */
    171 #define ORION_MLMB_EIMR			  0x20c	/* Endpoint Interrupt Mask */
    172 
    173 /*
    174  * PCI Express Interface Registers
    175  *   or PCI Interface Registers
    176  */
    177 #define ORION_PEX1_BASE		(ORION_UNITID2PHYS(PEX1))	/* 0x30000 */
    178 #define ORION_PCI_BASE		(ORION_UNITID2PHYS(PCI))	/* 0x30000 */
    179 
    180 /*
    181  * USB 2.0 Interface Registers
    182  */
    183 #define ORION_USB0_BASE		(ORION_UNITID2PHYS(USB0))	/* 0x50000 */
    184 #define ORION_USB1_BASE		(ORION_UNITID2PHYS(USB1))	/* 0xa0000 */
    185 
    186 /*
    187  * IDMA Controller and XOR Engine Registers
    188  */
    189 #define ORION_IDMAC_BASE	(ORION_UNITID2PHYS(IDMA))	/* 0x60000 */
    190 
    191 /*
    192  * Gigabit Ethernet Registers
    193  */
    194 #define ORION_GBE_BASE		(ORION_UNITID2PHYS(GBE))	/* 0x70000 */
    195 
    196 /*
    197  * Serial-ATA Host Controller (SATAHC) Registers
    198  */
    199 #define ORION_SATAHC_BASE	(ORION_UNITID2PHYS(SATA))	/* 0x80000 */
    200 
    201 /*
    202  * Cryptographic Engine and Security Accelerator Registers
    203  */
    204 #define ORION_CESA_BASE		(ORION_UNITID2PHYS(CRYPT) + 0xd000)/* 0x9d000 */
    205 
    206 #endif	/* _ORIONREG_H_ */
    207