1 /* $NetBSD: i2sreg.h,v 1.2 2025/09/08 08:06:19 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: i2sreg.h,v 1.2 2025/09/08 08:06:19 macallan Exp $"); 31 32 #ifndef I2SREG_H 33 #define I2SREG_H 34 35 /* I2S registers */ 36 #define I2S_INT 0x00 37 #define I2S_FORMAT 0x10 38 #define I2S_FRAMECOUNT 0x40 39 #define I2S_FRAMEMATCH 0x50 40 #define I2S_WORDSIZE 0x60 41 42 /* I2S_INT register definitions */ 43 #define I2S_INT_CLKSTOPPEND 0x01000000 /* clock-stop interrupt pending */ 44 45 /* I2S_WORDSIZE register definitions */ 46 #define INPUT_STEREO (2 << 24) 47 #define INPUT_MONO (1 << 24) 48 #define INPUT_16BIT (0 << 16) 49 #define INPUT_24BIT (3 << 16) 50 #define OUTPUT_STEREO (2 << 8) 51 #define OUTPUT_MONO (1 << 8) 52 #define OUTPUT_16BIT (0 << 0) 53 #define OUTPUT_24BIT (3 << 0) 54 55 /* I2S_FORMAT register definitions */ 56 #define CLKSRC_49MHz 0x80000000 /* Use 49152000Hz Osc. */ 57 #define CLKSRC_45MHz 0x40000000 /* Use 45158400Hz Osc. */ 58 #define CLKSRC_18MHz 0x00000000 /* Use 18432000Hz Osc. */ 59 #define MCLK_DIV 0x1f000000 /* MCLK = SRC / DIV */ 60 #define MCLK_DIV1 0x14000000 /* MCLK = SRC */ 61 #define MCLK_DIV3 0x13000000 /* MCLK = SRC / 3 */ 62 #define MCLK_DIV5 0x12000000 /* MCLK = SRC / 5 */ 63 #define SCLK_DIV 0x00f00000 /* SCLK = MCLK / DIV */ 64 #define SCLK_DIV1 0x00800000 65 #define SCLK_DIV3 0x00900000 66 #define SCLK_MASTER 0x00080000 /* Master mode */ 67 #define SCLK_SLAVE 0x00000000 /* Slave mode */ 68 #define SERIAL_FORMAT 0x00070000 69 #define SERIAL_SONY 0x00000000 70 #define SERIAL_64x 0x00010000 71 #define SERIAL_32x 0x00020000 72 #define SERIAL_DAV 0x00040000 73 #define SERIAL_SILICON 0x00050000 74 75 #endif
Indexes created Wed Sep 24 15:09:51 GMT 2025