1 /* $NetBSD: dce_transform.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-16 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef _DCE_DCE_TRANSFORM_H_ 29 #define _DCE_DCE_TRANSFORM_H_ 30 31 32 #include "transform.h" 33 34 #define TO_DCE_TRANSFORM(transform)\ 35 container_of(transform, struct dce_transform, base) 36 37 #define LB_TOTAL_NUMBER_OF_ENTRIES 1712 38 #define LB_BITS_PER_ENTRY 144 39 40 #define XFM_COMMON_REG_LIST_DCE_BASE(id) \ 41 SRI(LB_DATA_FORMAT, LB, id), \ 42 SRI(GAMUT_REMAP_CONTROL, DCP, id), \ 43 SRI(GAMUT_REMAP_C11_C12, DCP, id), \ 44 SRI(GAMUT_REMAP_C13_C14, DCP, id), \ 45 SRI(GAMUT_REMAP_C21_C22, DCP, id), \ 46 SRI(GAMUT_REMAP_C23_C24, DCP, id), \ 47 SRI(GAMUT_REMAP_C31_C32, DCP, id), \ 48 SRI(GAMUT_REMAP_C33_C34, DCP, id), \ 49 SRI(OUTPUT_CSC_C11_C12, DCP, id), \ 50 SRI(OUTPUT_CSC_C13_C14, DCP, id), \ 51 SRI(OUTPUT_CSC_C21_C22, DCP, id), \ 52 SRI(OUTPUT_CSC_C23_C24, DCP, id), \ 53 SRI(OUTPUT_CSC_C31_C32, DCP, id), \ 54 SRI(OUTPUT_CSC_C33_C34, DCP, id), \ 55 SRI(OUTPUT_CSC_CONTROL, DCP, id), \ 56 SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ 57 SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ 58 SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ 59 SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ 60 SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ 61 SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ 62 SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ 63 SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ 64 SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ 65 SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ 66 SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ 67 SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ 68 SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ 69 SRI(REGAMMA_LUT_INDEX, DCP, id), \ 70 SRI(REGAMMA_LUT_DATA, DCP, id), \ 71 SRI(REGAMMA_CONTROL, DCP, id), \ 72 SRI(DENORM_CONTROL, DCP, id), \ 73 SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \ 74 SRI(OUT_ROUND_CONTROL, DCP, id), \ 75 SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \ 76 SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \ 77 SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \ 78 SRI(SCL_MODE, SCL, id), \ 79 SRI(SCL_TAP_CONTROL, SCL, id), \ 80 SRI(SCL_CONTROL, SCL, id), \ 81 SRI(SCL_BYPASS_CONTROL, SCL, id), \ 82 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \ 83 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \ 84 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \ 85 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \ 86 SRI(SCL_COEF_RAM_SELECT, SCL, id), \ 87 SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \ 88 SRI(VIEWPORT_START, SCL, id), \ 89 SRI(VIEWPORT_SIZE, SCL, id), \ 90 SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \ 91 SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \ 92 SRI(SCL_HORZ_FILTER_INIT, SCL, id), \ 93 SRI(SCL_VERT_FILTER_INIT, SCL, id), \ 94 SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \ 95 SRI(LB_MEMORY_CTRL, LB, id), \ 96 SRI(SCL_UPDATE, SCL, id), \ 97 SRI(SCL_F_SHARP_CONTROL, SCL, id) 98 99 #define XFM_COMMON_REG_LIST_DCE80(id) \ 100 XFM_COMMON_REG_LIST_DCE_BASE(id), \ 101 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id) 102 103 #define XFM_COMMON_REG_LIST_DCE100(id) \ 104 XFM_COMMON_REG_LIST_DCE_BASE(id), \ 105 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \ 106 SRI(DCFE_MEM_PWR_STATUS, CRTC, id) 107 108 #define XFM_COMMON_REG_LIST_DCE110(id) \ 109 XFM_COMMON_REG_LIST_DCE_BASE(id), \ 110 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ 111 SRI(DCFE_MEM_PWR_STATUS, DCFE, id) 112 113 #define XFM_SF(reg_name, field_name, post_fix)\ 114 .field_name = reg_name ## __ ## field_name ## post_fix 115 116 #define XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 117 XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ 118 XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ 119 XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ 120 XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ 121 XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ 122 XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ 123 XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ 124 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ 125 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ 126 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ 127 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ 128 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ 129 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ 130 XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \ 131 XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ 132 XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ 133 XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ 134 XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ 135 XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ 136 XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ 137 XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ 138 XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ 139 XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ 140 XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ 141 XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ 142 XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ 143 XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ 144 XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ 145 XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ 146 XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ 147 XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ 148 XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ 149 XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ 150 XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ 151 XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ 152 XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ 153 XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ 154 XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ 155 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 156 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 157 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 158 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 159 XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ 160 XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ 161 XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \ 162 XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ 163 XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ 164 XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ 165 XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ 166 XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ 167 XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ 168 XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ 169 XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ 170 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ 171 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ 172 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ 173 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ 174 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ 175 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ 176 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ 177 XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ 178 XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ 179 XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ 180 XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ 181 XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ 182 XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ 183 XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ 184 XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ 185 XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ 186 XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ 187 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ 188 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ 189 XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ 190 XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ 191 XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ 192 XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh) 193 194 #define XFM_COMMON_MASK_SH_LIST_DCE80(mask_sh) \ 195 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 196 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ 197 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ 198 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) 199 200 #define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh) \ 201 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 202 XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ 203 XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ 204 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ 205 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ 206 XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ 207 XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) 208 209 #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ 210 XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ 211 XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ 212 XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ 213 XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ 214 XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ 215 XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ 216 XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ 217 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ 218 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ 219 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ 220 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ 221 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ 222 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ 223 XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \ 224 XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ 225 XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ 226 XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ 227 XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ 228 XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ 229 XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ 230 XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ 231 XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ 232 XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ 233 XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ 234 XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ 235 XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ 236 XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ 237 XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ 238 XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ 239 XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ 240 XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ 241 XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ 242 XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ 243 XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ 244 XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ 245 XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ 246 XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ 247 XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ 248 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 249 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 250 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 251 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 252 XFM_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ 253 XFM_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ 254 XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \ 255 XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ 256 XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ 257 XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ 258 XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ 259 XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ 260 XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ 261 XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ 262 XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ 263 XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ 264 XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ 265 XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ 266 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ 267 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ 268 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ 269 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ 270 XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ 271 XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ 272 XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ 273 XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ 274 XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ 275 XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ 276 XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ 277 XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ 278 XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ 279 XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ 280 XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ 281 XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ 282 XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ 283 XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ 284 XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ 285 XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \ 286 XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ 287 XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ 288 XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ 289 XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ 290 XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh) 291 292 #define XFM_REG_FIELD_LIST(type) \ 293 type OUT_CLAMP_MIN_B_CB; \ 294 type OUT_CLAMP_MAX_B_CB; \ 295 type OUT_CLAMP_MIN_G_Y; \ 296 type OUT_CLAMP_MAX_G_Y; \ 297 type OUT_CLAMP_MIN_R_CR; \ 298 type OUT_CLAMP_MAX_R_CR; \ 299 type OUT_ROUND_TRUNC_MODE; \ 300 type DCP_SPATIAL_DITHER_EN; \ 301 type DCP_SPATIAL_DITHER_MODE; \ 302 type DCP_SPATIAL_DITHER_DEPTH; \ 303 type DCP_FRAME_RANDOM_ENABLE; \ 304 type DCP_RGB_RANDOM_ENABLE; \ 305 type DCP_HIGHPASS_RANDOM_ENABLE; \ 306 type DENORM_MODE; \ 307 type PIXEL_DEPTH; \ 308 type PIXEL_EXPAN_MODE; \ 309 type GAMUT_REMAP_C11; \ 310 type GAMUT_REMAP_C12; \ 311 type GAMUT_REMAP_C13; \ 312 type GAMUT_REMAP_C14; \ 313 type GAMUT_REMAP_C21; \ 314 type GAMUT_REMAP_C22; \ 315 type GAMUT_REMAP_C23; \ 316 type GAMUT_REMAP_C24; \ 317 type GAMUT_REMAP_C31; \ 318 type GAMUT_REMAP_C32; \ 319 type GAMUT_REMAP_C33; \ 320 type GAMUT_REMAP_C34; \ 321 type GRPH_GAMUT_REMAP_MODE; \ 322 type OUTPUT_CSC_C11; \ 323 type OUTPUT_CSC_C12; \ 324 type OUTPUT_CSC_GRPH_MODE; \ 325 type DCP_REGAMMA_MEM_PWR_DIS; \ 326 type DCP_LUT_MEM_PWR_DIS; \ 327 type REGAMMA_LUT_LIGHT_SLEEP_DIS; \ 328 type DCP_LUT_LIGHT_SLEEP_DIS; \ 329 type REGAMMA_CNTLA_EXP_REGION_START; \ 330 type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \ 331 type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \ 332 type REGAMMA_CNTLA_EXP_REGION_END; \ 333 type REGAMMA_CNTLA_EXP_REGION_END_BASE; \ 334 type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \ 335 type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \ 336 type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \ 337 type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \ 338 type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \ 339 type DCP_REGAMMA_MEM_PWR_STATE; \ 340 type REGAMMA_LUT_MEM_PWR_STATE; \ 341 type REGAMMA_LUT_WRITE_EN_MASK; \ 342 type GRPH_REGAMMA_MODE; \ 343 type SCL_MODE; \ 344 type SCL_BYPASS_MODE; \ 345 type SCL_PSCL_EN; \ 346 type SCL_H_NUM_OF_TAPS; \ 347 type SCL_V_NUM_OF_TAPS; \ 348 type SCL_BOUNDARY_MODE; \ 349 type EXT_OVERSCAN_LEFT; \ 350 type EXT_OVERSCAN_RIGHT; \ 351 type EXT_OVERSCAN_TOP; \ 352 type EXT_OVERSCAN_BOTTOM; \ 353 type SCL_COEFF_MEM_PWR_DIS; \ 354 type SCL_COEFF_MEM_PWR_STATE; \ 355 type SCL_C_RAM_FILTER_TYPE; \ 356 type SCL_C_RAM_PHASE; \ 357 type SCL_C_RAM_TAP_PAIR_IDX; \ 358 type SCL_C_RAM_EVEN_TAP_COEF_EN; \ 359 type SCL_C_RAM_EVEN_TAP_COEF; \ 360 type SCL_C_RAM_ODD_TAP_COEF_EN; \ 361 type SCL_C_RAM_ODD_TAP_COEF; \ 362 type VIEWPORT_X_START; \ 363 type VIEWPORT_Y_START; \ 364 type VIEWPORT_HEIGHT; \ 365 type VIEWPORT_WIDTH; \ 366 type SCL_H_SCALE_RATIO; \ 367 type SCL_V_SCALE_RATIO; \ 368 type SCL_H_INIT_INT; \ 369 type SCL_H_INIT_FRAC; \ 370 type SCL_V_INIT_INT; \ 371 type SCL_V_INIT_FRAC; \ 372 type LB_MEMORY_CONFIG; \ 373 type LB_MEMORY_SIZE; \ 374 type SCL_V_2TAP_HARDCODE_COEF_EN; \ 375 type SCL_H_2TAP_HARDCODE_COEF_EN; \ 376 type SCL_COEF_UPDATE_COMPLETE; \ 377 type ALPHA_EN 378 379 struct dce_transform_shift { 380 XFM_REG_FIELD_LIST(uint8_t); 381 }; 382 383 struct dce_transform_mask { 384 XFM_REG_FIELD_LIST(uint32_t); 385 }; 386 387 struct dce_transform_registers { 388 uint32_t LB_DATA_FORMAT; 389 uint32_t GAMUT_REMAP_CONTROL; 390 uint32_t GAMUT_REMAP_C11_C12; 391 uint32_t GAMUT_REMAP_C13_C14; 392 uint32_t GAMUT_REMAP_C21_C22; 393 uint32_t GAMUT_REMAP_C23_C24; 394 uint32_t GAMUT_REMAP_C31_C32; 395 uint32_t GAMUT_REMAP_C33_C34; 396 uint32_t OUTPUT_CSC_C11_C12; 397 uint32_t OUTPUT_CSC_C13_C14; 398 uint32_t OUTPUT_CSC_C21_C22; 399 uint32_t OUTPUT_CSC_C23_C24; 400 uint32_t OUTPUT_CSC_C31_C32; 401 uint32_t OUTPUT_CSC_C33_C34; 402 uint32_t OUTPUT_CSC_CONTROL; 403 uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL; 404 uint32_t REGAMMA_CNTLA_START_CNTL; 405 uint32_t REGAMMA_CNTLA_SLOPE_CNTL; 406 uint32_t REGAMMA_CNTLA_END_CNTL1; 407 uint32_t REGAMMA_CNTLA_END_CNTL2; 408 uint32_t REGAMMA_CNTLA_REGION_0_1; 409 uint32_t REGAMMA_CNTLA_REGION_2_3; 410 uint32_t REGAMMA_CNTLA_REGION_4_5; 411 uint32_t REGAMMA_CNTLA_REGION_6_7; 412 uint32_t REGAMMA_CNTLA_REGION_8_9; 413 uint32_t REGAMMA_CNTLA_REGION_10_11; 414 uint32_t REGAMMA_CNTLA_REGION_12_13; 415 uint32_t REGAMMA_CNTLA_REGION_14_15; 416 uint32_t REGAMMA_LUT_WRITE_EN_MASK; 417 uint32_t REGAMMA_LUT_INDEX; 418 uint32_t REGAMMA_LUT_DATA; 419 uint32_t REGAMMA_CONTROL; 420 uint32_t DENORM_CONTROL; 421 uint32_t DCP_SPATIAL_DITHER_CNTL; 422 uint32_t OUT_ROUND_CONTROL; 423 uint32_t OUT_CLAMP_CONTROL_R_CR; 424 uint32_t OUT_CLAMP_CONTROL_G_Y; 425 uint32_t OUT_CLAMP_CONTROL_B_CB; 426 uint32_t SCL_MODE; 427 uint32_t SCL_TAP_CONTROL; 428 uint32_t SCL_CONTROL; 429 uint32_t SCL_BYPASS_CONTROL; 430 uint32_t EXT_OVERSCAN_LEFT_RIGHT; 431 uint32_t EXT_OVERSCAN_TOP_BOTTOM; 432 uint32_t SCL_VERT_FILTER_CONTROL; 433 uint32_t SCL_HORZ_FILTER_CONTROL; 434 uint32_t DCFE_MEM_PWR_CTRL; 435 uint32_t DCFE_MEM_PWR_STATUS; 436 uint32_t SCL_COEF_RAM_SELECT; 437 uint32_t SCL_COEF_RAM_TAP_DATA; 438 uint32_t VIEWPORT_START; 439 uint32_t VIEWPORT_SIZE; 440 uint32_t SCL_HORZ_FILTER_SCALE_RATIO; 441 uint32_t SCL_VERT_FILTER_SCALE_RATIO; 442 uint32_t SCL_HORZ_FILTER_INIT; 443 uint32_t SCL_VERT_FILTER_INIT; 444 uint32_t SCL_AUTOMATIC_MODE_CONTROL; 445 uint32_t LB_MEMORY_CTRL; 446 uint32_t SCL_UPDATE; 447 uint32_t SCL_F_SHARP_CONTROL; 448 }; 449 450 struct init_int_and_frac { 451 uint32_t integer; 452 uint32_t fraction; 453 }; 454 455 struct scl_ratios_inits { 456 uint32_t h_int_scale_ratio; 457 uint32_t v_int_scale_ratio; 458 struct init_int_and_frac h_init; 459 struct init_int_and_frac v_init; 460 }; 461 462 enum ram_filter_type { 463 FILTER_TYPE_RGB_Y_VERTICAL = 0, /* 0 - RGB/Y Vertical filter */ 464 FILTER_TYPE_CBCR_VERTICAL = 1, /* 1 - CbCr Vertical filter */ 465 FILTER_TYPE_RGB_Y_HORIZONTAL = 2, /* 1 - RGB/Y Horizontal filter */ 466 FILTER_TYPE_CBCR_HORIZONTAL = 3, /* 3 - CbCr Horizontal filter */ 467 FILTER_TYPE_ALPHA_VERTICAL = 4, /* 4 - Alpha Vertical filter. */ 468 FILTER_TYPE_ALPHA_HORIZONTAL = 5, /* 5 - Alpha Horizontal filter. */ 469 }; 470 471 struct dce_transform { 472 struct transform base; 473 const struct dce_transform_registers *regs; 474 const struct dce_transform_shift *xfm_shift; 475 const struct dce_transform_mask *xfm_mask; 476 477 const uint16_t *filter_v; 478 const uint16_t *filter_h; 479 const uint16_t *filter_v_c; 480 const uint16_t *filter_h_c; 481 int lb_pixel_depth_supported; 482 int lb_memory_size; 483 int lb_bits_per_entry; 484 bool prescaler_on; 485 }; 486 487 void dce_transform_construct(struct dce_transform *xfm_dce, 488 struct dc_context *ctx, 489 uint32_t inst, 490 const struct dce_transform_registers *regs, 491 const struct dce_transform_shift *xfm_shift, 492 const struct dce_transform_mask *xfm_mask); 493 494 bool dce_transform_get_optimal_number_of_taps( 495 struct transform *xfm, 496 struct scaler_data *scl_data, 497 const struct scaling_taps *in_taps); 498 499 void dce110_opp_set_csc_adjustment( 500 struct transform *xfm, 501 const struct out_csc_color_matrix *tbl_entry); 502 503 void dce110_opp_set_csc_default( 504 struct transform *xfm, 505 const struct default_adjustment *default_adjust); 506 507 /* REGAMMA RELATED */ 508 void dce110_opp_power_on_regamma_lut( 509 struct transform *xfm, 510 bool power_on); 511 512 void dce110_opp_program_regamma_pwl( 513 struct transform *xfm, 514 const struct pwl_params *params); 515 516 void dce110_opp_set_regamma_mode(struct transform *xfm, 517 enum opp_regamma mode); 518 519 #endif /* _DCE_DCE_TRANSFORM_H_ */ 520
Indexes created Sun Sep 21 19:09:51 GMT 2025