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    Searched defs:Odd (Results 1 - 7 of 7) sorted by relevancy

  /src/external/gpl3/gcc/dist/libgcc/config/alpha/
qrnnd.S 146 bne $6,$Odd
151 $Odd:
  /src/external/gpl3/gcc.old/dist/libgcc/config/alpha/
qrnnd.S 146 bne $6,$Odd
151 $Odd:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.h 310 // is an adjacent odd bit or vice versa.
314 uint64_t Odd = Mask & 0x5555555555555555ULL;
315 return countPopulation(Odd);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.cpp 309 static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd,
313 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
325 unsigned Odd;
328 Odd = 0;
331 Odd = 1;
342 // This register should preferably be even (Odd == 0) or odd (Odd == 1).
353 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
360 // Then prefer even or odd registers
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64InstPrinter.cpp 1267 unsigned Odd = MRI.getSubReg(Reg, Subo);
1268 O << getRegisterName(Even) << ", " << getRegisterName(Odd);
  /src/external/apache2/llvm/dist/llvm/lib/IR/
AutoUpgrade.cpp 3420 Value *Odd = Builder.CreateCall(FMA, Ops);
3425 std::swap(Even, Odd);
3431 Rep = Builder.CreateShuffleVector(Even, Odd, Idxs);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 9820 bool Odd = false;
9822 // the Odd pattern <1,3,5,...>.
9839 Odd = false;
9844 // Extracted values are either at Even indices <0,2,4,...> or at Odd
9852 Odd = true;
9857 Odd = false;
9861 if (Even || Odd) {
9869 if (Even && !Odd)
9872 if (Odd && !Even)
11320 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd element
    [all...]

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