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    Searched defs:Offset1 (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 243 int64_t Offset1, Offset2;
244 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
245 Offset1 == Offset2 ||
251 if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
252 Offsets.push_back(Offset1);
255 if (Offset2 < Offset1)
DAGCombiner.cpp 1005 // (load/store (add, (add, x, offset1), offset2)) ->
1006 // (load/store (add, x, offset1+offset2)).
1044 // Would x[offset1+offset2] still be a legal addressing mode?
15255 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
15261 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
15265 const APInt &Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
15275 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
15276 else CNV = CNV - Offset1;
17385 int64_t Offset1 = LoadNodes[1].OffsetFromBase;
17387 if (Offset0 - Offset1 == ElementSizeBytes &
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 203 int64_t Offset1 = 0;
209 Ptr1 = GetPointerBaseWithConstantOffset(BaseVal1, Offset1, DL, true);
211 return CheckOffsets(Offset0, Offset1);
221 Offset1 = MF.getFrameInfo().getObjectOffset(FS1->getFrameIndex());
222 return CheckOffsets(Offset0, Offset1);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
ConstraintElimination.cpp 131 int64_t Offset1 = 0;
179 Offset1 = ADec[0].first;
181 Offset1 *= -1;
201 R[0] = Offset1 + Offset2 + (Pred == CmpInst::ICMP_ULT ? -1 : 0);
SeparateConstOffsetFromGEP.cpp 1351 Value *Offset1 = First->getOperand(1);
1354 Second->setOperand(1, Offset1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSubtarget.cpp 360 int64_t Offset1;
362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
368 if (((Offset0 ^ Offset1) & 0x18) != 0)
  /src/external/apache2/llvm/dist/llvm/tools/llvm-profgen/
ProfiledBinary.cpp 120 uint64_t Offset1 = virtualAddrToOffset(Address1);
122 const FrameLocationStack &Context1 = getFrameLocationStack(Offset1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MicroMipsSizeReduction.cpp 400 int64_t Offset1, Offset2;
401 if (!GetImm(MI1, 2, Offset1))
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2)));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachinePipeliner.cpp 775 int64_t Offset1, Offset2;
777 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1,
783 (int)Offset1 < (int)Offset2) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 1269 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) |
1273 Offset1 |= (CountDw - 1) << 6;
1275 unsigned Offset = Offset0 | (Offset1 << 8);
3793 int64_t Offset1,
3795 if (Offset0 % Size != 0 || Offset1 % Size != 0)
3797 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size))
SIInstrInfo.cpp 131 int64_t &Offset1) const {
167 Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue();
192 Offset1 = Load1Offset->getZExtValue();
225 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
274 // The 2 offset instructions use offset0 and offset1 instead. We can treat
280 getNamedOperand(LdSt, AMDGPU::OpName::offset1);
283 unsigned Offset1 = Offset1Op->getImm();
284 if (Offset0 + 1 != Offset1)
471 int64_t Offset0, int64_t Offset1,
473 assert(Offset1 > Offset0 &
    [all...]
SIISelLowering.cpp 6847 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) |
6851 Offset1 |= (CountDw - 1) << 6;
6853 unsigned Offset = Offset0 | (Offset1 << 8);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 12751 int64_t Offset1 = 0, Offset2 = 0;
12752 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
12754 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
12760 Offset1 = 0;
12762 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
12765 return Offset1 == (Offset2 + Dist*Bytes);

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