HomeSort by: relevance | last modified time | path
    Searched defs:Op1 (Results 1 - 25 of 114) sorted by relevancy

1 2 3 4 5

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ExpandImm.h 24 uint64_t Op1;
SVEIntrinsicOpts.cpp 289 IntrinsicInst *Op1 = dyn_cast<IntrinsicInst>(I->getArgOperand(0));
292 if (Op1 && Op2 &&
293 Op1->getIntrinsicID() == Intrinsic::aarch64_sve_convert_to_svbool &&
295 Op1->getArgOperand(0)->getType() == Op2->getArgOperand(0)->getType()) {
297 Value *Ops[] = {Op1->getArgOperand(0), Op2->getArgOperand(0)};
298 Type *Tys[] = {Op1->getArgOperand(0)->getType()};
306 if (Op1->use_empty())
307 Op1->eraseFromParent();
308 if (Op1 != Op2 && Op2->use_empty())
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/MCTargetDesc/
BPFMCCodeEmitter.cpp 169 const MCOperand Op1 = MI.getOperand(MemOpStartIndex);
170 assert(Op1.isReg() && "First operand is not register.");
171 Encoding = MRI.getEncodingValue(Op1.getReg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelDAGToDAG.cpp 253 SDValue Op0, Op1, AluOp;
258 if (!selectAddrRr(Op, Op0, Op1, AluOp) &&
259 !selectAddrRi(Op, Op0, Op1, AluOp))
265 OutOps.push_back(Op1);
LanaiMemAluCombiner.cpp 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
171 if (Op1.getType() != Op2.getType())
174 switch (Op1.getType()) {
176 return Op1.getReg() == Op2.getReg();
178 return Op1.getImm() == Op2.getImm();
293 MachineOperand &Op1 = AluIter->getOperand(1);
298 if (!isSameOperand(Dest, Base) || !isSameOperand(Dest, Op1))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
LanaiMCCodeEmitter.cpp 189 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
193 assert(Op1.isReg() && "First operand is not register.");
199 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18);
221 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
225 assert(Op1.isReg() && "First operand is not register.");
226 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15);
260 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
264 assert(Op1.isReg() && "First operand is not register.");
270 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/
SparcInstPrinter.cpp 152 const MCOperand &Op1 = MI->getOperand(opNum);
156 if (Op1.isReg() && Op1.getReg() != SP::G0) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyPeephole.cpp 156 MachineOperand &Op1 = MI.getOperand(1);
157 if (Op1.isSymbol()) {
158 StringRef Name(Op1.getSymbolName());
WebAssemblyMemIntrinsicResults.cpp 154 MachineOperand &Op1 = MI.getOperand(1);
155 if (!Op1.isSymbol())
158 StringRef Name(Op1.getSymbolName());
  /src/external/apache2/llvm/dist/llvm/lib/IR/
ProfileSummary.cpp 165 ConstantAsMetadata *Op1 =
170 if (!Op0 || !Op1 || !Op2)
173 cast<ConstantInt>(Op1->getValue())->getZExtValue(),
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFAdjustOpt.cpp 120 Value *Op0, *Op1;
121 // Use LogicalOr (accept `or i1` as well as `select i1 Op0, true, Op1`)
122 if (!match(&I, m_LogicalOr(m_Value(Op0), m_Value(Op1))))
127 auto *Icmp2 = dyn_cast<ICmpInst>(Op1);
BPFMISimplifyPatchable.cpp 94 const MachineOperand *Op1 = &Inst->getOperand(1);
96 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCMacroFusion.cpp 70 const MachineOperand &Op1 = FirstMI.getOperand(FirstMIOpIndex);
72 if (!Op1.isReg() || !Op2.isReg())
75 return Op1.getReg() == Op2.getReg();
PPCBranchCoalescing.cpp 341 const MachineOperand &Op1 = OpList1[i];
344 LLVM_DEBUG(dbgs() << "Op1: " << Op1 << "\n"
347 if (Op1.isIdenticalTo(Op2)) {
349 if (Op1.isReg() &&
350 Register::isPhysicalRegister(Op1.getReg())
353 && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) {
357 LLVM_DEBUG(dbgs() << "Op1 and Op2 are identical!\n");
364 if (Op1.isReg() && Op2.isReg() &
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrBuilder.h 104 const MachineOperand &Op1 = MI->getOperand(Operand + 1);
105 AM.Scale = Op1.getImm();
X86RegisterBankInfo.cpp 214 auto &Op1 = MI.getOperand(1);
216 const LLT Ty1 = MRI.getType(Op1.getReg());
243 auto &Op1 = MI.getOperand(1);
245 const LLT Ty1 = MRI.getType(Op1.getReg());
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
BypassSlowDivision.cpp 89 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
203 Value *Op1 = I->getOperand(1);
204 ConstantInt *C = dyn_cast<ConstantInt>(Op1);
205 if (!C && isa<BitCastInst>(Op1))
206 C = dyn_cast<ConstantInt>(cast<BitCastInst>(Op1)->getOperand(0));
330 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) {
331 assert((Op1 || Op2) && "Nothing to check");
336 if (Op1 && Op2)
337 OrV = Builder.CreateOr(Op1, Op2);
339 OrV = Op1 ? Op1 : Op2
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ExpandVectorPredication.cpp 224 Value *Op1 = VPI.getOperand(1);
241 Op1 = Builder.CreateSelect(Mask, Op1, SafeDivisor);
245 Value *NewBinOp = Builder.CreateBinOp(OC, Op0, Op1, VPI.getName());
  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/
DWARFDebugFrame.cpp 261 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK;
265 addInstruction(Primary, Op1);
268 addInstruction(Primary, Op1, Data.getULEB128(C));
325 uint64_t op1 = Data.getULEB128(C); local
327 addInstruction(Opcode, op1, op2);
335 uint64_t op1 = Data.getULEB128(C); local
337 addInstruction(Opcode, op1, op2);
  /src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/Interpreter/
Execution.cpp 2065 GenericValue Op1 = getOperandValue(CE->getOperand(1), SF);
2069 case Instruction::Add: Dest.IntVal = Op0.IntVal + Op1.IntVal; break;
2070 case Instruction::Sub: Dest.IntVal = Op0.IntVal - Op1.IntVal; break;
2071 case Instruction::Mul: Dest.IntVal = Op0.IntVal * Op1.IntVal; break;
2072 case Instruction::FAdd: executeFAddInst(Dest, Op0, Op1, Ty); break;
2073 case Instruction::FSub: executeFSubInst(Dest, Op0, Op1, Ty); break;
2074 case Instruction::FMul: executeFMulInst(Dest, Op0, Op1, Ty); break;
2075 case Instruction::FDiv: executeFDivInst(Dest, Op0, Op1, Ty); break;
2076 case Instruction::FRem: executeFRemInst(Dest, Op0, Op1, Ty); break;
2077 case Instruction::SDiv: Dest.IntVal = Op0.IntVal.sdiv(Op1.IntVal); break
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/
AArch64BaseInfo.cpp 134 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
142 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
145 Ops[2].getAsInteger(10, Op1);
149 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
157 uint32_t Op1 = (Bits >> 11) & 0x7;
162 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/
BPFAsmParser.cpp 269 BPFOperand &Op1 = (BPFOperand &)*Operands[1];
272 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg()
273 && Op1.getToken() == "="
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelDAGToDAG.cpp 284 SDValue Op0, Op1;
288 if (!SelectAddr(Op, Op0, Op1))
294 OutOps.push_back(Op1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 380 SDValue Op0, Op1;
385 if (!SelectADDRrr(Op, Op0, Op1))
386 SelectADDRri(Op, Op0, Op1);
391 OutOps.push_back(Op1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZTDC.cpp 296 Value *Op0, *Op1;
300 std::tie(Op1, Mask1, Worthy1) = ConvertedInsts[cast<Instruction>(I.getOperand(1))];
301 if (Op0 != Op1)

Completed in 112 milliseconds

1 2 3 4 5