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    Searched defs:Op2 (Results 1 - 25 of 66) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ExpandImm.h 25 uint64_t Op2;
SVEIntrinsicOpts.cpp 290 IntrinsicInst *Op2 = dyn_cast<IntrinsicInst>(I->getArgOperand(1));
292 if (Op1 && Op2 &&
294 Op2->getIntrinsicID() == Intrinsic::aarch64_sve_convert_to_svbool &&
295 Op1->getArgOperand(0)->getType() == Op2->getArgOperand(0)->getType()) {
297 Value *Ops[] = {Op1->getArgOperand(0), Op2->getArgOperand(0)};
308 if (Op1 != Op2 && Op2->use_empty())
309 Op2->eraseFromParent();
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/MCTargetDesc/
BPFMCCodeEmitter.cpp 173 MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1);
174 assert(Op2.isImm() && "Second operand is not immediate.");
175 Encoding |= Op2.getImm() & 0xffff;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
LanaiMCCodeEmitter.cpp 142 const MCOperand Op2 = Inst.getOperand(2);
145 ((Op2.isImm() && Op2.getImm() != 0) ||
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/
SparcInstPrinter.cpp 153 const MCOperand &Op2 = MI->getOperand(opNum + 1);
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) ||
165 (Op2.isImm() && Op2.getImm() == 0));
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyPeephole.cpp 164 const auto &Op2 = MI.getOperand(2);
165 if (!Op2.isReg())
170 Register NewReg = Op2.getReg();
  /src/external/apache2/llvm/dist/llvm/lib/IR/
ProfileSummary.cpp 167 ConstantAsMetadata *Op2 =
170 if (!Op0 || !Op1 || !Op2)
174 cast<ConstantInt>(Op2->getValue())->getZExtValue());
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFMISimplifyPatchable.cpp 95 const MachineOperand *Op2 = &Inst->getOperand(2);
96 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCMacroFusion.cpp 71 const MachineOperand &Op2 = SecondMI.getOperand(SecondMIOpIndex);
72 if (!Op1.isReg() || !Op2.isReg())
75 return Op1.getReg() == Op2.getReg();
PPCBranchCoalescing.cpp 342 const MachineOperand &Op2 = OpList2[i];
345 << "Op2: " << Op2 << "\n");
347 if (Op1.isIdenticalTo(Op2)) {
357 LLVM_DEBUG(dbgs() << "Op1 and Op2 are identical!\n");
364 if (Op1.isReg() && Op2.isReg() &&
366 Register::isVirtualRegister(Op2.getReg())) {
368 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrBuilder.h 107 const MachineOperand &Op2 = MI->getOperand(Operand + 2);
108 AM.IndexReg = Op2.getReg();
X86OptimizeLEAs.cpp 404 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp);
406 assert(isSimilarDispOp(Op1, Op2) &&
414 return Op1.isImm() ? Op1.getImm() - Op2.getImm()
415 : Op1.getOffset() - Op2.getOffset();
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/
AArch64BaseInfo.cpp 134 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
142 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
148 Ops[5].getAsInteger(10, Op2);
149 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
160 uint32_t Op2 = Bits & 0x7;
163 utostr(CRm) + "_" + utostr(Op2);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIOptimizeExecMaskingPreRA.cpp 156 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1);
157 if (Op1->isImm() && Op2->isReg())
158 std::swap(Op1, Op2);
159 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)
172 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1);
174 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
175 Op1->getImm() != 0 || Op2->getImm() != 1)
SIPreEmitPeephole.cpp 108 MachineOperand &Op2 = A->getOperand(2);
109 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
115 if (Op2.isImm() && !(Op2.getImm() == -1 || Op2.getImm() == 0))
120 if (Op2.isReg()) {
121 SReg = Op2.getReg();
137 if (!ReadsSreg && Op2.isKill()) {
141 } else if (Op2.isImm())
    [all...]
AMDGPUInstCombineIntrinsic.cpp 874 Value *Op2 = II.getArgOperand(2);
881 // It's tempting to just return Op2 here, but that would give the wrong
882 // result if Op2 was -0.0.
884 auto *FAdd = IC.Builder.CreateFAddFMF(Zero, Op2, &II);
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/
BPFAsmParser.cpp 270 BPFOperand &Op2 = (BPFOperand &)*Operands[2];
272 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg()
274 && (Op2.getToken() == "-" || Op2.getToken() == "be16"
275 || Op2.getToken() == "be32" || Op2.getToken() == "be64"
276 || Op2.getToken() == "le16" || Op2.getToken() == "le32"
277 || Op2.getToken() == "le64")
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonNewValueJump.cpp 251 const MachineOperand &Op2 = MI.getOperand(2);
252 if (!Op2.isImm())
255 int64_t v = Op2.getImm();
HexagonRegisterInfo.cpp 308 const auto &Op2 = BI.getOperand(2);
309 if (!Op2.isImm() || Op2.getImm() != RealOffset)
HexagonSplitDouble.cpp 345 const MachineOperand &Op2 = MI->getOperand(2);
347 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0;
728 MachineOperand &Op2 = MI->getOperand(2);
745 if (!Op2.isReg()) {
747 .add(Op2);
750 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
780 MachineOperand &Op2 = MI->getOperand(2)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiMemAluCombiner.cpp 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
171 if (Op1.getType() != Op2.getType())
176 return Op1.getReg() == Op2.getReg();
178 return Op1.getImm() == Op2.getImm();
294 MachineOperand &Op2 = AluIter->getOperand(2);
301 if (Op2.isImm()) {
312 // Check that the Op2 would fit in the immediate field of the
314 ((IsSpls && isInt<10>(Op2.getImm())) ||
315 (!IsSpls && isInt<16>(Op2.getImm())))) ||
316 Offset.getImm() == Op2.getImm())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/
XCoreDisassembler.cpp 240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
253 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
268 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
346 unsigned Op1, Op2;
347 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
352 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
359 unsigned Op1, Op2;
360 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
365 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 346 const MachineOperand &Op2 = I->getOperand(2);
348 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
374 unsigned N = Op2.getImm();
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 918 SDValue Op2 = Node->getOperand(2);
921 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
960 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
967 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
968 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
1174 SDValue Op2 = Node->getOperand(2);
1202 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64InstPrinter.cpp 77 const MCOperand &Op2 = MI->getOperand(2);
82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
118 if (Op2.isImm() && Op3.isImm()) {
121 int64_t immr = Op2.getImm();
152 if (Op2.getImm() > Op3.getImm()) {
155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
170 const MCOperand &Op2 = MI->getOperand(2)
    [all...]

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