HomeSort by: relevance | last modified time | path
    Searched defs:Op4 (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/
XCoreDisassembler.cpp 647 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
652 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
656 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
681 unsigned Op1, Op2, Op3, Op4, Op5;
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
691 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
707 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
710 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
721 unsigned Op4 = fieldFromInstruction(Insn, 16, 4)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelDAGToDAG.cpp 1609 SDValue Op4 = Node->getOperand(4);
1611 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 5974 SDValue Op0, Op1, Op2, Op3, Op4;
5982 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
5991 OutOps.push_back(Op4);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp 1982 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4));
1984 Op2, Op3, Op4),
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 4842 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]);
4844 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) {
4846 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm());
4863 return Error(Op4.getStartLoc(),
4875 return Error(Op4.getStartLoc(),
4885 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext());
4906 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]);
4908 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) {
4910 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 6623 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
6624 if (!Op3.isReg() || !Op4.isReg())
6628 auto Op4Reg = Op4.getReg();
6663 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
6672 LastOp = &Op4;
6693 std::swap(Op4, Op5);

Completed in 51 milliseconds