| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| ReplaceConstant.cpp | 24 unsigned OpCode = CE->getOpcode();
25 switch (OpCode) {
49 Builder.CreateBinOp((Instruction::BinaryOps)OpCode, CE->getOperand(0),
65 Builder.CreateCast((Instruction::CastOps)OpCode, CE->getOperand(0),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 88 llvm_unreachable("Unexpected Opcode");
124 llvm_unreachable("Unexpected Opcode");
157 llvm_unreachable("Unexpected Opcode");
168 unsigned OpCode = MI.getOpcode();
171 if (OpCode==XCore::STWFI) {
181 switch (OpCode) {
201 llvm_unreachable("Unexpected Opcode");
|
| /src/external/apache2/llvm/dist/llvm/bindings/python/llvm/ |
| core.py | 26 "OpCode",
84 class OpCode(LLVMEnumeration):
85 """Represents an individual OpCode enumeration."""
90 super(OpCode, self).__init__(name, value)
427 def opcode(self): member in class:Instruction
428 return OpCode.from_value(lib.LLVMGetInstructionOpcode(self))
608 (OpCode, enumerations.OpCodes),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 882 unsigned OpCode = MI->getOpcode();
883 switch (OpCode) {
|
| X86MCInstLower.cpp | 319 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
336 Inst.setOpcode(Opcode);
370 unsigned Opcode) {
415 Inst.setOpcode(Opcode);
459 static unsigned convertTailJumpOpcode(unsigned Opcode) {
460 switch (Opcode) {
462 Opcode = X86::JMP32r;
465 Opcode = X86::JMP32m;
468 Opcode = X86::JMP64r;
471 Opcode = X86::JMP64m
[all...] |
| /src/external/gpl3/binutils/dist/gprofng/src/ |
| Expression.h | 62 enum OpCode
117 Expression (OpCode, const Expression*, const Expression* = 0);
118 Expression (OpCode, uint64_t);
171 OpCode op;
|
| /src/external/gpl3/binutils.old/dist/gprofng/src/ |
| Expression.h | 62 enum OpCode
117 Expression (OpCode, const Expression*, const Expression* = 0);
118 Expression (OpCode, uint64_t);
171 OpCode op;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| MVEGatherScatterLowering.cpp | 875 unsigned OpCode = cast<Instruction>(U)->getOpcode();
876 if ((OpCode == Instruction::Add || OpCode == Instruction::Mul) &&
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/ |
| M68kDisassembler.cpp | 79 unsigned OpCode;
107 M68kInstructionLookup build(unsigned OpCode);
227 dbgs() << "M68kInstructionLookup " << OpCode << " ";
260 M68kInstructionLookup M68kInstructionLookupBuilder::build(unsigned OpCode) {
265 Ret.OpCode = OpCode;
476 Instr.setOpcode(Lookup.OpCode);
477 LLVM_DEBUG(errs() << "decoding instruction " << MCII->getName(Lookup.OpCode)
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/CodeView/ |
| SymbolRecord.h | 162 BinaryAnnotationsOpCode OpCode = BinaryAnnotationsOpCode::Invalid;
258 Result.OpCode = static_cast<BinaryAnnotationsOpCode>(Op);
259 switch (Result.OpCode) {
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| MIParser.cpp | 144 unsigned &OpCode) {
149 OpCode = InstrInfo->getValue();
485 bool parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
488 bool parseMachineOperandAndTargetFlags(const unsigned OpCode,
507 bool parseTargetImmMnemonic(const unsigned OpCode, const unsigned OpIdx,
535 bool parseInstruction(unsigned &OpCode, unsigned &Flags);
975 unsigned OpCode, Flags = 0;
976 if (Token.isError() || parseInstruction(OpCode, Flags))
988 if (parseMachineOperandAndTargetFlags(OpCode, Operands.size(), MO, TiedDefIdx))
990 if ((OpCode == TargetOpcode::DBG_VALUE |
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInstrInfo.cpp | 950 const unsigned OpCode = MCI.getOpcode();
952 const bool NoSlotReqd = Hexagon::A4_ext == OpCode ||
953 (IsTiny && Hexagon::A2_nop == OpCode) ||
954 (IsTiny && Hexagon::J4_hintjumpr == OpCode);
|
| /src/external/mit/lua/dist/src/ |
| lopcodes.h | 17 All instructions have an opcode in the first 7 bits.
38 ** size and position of opcode arguments.
64 ** limits for opcode arguments.
116 #define GET_OPCODE(i) (cast(OpCode, ((i)>>POS_OP) & MASK1(SIZE_OP,0)))
317 OP_EXTRAARG/* Ax extra (larger) argument for previous opcode */
318 } OpCode;
328 (*) Opcode OP_LFALSESKIP is used to convert a condition to a boolean
333 bitwise opcode. If the operation succeeds, it skips this next
334 opcode. Otherwise, this opcode calls the corresponding metamethod
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 310 // Check if an opcode is a FMA instruction. If it is, return the index in array
312 int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const {
314 if (FMAOpIdxInfo[I][InfoArrayIdxFMAInst] == Opcode)
450 unsigned Opcode = Root.getOpcode();
451 if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP)
1071 unsigned Opcode = MI.getOpcode();
1075 if (End != std::find(OpcodesForSpill, End, Opcode)) {
1128 unsigned Opcode = MI.getOpcode();
1132 if (End != std::find(OpcodesForSpill, End, Opcode)) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| SimplifyIndVar.cpp | 1108 unsigned OpCode) const;
1203 unsigned Opcode = DU.NarrowUse->getOpcode();
1204 switch (Opcode) {
1332 unsigned OpCode) const {
1333 switch (OpCode) {
1343 llvm_unreachable("Unsupported opcode.");
1355 const unsigned OpCode = DU.NarrowUse->getOpcode();
1357 if (OpCode != Instruction::Add && OpCode != Instruction::Sub &&
1358 OpCode != Instruction::Mul
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 612 unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
613 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
1863 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1864 switch ((HexagonISD::NodeType)Opcode) {
2277 llvm_unreachable("Unexpected shift opcode");
|
| /src/sys/external/bsd/gnu-efi/dist/inc/ |
| efi_pxe.h | 205 // last valid opcode:
209 // Last valid PXE UNDI OpCode number.
920 PXE_OPCODE OpCode;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 41 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
508 unsigned Opcode = Op.getOpcode();
515 switch (Opcode) {
527 if (Opcode == ISD::XOR && DemandedBits.isSubsetOf(C))
533 SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
2378 unsigned Opcode = Op.getOpcode();
2424 Opcode, SDLoc(Op), VT, NewOp0 ? NewOp0 : Op0, NewOp1 ? NewOp1 : Op1);
2430 switch (Opcode) {
4542 const unsigned OpCode = Op.getOpcode();
4543 if (OpCode == ISD::ADD || OpCode == ISD::SUB)
[all...] |
| SelectionDAGBuilder.cpp | 1128 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
1131 switch (Opcode) {
1134 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1135 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
2201 // Compute the effective opcode for Cond, taking into account whether it needs
2222 // Note that all nodes in the tree should have same opcode.
2385 Instruction::BinaryOps Opcode = (Instruction::BinaryOps)0;
2387 Opcode = Instruction::And;
2389 Opcode = Instruction::Or
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 1721 unsigned OpCode = !Subtarget->hasMadMacF32Insts() ?
1726 SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
2339 llvm_unreachable("Unexpected OPCode!!!");
3641 llvm_unreachable("invalid min/max opcode");
4207 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
4208 switch ((AMDGPUISD::NodeType)Opcode) {
4609 unsigned Opcode = Op.getOpcode();
4610 switch (Opcode) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 175 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1754 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
1755 return MipsInsts[Opcode];
1876 const unsigned Opcode = Inst.getOpcode();
1877 const MCInstrDesc &MCID = getInstDesc(Opcode);
1885 switch (Opcode) {
1996 if (hasMips32r6() && Opcode == Mips::SSNOP) {
2006 switch (Opcode) {
2020 if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 ||
2021 Opcode == Mips::BBIT1 ? 63 : 31)
[all...] |
