1 //===-- AMDGPUAsmUtils.cpp - AsmParser/InstPrinter common -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 #include "AMDGPUAsmUtils.h" 9 #include "SIDefines.h" 10 11 #include "llvm/ADT/StringRef.h" 12 13 namespace llvm { 14 namespace AMDGPU { 15 namespace SendMsg { 16 17 // This must be in sync with llvm::AMDGPU::SendMsg::Id enum members, see SIDefines.h. 18 const char *const IdSymbolic[ID_GAPS_LAST_] = { 19 nullptr, 20 "MSG_INTERRUPT", 21 "MSG_GS", 22 "MSG_GS_DONE", 23 "MSG_SAVEWAVE", 24 "MSG_STALL_WAVE_GEN", 25 "MSG_HALT_WAVES", 26 "MSG_ORDERED_PS_DONE", 27 "MSG_EARLY_PRIM_DEALLOC", 28 "MSG_GS_ALLOC_REQ", 29 "MSG_GET_DOORBELL", 30 "MSG_GET_DDID", 31 nullptr, 32 nullptr, 33 nullptr, 34 "MSG_SYSMSG" 35 }; 36 37 // These two must be in sync with llvm::AMDGPU::SendMsg::Op enum members, see SIDefines.h. 38 const char *const OpSysSymbolic[OP_SYS_LAST_] = { 39 nullptr, 40 "SYSMSG_OP_ECC_ERR_INTERRUPT", 41 "SYSMSG_OP_REG_RD", 42 "SYSMSG_OP_HOST_TRAP_ACK", 43 "SYSMSG_OP_TTRACE_PC" 44 }; 45 46 const char *const OpGsSymbolic[OP_GS_LAST_] = { 47 "GS_OP_NOP", 48 "GS_OP_CUT", 49 "GS_OP_EMIT", 50 "GS_OP_EMIT_CUT" 51 }; 52 53 } // namespace SendMsg 54 55 namespace Hwreg { 56 57 // This must be in sync with llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_/LAST_, see SIDefines.h. 58 const char* const IdSymbolic[] = { 59 nullptr, 60 "HW_REG_MODE", 61 "HW_REG_STATUS", 62 "HW_REG_TRAPSTS", 63 "HW_REG_HW_ID", 64 "HW_REG_GPR_ALLOC", 65 "HW_REG_LDS_ALLOC", 66 "HW_REG_IB_STS", 67 nullptr, 68 nullptr, 69 nullptr, 70 nullptr, 71 nullptr, 72 nullptr, 73 nullptr, 74 "HW_REG_SH_MEM_BASES", 75 "HW_REG_TBA_LO", 76 "HW_REG_TBA_HI", 77 "HW_REG_TMA_LO", 78 "HW_REG_TMA_HI", 79 "HW_REG_FLAT_SCR_LO", 80 "HW_REG_FLAT_SCR_HI", 81 "HW_REG_XNACK_MASK", 82 nullptr, // HW_ID1, no predictable values 83 nullptr, // HW_ID2, no predictable values 84 "HW_REG_POPS_PACKER", 85 nullptr, 86 nullptr, 87 nullptr, 88 "HW_REG_SHADER_CYCLES" 89 }; 90 91 } // namespace Hwreg 92 93 namespace MTBUFFormat { 94 95 StringLiteral const DfmtSymbolic[] = { 96 "BUF_DATA_FORMAT_INVALID", 97 "BUF_DATA_FORMAT_8", 98 "BUF_DATA_FORMAT_16", 99 "BUF_DATA_FORMAT_8_8", 100 "BUF_DATA_FORMAT_32", 101 "BUF_DATA_FORMAT_16_16", 102 "BUF_DATA_FORMAT_10_11_11", 103 "BUF_DATA_FORMAT_11_11_10", 104 "BUF_DATA_FORMAT_10_10_10_2", 105 "BUF_DATA_FORMAT_2_10_10_10", 106 "BUF_DATA_FORMAT_8_8_8_8", 107 "BUF_DATA_FORMAT_32_32", 108 "BUF_DATA_FORMAT_16_16_16_16", 109 "BUF_DATA_FORMAT_32_32_32", 110 "BUF_DATA_FORMAT_32_32_32_32", 111 "BUF_DATA_FORMAT_RESERVED_15" 112 }; 113 114 StringLiteral const NfmtSymbolicGFX10[] = { 115 "BUF_NUM_FORMAT_UNORM", 116 "BUF_NUM_FORMAT_SNORM", 117 "BUF_NUM_FORMAT_USCALED", 118 "BUF_NUM_FORMAT_SSCALED", 119 "BUF_NUM_FORMAT_UINT", 120 "BUF_NUM_FORMAT_SINT", 121 "", 122 "BUF_NUM_FORMAT_FLOAT" 123 }; 124 125 StringLiteral const NfmtSymbolicSICI[] = { 126 "BUF_NUM_FORMAT_UNORM", 127 "BUF_NUM_FORMAT_SNORM", 128 "BUF_NUM_FORMAT_USCALED", 129 "BUF_NUM_FORMAT_SSCALED", 130 "BUF_NUM_FORMAT_UINT", 131 "BUF_NUM_FORMAT_SINT", 132 "BUF_NUM_FORMAT_SNORM_OGL", 133 "BUF_NUM_FORMAT_FLOAT" 134 }; 135 136 StringLiteral const NfmtSymbolicVI[] = { // VI and GFX9 137 "BUF_NUM_FORMAT_UNORM", 138 "BUF_NUM_FORMAT_SNORM", 139 "BUF_NUM_FORMAT_USCALED", 140 "BUF_NUM_FORMAT_SSCALED", 141 "BUF_NUM_FORMAT_UINT", 142 "BUF_NUM_FORMAT_SINT", 143 "BUF_NUM_FORMAT_RESERVED_6", 144 "BUF_NUM_FORMAT_FLOAT" 145 }; 146 147 StringLiteral const UfmtSymbolic[] = { 148 "BUF_FMT_INVALID", 149 150 "BUF_FMT_8_UNORM", 151 "BUF_FMT_8_SNORM", 152 "BUF_FMT_8_USCALED", 153 "BUF_FMT_8_SSCALED", 154 "BUF_FMT_8_UINT", 155 "BUF_FMT_8_SINT", 156 157 "BUF_FMT_16_UNORM", 158 "BUF_FMT_16_SNORM", 159 "BUF_FMT_16_USCALED", 160 "BUF_FMT_16_SSCALED", 161 "BUF_FMT_16_UINT", 162 "BUF_FMT_16_SINT", 163 "BUF_FMT_16_FLOAT", 164 165 "BUF_FMT_8_8_UNORM", 166 "BUF_FMT_8_8_SNORM", 167 "BUF_FMT_8_8_USCALED", 168 "BUF_FMT_8_8_SSCALED", 169 "BUF_FMT_8_8_UINT", 170 "BUF_FMT_8_8_SINT", 171 172 "BUF_FMT_32_UINT", 173 "BUF_FMT_32_SINT", 174 "BUF_FMT_32_FLOAT", 175 176 "BUF_FMT_16_16_UNORM", 177 "BUF_FMT_16_16_SNORM", 178 "BUF_FMT_16_16_USCALED", 179 "BUF_FMT_16_16_SSCALED", 180 "BUF_FMT_16_16_UINT", 181 "BUF_FMT_16_16_SINT", 182 "BUF_FMT_16_16_FLOAT", 183 184 "BUF_FMT_10_11_11_UNORM", 185 "BUF_FMT_10_11_11_SNORM", 186 "BUF_FMT_10_11_11_USCALED", 187 "BUF_FMT_10_11_11_SSCALED", 188 "BUF_FMT_10_11_11_UINT", 189 "BUF_FMT_10_11_11_SINT", 190 "BUF_FMT_10_11_11_FLOAT", 191 192 "BUF_FMT_11_11_10_UNORM", 193 "BUF_FMT_11_11_10_SNORM", 194 "BUF_FMT_11_11_10_USCALED", 195 "BUF_FMT_11_11_10_SSCALED", 196 "BUF_FMT_11_11_10_UINT", 197 "BUF_FMT_11_11_10_SINT", 198 "BUF_FMT_11_11_10_FLOAT", 199 200 "BUF_FMT_10_10_10_2_UNORM", 201 "BUF_FMT_10_10_10_2_SNORM", 202 "BUF_FMT_10_10_10_2_USCALED", 203 "BUF_FMT_10_10_10_2_SSCALED", 204 "BUF_FMT_10_10_10_2_UINT", 205 "BUF_FMT_10_10_10_2_SINT", 206 207 "BUF_FMT_2_10_10_10_UNORM", 208 "BUF_FMT_2_10_10_10_SNORM", 209 "BUF_FMT_2_10_10_10_USCALED", 210 "BUF_FMT_2_10_10_10_SSCALED", 211 "BUF_FMT_2_10_10_10_UINT", 212 "BUF_FMT_2_10_10_10_SINT", 213 214 "BUF_FMT_8_8_8_8_UNORM", 215 "BUF_FMT_8_8_8_8_SNORM", 216 "BUF_FMT_8_8_8_8_USCALED", 217 "BUF_FMT_8_8_8_8_SSCALED", 218 "BUF_FMT_8_8_8_8_UINT", 219 "BUF_FMT_8_8_8_8_SINT", 220 221 "BUF_FMT_32_32_UINT", 222 "BUF_FMT_32_32_SINT", 223 "BUF_FMT_32_32_FLOAT", 224 225 "BUF_FMT_16_16_16_16_UNORM", 226 "BUF_FMT_16_16_16_16_SNORM", 227 "BUF_FMT_16_16_16_16_USCALED", 228 "BUF_FMT_16_16_16_16_SSCALED", 229 "BUF_FMT_16_16_16_16_UINT", 230 "BUF_FMT_16_16_16_16_SINT", 231 "BUF_FMT_16_16_16_16_FLOAT", 232 233 "BUF_FMT_32_32_32_UINT", 234 "BUF_FMT_32_32_32_SINT", 235 "BUF_FMT_32_32_32_FLOAT", 236 "BUF_FMT_32_32_32_32_UINT", 237 "BUF_FMT_32_32_32_32_SINT", 238 "BUF_FMT_32_32_32_32_FLOAT" 239 }; 240 241 unsigned const DfmtNfmt2UFmt[] = { 242 DFMT_INVALID | (NFMT_UNORM << NFMT_SHIFT), 243 244 DFMT_8 | (NFMT_UNORM << NFMT_SHIFT), 245 DFMT_8 | (NFMT_SNORM << NFMT_SHIFT), 246 DFMT_8 | (NFMT_USCALED << NFMT_SHIFT), 247 DFMT_8 | (NFMT_SSCALED << NFMT_SHIFT), 248 DFMT_8 | (NFMT_UINT << NFMT_SHIFT), 249 DFMT_8 | (NFMT_SINT << NFMT_SHIFT), 250 251 DFMT_16 | (NFMT_UNORM << NFMT_SHIFT), 252 DFMT_16 | (NFMT_SNORM << NFMT_SHIFT), 253 DFMT_16 | (NFMT_USCALED << NFMT_SHIFT), 254 DFMT_16 | (NFMT_SSCALED << NFMT_SHIFT), 255 DFMT_16 | (NFMT_UINT << NFMT_SHIFT), 256 DFMT_16 | (NFMT_SINT << NFMT_SHIFT), 257 DFMT_16 | (NFMT_FLOAT << NFMT_SHIFT), 258 259 DFMT_8_8 | (NFMT_UNORM << NFMT_SHIFT), 260 DFMT_8_8 | (NFMT_SNORM << NFMT_SHIFT), 261 DFMT_8_8 | (NFMT_USCALED << NFMT_SHIFT), 262 DFMT_8_8 | (NFMT_SSCALED << NFMT_SHIFT), 263 DFMT_8_8 | (NFMT_UINT << NFMT_SHIFT), 264 DFMT_8_8 | (NFMT_SINT << NFMT_SHIFT), 265 266 DFMT_32 | (NFMT_UINT << NFMT_SHIFT), 267 DFMT_32 | (NFMT_SINT << NFMT_SHIFT), 268 DFMT_32 | (NFMT_FLOAT << NFMT_SHIFT), 269 270 DFMT_16_16 | (NFMT_UNORM << NFMT_SHIFT), 271 DFMT_16_16 | (NFMT_SNORM << NFMT_SHIFT), 272 DFMT_16_16 | (NFMT_USCALED << NFMT_SHIFT), 273 DFMT_16_16 | (NFMT_SSCALED << NFMT_SHIFT), 274 DFMT_16_16 | (NFMT_UINT << NFMT_SHIFT), 275 DFMT_16_16 | (NFMT_SINT << NFMT_SHIFT), 276 DFMT_16_16 | (NFMT_FLOAT << NFMT_SHIFT), 277 278 DFMT_10_11_11 | (NFMT_UNORM << NFMT_SHIFT), 279 DFMT_10_11_11 | (NFMT_SNORM << NFMT_SHIFT), 280 DFMT_10_11_11 | (NFMT_USCALED << NFMT_SHIFT), 281 DFMT_10_11_11 | (NFMT_SSCALED << NFMT_SHIFT), 282 DFMT_10_11_11 | (NFMT_UINT << NFMT_SHIFT), 283 DFMT_10_11_11 | (NFMT_SINT << NFMT_SHIFT), 284 DFMT_10_11_11 | (NFMT_FLOAT << NFMT_SHIFT), 285 286 DFMT_11_11_10 | (NFMT_UNORM << NFMT_SHIFT), 287 DFMT_11_11_10 | (NFMT_SNORM << NFMT_SHIFT), 288 DFMT_11_11_10 | (NFMT_USCALED << NFMT_SHIFT), 289 DFMT_11_11_10 | (NFMT_SSCALED << NFMT_SHIFT), 290 DFMT_11_11_10 | (NFMT_UINT << NFMT_SHIFT), 291 DFMT_11_11_10 | (NFMT_SINT << NFMT_SHIFT), 292 DFMT_11_11_10 | (NFMT_FLOAT << NFMT_SHIFT), 293 294 DFMT_10_10_10_2 | (NFMT_UNORM << NFMT_SHIFT), 295 DFMT_10_10_10_2 | (NFMT_SNORM << NFMT_SHIFT), 296 DFMT_10_10_10_2 | (NFMT_USCALED << NFMT_SHIFT), 297 DFMT_10_10_10_2 | (NFMT_SSCALED << NFMT_SHIFT), 298 DFMT_10_10_10_2 | (NFMT_UINT << NFMT_SHIFT), 299 DFMT_10_10_10_2 | (NFMT_SINT << NFMT_SHIFT), 300 301 DFMT_2_10_10_10 | (NFMT_UNORM << NFMT_SHIFT), 302 DFMT_2_10_10_10 | (NFMT_SNORM << NFMT_SHIFT), 303 DFMT_2_10_10_10 | (NFMT_USCALED << NFMT_SHIFT), 304 DFMT_2_10_10_10 | (NFMT_SSCALED << NFMT_SHIFT), 305 DFMT_2_10_10_10 | (NFMT_UINT << NFMT_SHIFT), 306 DFMT_2_10_10_10 | (NFMT_SINT << NFMT_SHIFT), 307 308 DFMT_8_8_8_8 | (NFMT_UNORM << NFMT_SHIFT), 309 DFMT_8_8_8_8 | (NFMT_SNORM << NFMT_SHIFT), 310 DFMT_8_8_8_8 | (NFMT_USCALED << NFMT_SHIFT), 311 DFMT_8_8_8_8 | (NFMT_SSCALED << NFMT_SHIFT), 312 DFMT_8_8_8_8 | (NFMT_UINT << NFMT_SHIFT), 313 DFMT_8_8_8_8 | (NFMT_SINT << NFMT_SHIFT), 314 315 DFMT_32_32 | (NFMT_UINT << NFMT_SHIFT), 316 DFMT_32_32 | (NFMT_SINT << NFMT_SHIFT), 317 DFMT_32_32 | (NFMT_FLOAT << NFMT_SHIFT), 318 319 DFMT_16_16_16_16 | (NFMT_UNORM << NFMT_SHIFT), 320 DFMT_16_16_16_16 | (NFMT_SNORM << NFMT_SHIFT), 321 DFMT_16_16_16_16 | (NFMT_USCALED << NFMT_SHIFT), 322 DFMT_16_16_16_16 | (NFMT_SSCALED << NFMT_SHIFT), 323 DFMT_16_16_16_16 | (NFMT_UINT << NFMT_SHIFT), 324 DFMT_16_16_16_16 | (NFMT_SINT << NFMT_SHIFT), 325 DFMT_16_16_16_16 | (NFMT_FLOAT << NFMT_SHIFT), 326 327 DFMT_32_32_32 | (NFMT_UINT << NFMT_SHIFT), 328 DFMT_32_32_32 | (NFMT_SINT << NFMT_SHIFT), 329 DFMT_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT), 330 DFMT_32_32_32_32 | (NFMT_UINT << NFMT_SHIFT), 331 DFMT_32_32_32_32 | (NFMT_SINT << NFMT_SHIFT), 332 DFMT_32_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT) 333 }; 334 335 } // namespace MTBUFFormat 336 337 namespace Swizzle { 338 339 // This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h. 340 const char* const IdSymbolic[] = { 341 "QUAD_PERM", 342 "BITMASK_PERM", 343 "SWAP", 344 "REVERSE", 345 "BROADCAST", 346 }; 347 348 } // namespace Swizzle 349 350 namespace VGPRIndexMode { 351 352 // This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h. 353 const char* const IdSymbolic[] = { 354 "SRC0", 355 "SRC1", 356 "SRC2", 357 "DST", 358 }; 359 360 } // namespace VGPRIndexMode 361 362 } // namespace AMDGPU 363 } // namespace llvm 364
Indexes created Mon Jun 08 00:24:58 UTC 2026