| /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/ |
| DWARFExpression.cpp | 235 unsigned OpNum = 0;
239 DwarfRegNum = Operands[OpNum++];
249 OS << format(" %s%+" PRId64, RegName, Operands[OpNum]);
|
| /src/external/apache2/llvm/dist/llvm/utils/PerfectShuffle/ |
| PerfectShuffle.cpp | 106 unsigned short OpNum;
109 Operator(unsigned short shufflemask, const char *name, unsigned opnum,
111 : Name(name), ShuffleMask(shufflemask), OpNum(opnum),Cost(cost) {
302 for (unsigned opnum = 0, e = TheOperators.size(); opnum != e; ++opnum) {
303 Operator *Op = TheOperators[opnum];
393 unsigned OpNum = ShufTab[i].Op ? ShufTab[i].Op->OpNum : 0
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfExpression.cpp | 485 uint64_t OpNum = Op->getOp();
487 if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
488 emitOp(OpNum);
490 } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
491 addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
495 switch (OpNum) {
553 emitOp(OpNum);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRDFOpt.cpp | 96 void removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum);
189 void HexagonDCE::removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum) {
204 MI->RemoveOperand(OpNum);
208 if (N < OpNum)
210 else if (N > OpNum)
224 unsigned OpNum, NewOpc;
228 OpNum = 1;
232 OpNum = 1;
236 OpNum = 1;
240 OpNum = 0
[all...] |
| HexagonConstExtenders.cpp | 318 unsigned OpNum = -1u;
330 return UseMI->getOperand(OpNum);
333 return UseMI->getOperand(OpNum);
396 void recordExtender(MachineInstr &MI, unsigned OpNum);
492 assert(ED.OpNum != -1u);
1140 void HCE::recordExtender(MachineInstr &MI, unsigned OpNum) {
1143 ED.OpNum = OpNum;
1162 ED.Rd = MI.getOperand(OpNum-1);
1170 ED.Expr.Rs = MI.getOperand(OpNum-1)
[all...] |
| HexagonFrameLowering.cpp | 2290 unsigned OpNum = Load ? 0 : 2;
2291 auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
|
| HexagonInstrInfo.cpp | 3484 unsigned OpNum = MI.getOpcode();
3487 auto Iter = DupMap.find(OpNum);
3492 if (Iter->second == OpNum)
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| DetectDeadLanes.cpp | 85 /// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum
88 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
169 unsigned OpNum = MI.getOperandNo(&MO);
170 DstSubIdx = MI.getOperand(OpNum+1).getImm();
229 unsigned OpNum = MI.getOperandNo(&MO);
238 assert(OpNum % 2 == 1);
239 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
246 if (OpNum == 2)
258 assert(OpNum == 1);
262 assert(OpNum == 1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 415 unsigned OpNum = 3; // First 'rest' of operands.
452 OpNum = 4;
515 OpNum = 0;
541 OpNum = 2;
548 OpNum = 0;
555 OpNum = 2;
614 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
615 MIB.add(MI->getOperand(OpNum));
|
| ARMISelLowering.cpp | 7940 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7941 switch (OpNum) {
8010 unsigned OpNum = (PFEntry >> 26) & 0x0F;
8014 if (OpNum == OP_COPY) {
8025 switch (OpNum) {
8044 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32));
8050 DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32));
8054 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
8058 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
8062 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64InstPrinter.cpp | 734 int OpNum = LdStDesc->ListOperand;
735 printVectorList(MI, OpNum++, STI, O, "");
738 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
741 unsigned AddrReg = MI->getOperand(OpNum++).getReg();
746 unsigned Reg = MI->getOperand(OpNum++).getReg();
947 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
950 const MCOperand &MO = MI->getOperand(OpNum);
955 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
958 printShifter(MI, OpNum + 1, STI, O);
965 printShifter(MI, OpNum + 1, STI, O)
[all...] |
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| AsmWriterEmitter.cpp | 875 unsigned OpNum = Operands.getSubOperandNumber(MIOpNum).first;
876 if (Operands[OpNum].MINumOperands == 1 &&
877 Operands[OpNum].getTiedRegister() != -1) {
880 int TiedOpNum = Operands[OpNum].getTiedRegister();
881 if (Operands[OpNum].Rec->getName() ==
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | 1345 unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
1346 const MachineOperand &MO = MI->getOperand(OpNum);
|
| PPCISelLowering.cpp | 9295 unsigned OpNum = (PFEntry >> 26) & 0x0F;
9312 if (OpNum == OP_COPY) {
9323 switch (OpNum) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 1037 unsigned OpNum = Ops[0];
1040 .getRegClass(MI.getOperand(OpNum).getReg())) &&
1043 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1057 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1059 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1072 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1074 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1118 if (OpNum == 0) {
1129 if (OpNum == 1) {
1153 if (OpNum == 0 && MI.hasOneMemOperand())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| ValueTracking.cpp | 1411 unsigned OpNum = P->getOperand(0) == R ? 0 : 1;
1412 Instruction *RInst = P->getIncomingBlock(OpNum)->getTerminator();
1413 Instruction *LInst = P->getIncomingBlock(1-OpNum)->getTerminator();
2536 auto getOperands = [&](unsigned OpNum) -> auto {
2537 return std::make_pair(Op1->getOperand(OpNum), Op2->getOperand(OpNum));
|
| /src/external/apache2/llvm/dist/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | 2671 unsigned OpNum = 0;
2675 PointeeType = getTypeByID(Record[OpNum++]);
2680 uint64_t Op = Record[OpNum++];
2688 while (OpNum != Record.size()) {
2690 Elt0FullTy = getFullyStructuredTypeByID(Record[OpNum]);
2691 Type *ElTy = getTypeByID(Record[OpNum++]);
2694 Elts.push_back(ValueList.getConstantFwdRef(Record[OpNum++], ElTy));
3487 unsigned OpNum = 0;
3488 Type *FullTy = getFullyStructuredTypeByID(Record[OpNum++]);
3501 AddrSpace = Record[OpNum++]
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 1604 bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
1971 auto OpNum = Inst.getNumOperands();
1973 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));
1976 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));
1977 const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);
1982 uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType;
1999 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand
3070 auto OpNum =
3072 const auto &Op = Inst.getOperand(OpNum);
3826 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 3865 unsigned OpNum = Inst.getNumOperands();
3869 assert(Inst.getOperand(OpNum - 1).isImm() &&
3870 Inst.getOperand(OpNum - 2).isReg() &&
3871 Inst.getOperand(OpNum - 3).isReg() && "Invalid instruction operand.");
3873 if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
3874 Inst.getOperand(OpNum - 1).getImm() >= 0 &&
3875 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP ||
3876 Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) &&
3877 (Inst.getOperand(OpNum - 3).getReg() == Mips::RA |
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/Sema/ |
| SemaChecking.cpp | 2747 uint8_t OpNum;
2968 Error |= SemaBuiltinConstantArgRange(TheCall, A.OpNum, Min, Max);
2973 Error |= SemaBuiltinConstantArgRange(TheCall, A.OpNum, Min, Max) |
2974 SemaBuiltinConstantArgMultiple(TheCall, A.OpNum, M);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 8773 unsigned OpNum = (PFEntry >> 26) & 0x0F;
8795 if (OpNum == OP_COPY) {
8807 switch (OpNum) {
8842 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
8848 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
|
