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    Searched defs:OpSize (Results 1 - 14 of 14) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLegalizerInfo.cpp 399 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
404 auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
416 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
417 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
GISelKnownBits.cpp 456 unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
462 Known.insertBits(SrcOpKnown, I * OpSize);
MachineIRBuilder.cpp 558 unsigned OpSize = OpTy.getSizeInBits();
561 if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
567 if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
LegalizerHelper.cpp 4899 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
4903 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
4918 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
4921 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
4968 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
4972 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
4990 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
4995 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
4999 if (ExtractOffset != 0 || SegSize != OpSize) {
  /src/external/apache2/llvm/dist/llvm/lib/IR/
Metadata.cpp 495 size_t OpSize = NumOps * sizeof(MDOperand);
498 OpSize = alignTo(OpSize, alignof(uint64_t));
499 void *Ptr = reinterpret_cast<char *>(::operator new(OpSize + Size)) + OpSize;
510 size_t OpSize = N->NumOperands * sizeof(MDOperand);
511 OpSize = alignTo(OpSize, alignof(uint64_t));
516 ::operator delete(reinterpret_cast<char *>(Mem) - OpSize);
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
X86RecognizableInstr.h 176 /// The OpSize field from the record
177 uint8_t OpSize;
243 /// @param OpSize Indicates the operand size of the instruction.
244 /// If register size does not match OpSize, then
248 bool hasREX_WPrefix, uint8_t OpSize);
255 /// @param OpSize - Indicates whether this is an OpSize16 instruction.
259 uint8_t OpSize);
264 uint8_t OpSize);
269 uint8_t OpSize);
271 uint8_t OpSize);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ConstantFolding.cpp 788 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType());
793 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize) -
794 Offs2.zextOrTrunc(OpSize));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 584 int64_t OpSize = MFI.getObjectSize(FI);
589 OpSize = SubRegSize / 8;
592 MemSize = std::max(MemSize, OpSize);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 850 unsigned OpSize = OpTy.getSizeInBits();
853 if (OpSize == 32) {
894 bool Is64 = OpSize % 64 == 0;
896 LLT UnmergeTy = OpSize % 64 == 0 ? LLT::scalar(64) : LLT::scalar(32);
897 unsigned CmpOp = OpSize % 64 == 0 ? AMDGPU::V_CMP_EQ_U64_e64
4025 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
4026 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize);
4027 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize);
SIISelLowering.cpp 3102 unsigned OpSize = Flags.isByVal() ?
3112 int FI = MFI.CreateFixedObject(OpSize, Offset, true);
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 681 uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8;
682 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 3166 auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx);
3168 switch (OpSize) { // expected operand size
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 4971 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
4972 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
12968 auto OpSize = N->getOperand(0).getValueSizeInBits();
12972 if (OpSize < Size) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 5775 unsigned OpSize;
5777 OpSize = VA.getLocVT().getFixedSizeInBits();
5779 OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
5781 OpSize = (OpSize + 7) / 8;
5784 if (OpSize < 8)
5785 BEAlign = 8 - OpSize;
5794 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);

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