| /src/external/gpl3/gdb.old/dist/gdbsupport/ |
| traits.h | 5 This program is free software; you can redistribute it and/or modify
7 the Free Software Foundation; either version 3 of the License, or
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
93 because "and/or", etc. are reserved keywords. */
100 struct Or;
103 struct Or<> : public std::false_type
107 struct Or<B1> : public B1
111 struct Or<B1, B2>
116 struct Or<B1, B2, B3, Bn...>
117 : public std::conditional<B1::value, B1, Or<B2, B3, Bn...>>::typ
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| /src/external/apache2/llvm/dist/clang/include/clang/Analysis/Analyses/ |
| ThreadSafetyLogical.h | 26 Or,
75 class Or : public BinOp {
77 Or(LExpr *LHS, LExpr *RHS) : BinOp(LHS, RHS, LExpr::Or) {}
79 static bool classof(const LExpr *E) { return E->kind() == LExpr::Or; }
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| VPlanPredicator.cpp | 41 // Set the intermediate value - this is either 'CBV', or 'not CBV'
80 // We pop a pair of values from the front (e.g. P1 and P2), generate an OR
98 // Create an OR of these values.
99 VPValue *Or = Builder.createOr(LHS, RHS);
101 // Push OR to the back of the worklist.
102 Worklist.push_back(Or);
115 // Return whether the edge FromBlock -> ToBlock is a TRUE_EDGE or FALSE_EDGE
179 // Logically OR all incoming predicates by building the Predicate Tree.
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/ |
| BoundsChecking.cpp | 53 /// the result from the load or the value being stored. It is used to determine
99 Value *Or = IRB.CreateOr(Cmp2, Cmp3);
103 Or = IRB.CreateOr(Cmp1, Or);
106 return Or;
111 /// \p Or is the condition that should guard the trap.
115 static void insertBoundsCheck(Value *Or, BuilderTy &IRB, GetTrapBBT GetTrapBB) {
117 ConstantInt *C = dyn_cast_or_null<ConstantInt>(Or);
140 BranchInst::Create(GetTrapBB(IRB), Cont, Or, OldBB);
154 Value *Or = nullptr
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| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| IVDescriptors.h | 41 Or, ///< Bitwise or logical OR of integers.
42 And, ///< Bitwise or logical AND of integers.
43 Xor, ///< Bitwise or logical XOR of integers.
59 /// Basic recurrences are defined as the summation, product, OR, AND, XOR, min,
60 /// or max of a set of terms. For example: for(i=0; i<n; i++) { total +=
105 // pattern), or the current recurrence instruction otherwise.
131 /// or max(X, Y). \p Prev specifies the description of an already processed
148 /// RecurrenceDescriptor. If either \p DB is non-null or \p AC and \p DT ar
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| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| MIPatternMatch.h | 149 template <typename... Preds> struct Or {
157 struct Or<Pred, Preds...> : Or<Preds...> {
159 Or(Pred &&p, Preds &&... preds)
160 : Or<Preds...>(std::forward<Preds>(preds)...), P(std::forward<Pred>(p)) {}
163 return P.match(MRI, src) || Or<Preds...>::match(MRI, src);
171 template <typename... Preds> Or<Preds...> m_any_of(Preds &&... preds) {
172 return Or<Preds...>(std::forward<Preds>(preds)...);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SILowerControlFlow.cpp | 372 // AND the break condition operand with exec, then OR that into the "loop
374 MachineInstr *And = nullptr, *Or = nullptr;
380 Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
386 Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
393 LIS->ReplaceMachineInstrInMaps(MI, *Or);
496 // for exec or two operands if source was another equivalent operation.
533 if (Ops.size() == 1) OpToReplace = 2; // First operand can be exec or its copy
|
| AMDGPURegisterBankInfo.cpp | 31 /// is naturally a bitmask with one bit per lane, in a 32 or 64-bit
34 /// bank. To distinguish whether an SGPR should use the SGPR or VCC register
52 /// most 1 SGPR or constant literal value (this to 2 in gfx10 for most
63 /// complicated to solve here. Every optimization pattern or instruction
114 /// Set any registers that don't have a set register class or bank to SALU.
453 // Memory must be known constant, or not written before this load.
498 // s_{and|or|xor}_b32 set scc when the result of the 32-bit op is not 0.
1157 // Scalar loads of size 8 or 16 bit with proper alignment may be widened to
1158 // 32 bit. Check to see if we need to widen the memory access, 8 or 16 bit
1608 // any illegal vector extend or unmerge operations
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 35 // The operand must be a constant integer or splat integer.
89 /// with a constant or one of its operands. In such cases, this function does
162 // If either the LHS or the RHS are Zero, the result is zero.
190 case Instruction::Or: {
191 // If either the LHS or the RHS are One, the result is One.
207 // These bits cannot contribute to the result of the 'or'.
251 // If all of the demanded bits are known to be zero on one side or the
252 // other, turn this into an *inclusive* or.
255 Instruction *Or =
258 return InsertNewInstWith(Or, *I)
[all...] |
| InstCombineSelect.cpp | 110 // S = { select (cmp eq X, C), BO, ? } or { select (cmp ne X, C), ?, BO }
112 // S = { select (cmp eq X, C), Y, ? } or { select (cmp ne X, C), ?, Y }
121 /// Or:
123 /// With some variations depending if FC is larger than TC, or the shift
124 /// isn't needed, or the bit widths don't match.
183 // If the masked bit in V is clear, clear or set the bit in the result:
190 // If the masked bit in V is set, set or clear the bit in the result:
214 // or a trunc of the 'and'.
226 // have a icmp_ne or icmp_eq and whether the true or false val is the zero
[all...] |
| InstCombineAndOrXor.cpp | 54 /// operands into either a constant true or false, or a brand new ICmp
66 /// operands into either a FCmp instruction, or a true/false constant.
79 /// Transform BITWISE_OP(BSWAP(A),BSWAP(B)) or
82 /// \return Pointer to node that must replace the original binary operator, or
119 /// whether to treat V, Lo, and Hi as signed or not.
147 /// described as the "AMask" or "BMask" part of the enum. If the enum contains
149 /// then it was proven that (A & C) == C. This is trivial if C == A or C == 0.
153 /// "AllOnes" declares that the comparison is true only if (A & B) == A or all
157 /// "AllZeros" declares that the comparison is true only if (A & B) == 0 or al
[all...] |
| InstCombineCasts.cpp | 118 // The alloc and cast types should be either both fixed or both scalable.
178 /// Given an expression that CanEvaluateTruncated or CanEvaluateSExtd returns
183 C = ConstantExpr::getIntegerCast(C, Ty, isSigned /*Sext or ZExt*/);
197 case Instruction::Or:
268 // We don't want to form an inttoptr or ptrtoint that converts to an integer
284 // The first cast (CSrc) is eliminable so we need to fix up or replace
298 // or the select is likely better done in a narrow type.
344 // We don't extend or shrink something that has multiple uses -- doing so
377 case Instruction::Or:
379 // These operators can all arbitrarily be extended or truncated
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| InstCombineCompares.cpp | 172 /// is true or false for. This triggers on things like "abbbbc"[i] == 'b'.
179 // comparison is true for element 'i'. If there are 64 elements or less in
196 // Find out if the comparison would be true or false for the i'th element.
214 // Otherwise, we know if the comparison is true or false for this element,
282 // If the comparison is only true for one or two elements, emit direct
302 // If the comparison is only false for one or two elements, emit direct
698 // a GEP or a GEP + ptrtoint.
889 // and both GEPs have only constant indices or just one use, then fold
971 // Only lower this if the icmp is the only user of the GEP or if we expect
1039 // These intrinsics don't escape or compare the pointer. Memset is saf
[all...] |
| /src/external/apache2/llvm/dist/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 206 | Or
290 | Or
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| AtomicExpandPass.cpp | 10 // __atomic_* library calls, or target specific instruction which implement the
13 // AtomicCmpXchg, or type coercions.
288 (Op == AtomicRMWInst::Or || Op == AtomicRMWInst::Xor ||
423 /// equivalent bitwidth. We used to not support floating point or vector
426 /// float or vector store. The long term plan is to teach each backend to
455 // or lock cmpxchg8/16b on X86, as these are atomic for larger sizes.
510 case AtomicRMWInst::Or:
710 Value *Or = Builder.CreateOr(And, Shift, "inserted");
711 return Or;
730 case AtomicRMWInst::Or
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| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 110 // (or (rotl Input, Rotate), ~Mask)
117 // narrower (in which case the upper bits are don't care), or wider (in which
150 // Try to fold more of the base or index of AM into AM, where IsBase
270 // Check whether (or Op (and X InsertMask)) is effectively an insertion
289 // Try to implement AND or shift node N using RISBG with the zero flag set.
293 // Try to use RISBG or Opcode to implement OR or XOR node N.
341 // Return true if N (a load or a store) fullfills the alignment
406 // Change the base or index in AM to Value, where IsBase select
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 132 // Break down vector types to either 2 i64s or 4 i32s.
338 // Without this, every float setcc comes with a AND/OR with the result,
501 setTargetDAGCombine(ISD::OR);
806 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
815 // Return if the shifted mask does not start at bit 0 or the sum of its size
868 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
918 // $dst = or (and $src, mask0), mask1
933 // Don't generate INS if constant OR operand doesn't fit into bits
978 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
979 // or
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CGExprScalar.cpp | 112 /// Check if the binop computes a division or a remainder.
181 "Expected a unary or binary operator");
359 /// Convert between either a fixed point and other fixed point or fixed point
690 // effect is the evaluation of the postfix-expression before the dot or
784 return Builder.CreateOr(Ops.LHS, Ops.RHS, "or");
815 HANDLEBINOP(Or)
910 // +-Inf, NaN, or doesn't fit into the destination type (after truncation
1014 // We ignore conversions to/from pointer and/or bool.
1078 "either the widths should be different, or the signednesses.");
1126 // We ignore conversions to/from pointer and/or bool
[all...] |
| ItaniumCXXABI.cpp | 214 // emitted with external linkage or as linkonce if they are inline and used.
338 /// initializer, either because the language semantics demand it or because
390 /// We are guaranteeing, or need to guarantee, that the RTTI string
715 // If doing CFI, VFE or WPD, we will need the metadata node to check
872 /// Perform a bitcast, derived-to-base, or base-to-derived member pointer
1031 // Get the function pointer (or index if this is a virtual function).
1106 /// the same if they're either bitwise identical *or* both null.
1118 llvm::Instruction::BinaryOps And, Or;
1121 And = llvm::Instruction::Or;
1122 Or = llvm::Instruction::And
[all...] |
| MicrosoftCXXABI.cpp | 206 // place, delete single heap objects, or delete arrays.
212 // delegate to or alias the base destructor.
828 // registers, i.e. non-trivially copyable records or records marked with
901 // If this is a catch-all or the catch parameter is unnamed, we don't need to
915 /// or a cast), which requires an object with a vfptr. Adjust the
931 // Okay, one of the vbases must have a vfptr, or else this isn't
1085 // No private or protected non static data members.
1132 // be trivially copyable, or if this is an instance method struct return.
1189 // However, this is not enough while a constructor or a destructor of some
1197 // the X vftables (i.e. during X ctor or dtor)
[all...] |
| /src/external/apache2/llvm/dist/llvm/bindings/go/llvm/ |
| ir.go | 159 Or Opcode = C.LLVMOr
1003 panic("one or more indices are required")
1013 panic("one or more indices are required")
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 625 // We must have a return following the call (or debug insts) to get past
630 "Expected instr following MI to be return or debug inst?");
1087 MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
1089 MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero);
1858 // Overflow occurred if it occurred in the larger type, or if the high part
2741 // v5 = i32 or v4, v2
2772 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2773 MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
3739 // Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces
3742 // Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding wit
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 117 /// some float libcalls (6, 8 or 12 bits).
162 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
231 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
277 // zero or sign-extension.
324 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
364 // If the register was not expanded, truncate or copy the value,
380 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
760 // If the register was not expanded, promote or copy the value,
810 // A Value with type {} or [0 x %t] needs no registers.
1156 // TODO: Dangling debug info will eventually either be resolved or produc
[all...] |
| DAGCombiner.cpp | 317 /// Check the specified integer node value to see if it can be simplified or
339 /// Check the specified vector node value to see if it can be simplified or
697 /// elements of the consecutive stores are all constants or all extracted
748 /// This optimization uses wide integers or vectors when possible.
762 /// is legal or custom before legalizing operations, and whether is
781 /// This method returns true if we are running before type legalization or
887 // Return true if this node is a setcc, or is a select_cc
962 // Determines if it is a constant integer or a splat/build vector of constant
1034 // that's the one we hope to fold into the load or store).
1156 /// Check the specified integer node value to see if it can be simplified or i
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 237 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
241 // vector to all-one or all-zero.
821 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
869 // We combine OR nodes for bitfield operations.
870 setTargetDAGCombine(ISD::OR);
1005 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
1193 // NEON doesn't support masked loads or stores, but SVE does
1385 setOperationAction(ISD::OR, VT, Custom);
1494 setOperationAction(ISD::OR, VT, Custom);
1556 // Return if the immediate is already all zeros, all ones, a bimm32 or
[all...] |
