| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 92 SmallVector<ISD::OutputArg, 4> Outs;
95 GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
98 TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
|
| FastISel.cpp | 1002 SmallVector<ISD::OutputArg, 4> Outs;
1003 GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
1006 CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
|
| SelectionDAGBuilder.cpp | 1875 SmallVector<ISD::OutputArg, 8> Outs;
1895 // Leave Outs empty so that LowerReturn won't try to load return
1997 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
2005 // Push in swifterror virtual register as the last element of Outs. This makes
2014 Outs.push_back(ISD::OutputArg(Flags, EVT(TLI.getPointerTy(DL)) /*vt*/,
2029 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
9377 SmallVector<ISD::OutputArg, 4> Outs;
9378 GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
9382 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
9474 CLI.Outs.clear()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 226 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
241 CCInfo.AnalyzeCallOperands(Outs, CC_ARC);
595 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
598 if (!CCInfo.CheckReturn(Outs, RetCC_ARC))
608 const SmallVectorImpl<ISD::OutputArg> &Outs,
626 CCInfo.AnalyzeReturn(Outs, RetCC_ARC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 371 auto &Outs = CLI.Outs;
396 CCInfo.AnalyzeCallOperands(Outs, getHasAlu32() ? CC_BPF32 : CC_BPF64);
400 if (Outs.size() > MaxArgs)
403 for (auto &Arg : Outs) {
502 const SmallVectorImpl<ISD::OutputArg> &Outs,
520 CCInfo.AnalyzeReturn(Outs, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsCallLowering.cpp | 399 SmallVector<ISD::OutputArg, 8> Outs;
400 subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
405 CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
406 setLocInfo(ArgLocs, Outs);
566 SmallVector<ISD::OutputArg, 8> Outs;
567 subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
582 CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
583 setLocInfo(ArgLocs, Outs);
|
| MipsISelLowering.cpp | 3143 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3202 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
3256 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3326 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3762 const SmallVectorImpl<ISD::OutputArg> &Outs,
3766 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3792 const SmallVectorImpl<ISD::OutputArg> &Outs,
3804 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3845 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 413 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
428 return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
536 const SmallVectorImpl<ISD::OutputArg> &Outs,
547 CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
598 bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
616 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
619 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
621 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
629 for (unsigned I = 0, E = Outs.size(); I != E; ++I)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 441 const SmallVectorImpl<ISD::OutputArg> &Outs) {
442 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
555 const SmallVectorImpl<ISD::OutputArg> &Outs) {
556 State.AnalyzeReturn(Outs, RetCC_MSP430);
589 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
608 Outs, OutVals, Ins, dl, DAG, InVals);
726 const SmallVectorImpl<ISD::OutputArg> &Outs,
730 return CCInfo.CheckReturn(Outs, RetCC_MSP430);
736 const SmallVectorImpl<ISD::OutputArg> &Outs,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 1227 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1264 CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1266 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
1427 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1431 return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1434 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1441 const SmallVectorImpl<ISD::OutputArg> &Outs,
1455 CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1457 analyzeReturnValues(Outs, CCInfo)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 1704 SmallVector<ISD::OutputArg, 4> Outs;
1705 GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1710 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
|
| PPCISelLowering.cpp | 4690 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4714 for (const ISD::OutputArg& Param : Outs) {
4774 const SmallVectorImpl<ISD::OutputArg> &Outs,
4808 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4814 needStackSlotPassParameters(Subtarget, Outs))
4848 needStackSlotPassParameters(Subtarget, Outs))
4850 else if (!CB && needStackSlotPassParameters(Subtarget, Outs))
5564 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5580 Callee, CallConv, CB, isVarArg, Outs, Ins, DAG)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 893 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
899 if (CallConv == CallingConv::WASM_EmscriptenInvoke && Outs.size() >= 2 &&
900 Outs[0].Flags.isSRet()) {
901 std::swap(Outs[0], Outs[1]);
908 for (unsigned I = 0; I < Outs.size(); ++I) {
909 const ISD::OutputArg &Out = Outs[I];
951 CLI.Outs.push_back(Arg);
959 CLI.Outs.push_back(Arg)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 1034 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1054 Outs, OutVals, Ins, dl, DAG, InVals);
1108 bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
1122 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1424 const SmallVectorImpl<ISD::OutputArg> &Outs,
1428 if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
1438 const SmallVectorImpl<ISD::OutputArg> &Outs,
1458 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 3771 SmallVector<ISD::OutputArg, 4> Outs;
3772 GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
3779 CCInfo.AnalyzeReturn(Outs, RetCC);
3826 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
3829 bool IsZExt = Outs[0].Flags.isZExt();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 2093 SmallVector<ISD::OutputArg, 4> Outs;
2094 GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
2099 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2134 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2135 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 184 const SmallVectorImpl<ISD::OutputArg> &Outs,
190 return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
191 return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
200 const SmallVectorImpl<ISD::OutputArg> &Outs,
212 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
214 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
404 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
413 bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 181 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
182 if (Outs.empty())
185 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
471 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
481 StructReturnType SR = callIsStructReturn(Outs);
505 MF.getFunction().hasStructRetAttr(), CLI.RetTy, Outs, OutVals, Ins,
526 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
558 if (!Outs.empty() && Outs.back().Flags.isInAlloca())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 146 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
191 // stay in sync with Ins/Outs.
1246 const SmallVectorImpl<ISD::OutputArg> &Outs, MaybeAlign retAlignment,
1301 if (!Outs[OIdx].Flags.isByVal()) {
1312 // update the index for Outs
1320 assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
1321 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
1346 Align align = Outs[OIdx].Flags.getNonZeroByValAlign();
1410 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 197 const SmallVectorImpl<ISD::OutputArg> &Outs,
201 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
202 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
208 const SmallVectorImpl<ISD::OutputArg> &Outs,
221 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
293 const SmallVectorImpl<ISD::OutputArg> &Outs,
304 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
719 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
735 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 1212 SmallVector<ISD::OutputArg, 4> Outs;
1213 GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1218 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1251 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1257 if (Outs[0].Flags.isSExt())
1263 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetLowering.h | 3729 SmallVector<ISD::OutputArg, 32> Outs;
3912 /// DAG. The outgoing arguments to the call are described by the Outs array,
3926 /// described by the Outs array can fit into the return registers. If false
3930 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3938 /// by the Outs array, into the specified DAG. The implementation should
3942 const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
4650 SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 1310 static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1311 for (unsigned i = 0; i < Outs.size(); ++i)
1312 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
1519 SmallVectorImpl<ISD::OutputArg> &Outs) {
1532 if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
1543 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1557 VerifyVectorTypes(Outs);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 2500 const SmallVectorImpl<ISD::OutputArg> &Outs,
2510 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
2516 const SmallVectorImpl<ISD::OutputArg> &Outs,
2523 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
2529 Info->setIfReturnsVoid(Outs.empty());
2541 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2848 const SmallVectorImpl<ISD::OutputArg> &Outs,
2903 if (Outs.empty())
2909 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
2937 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 6934 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet,
6936 unsigned NumArgs = Outs.size();
6940 FirstMaskArgument = preAssignMask(Outs);
6943 MVT ArgVT = Outs[i].VT;
6944 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
6945 Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
6949 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this,
7369 auto &Outs = CLI.Outs;
7400 auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet()
[all...] |
