| /src/external/gpl3/gcc.old/dist/libgcc/config/bfin/ |
| crtn.S | 39 P3 = [SP++];
48 P3 = [SP++];
|
| /src/external/gpl3/gcc/dist/libgcc/config/bfin/ |
| crtn.S | 39 P3 = [SP++];
48 P3 = [SP++];
|
| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| c_comp3op_pr_plus_pr_sh1.s | 10 imm32 p3, 0xdef01234;
17 P3 = P1 + ( P3 << 1 );
24 CHECKREG p3, 0x5AE17E35;
32 imm32 p3, 0xdef01224;
39 P3 = P2 + ( P3 << 1 );
46 CHECKREG p3, 0xC149F2CC;
54 imm32 p3, 0xdef01233;
59 P1 = P3 + ( P1 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 10 imm32 p3, 0xdef01234;
17 P3 = P1 + ( P3 << 2 );
24 CHECKREG p3, 0x2C17DE7B;
32 imm32 p3, 0xdef01224;
39 P3 = P2 + ( P3 << 2 );
46 CHECKREG p3, 0x2C1B4B6C;
54 imm32 p3, 0xdef01233;
59 P1 = P3 + ( P1 << 2 )
[all...] |
| c_dsp32mac_pair_a0.s | 25 P3 = A0.w;
38 CHECKREG p3, 0xF2CF3598;
55 P3 = A0.w;
68 CHECKREG p3, 0xFFA518F6;
84 P3 = A0.w;
97 CHECKREG p3, 0xF8876658;
113 P3 = A0.w;
126 CHECKREG p3, 0xFF1FB35E;
|
| c_ldimmhalf_lz_pr.s | 13 P3 = 0x0007 (Z);
20 CHECKREG p3, 0x00000007;
28 P3 = 0x0070 (Z);
36 CHECKREG p3, 0x00000070;
44 P3 = 0x0700 (Z);
51 CHECKREG p3, 0x00000700;
59 P3 = 0x7000 (Z);
66 CHECKREG p3, 0x00007000;
|
| c_ldimmhalf_lzhi_pr.s | 17 P3 = 0x0007 (Z);
18 P3.H = 0x0006;
29 CHECKREG p3, 0x00060007;
39 P3 = 0x0070 (Z);
40 P3.H = 0x0060;
52 CHECKREG p3, 0x00600070;
62 P3 = 0x0700 (Z);
63 P3.H = 0x0600;
74 CHECKREG p3, 0x06000700;
84 P3 = 0x7000 (Z)
[all...] |
| c_ptr2op_pr_sft_2_1.s | 10 imm32 p3, 0xd0d61407;
17 P3 = P1 << 2;
24 CHECKREG p3, 0x09212030;
32 imm32 p3, 0x60761007;
39 P3 = P2;
46 CHECKREG p3, 0x26041005;
54 imm32 p3, 0x20061007;
59 P1 = P3 << 2;
60 P2 = P3 >> 1;
61 P3 = P3 >> 2
[all...] |
| c_pushpopmultiple_preg.s | 15 P3 = 0xa3 (X);
21 P3 = 0;
27 CHECKREG p3, 0x000000a3;
32 P3 = 0xb3 (X);
37 P3 = 0;
43 CHECKREG p3, 0x000000b3;
47 P3 = 0xc3 (X);
51 P3 = 0;
57 CHECKREG p3, 0x000000c3;
69 CHECKREG p3, 0x000000c3
[all...] |
| c_compi2opp_pr_eq_i7_n.s | 11 P3 = -3;
19 CHECKREG p3, -3;
28 P3 = -11;
36 CHECKREG p3, -11;
45 P3 = -19;
53 CHECKREG p3, -19;
62 P3 = -27;
70 CHECKREG p3, -27;
79 P3 = -35;
87 CHECKREG p3, -35
[all...] |
| c_compi2opp_pr_eq_i7_p.s | 11 P3 = 3;
18 CHECKREG p3, 3;
26 P3 = 11;
33 CHECKREG p3, 11;
41 P3 = 19;
48 CHECKREG p3, 19;
56 P3 = 27;
63 CHECKREG p3, 27;
72 P3 = 35;
80 CHECKREG p3, 35
[all...] |
| c_dsp32mac_pair_a0_i.s | 25 P3 = A0.w;
38 CHECKREG p3, 0xF9679ACC;
55 P3 = A0.w;
68 CHECKREG p3, 0xFC7F6BD4;
84 P3 = A0.w;
97 CHECKREG p3, 0x01A40FD3;
113 P3 = A0.w;
126 CHECKREG p3, 0xFF911149;
143 P3 = A0.w;
156 CHECKREG p3, 0xF9679ACC
[all...] |
| c_dsp32mac_pair_a0_is.s | 24 P3 = A1.w;
37 CHECKREG p3, 0xFFCD4859;
53 P3 = A0.w;
66 CHECKREG p3, 0xFC43C021;
82 P3 = A0.w;
95 CHECKREG p3, 0xFC43B32C;
111 P3 = A0.w;
124 CHECKREG p3, 0xFF8FD9AF;
141 P3 = A0.w;
154 CHECKREG p3, 0xF9679ACC
[all...] |
| c_dsp32mac_pair_a0_m.s | 25 P3 = A0.w;
38 CHECKREG p3, 0xF2CF3598;
55 P3 = A0.w;
68 CHECKREG p3, 0xFFA518F6;
84 P3 = A0.w;
97 CHECKREG p3, 0xC39B0E3E;
113 P3 = A0.w;
126 CHECKREG p3, 0x00DA3B3C;
|
| c_dsp32mac_pair_a0_s.s | 24 P3 = A0.w;
37 CHECKREG p3, 0xF2CF3598;
53 P3 = A0.w;
66 CHECKREG p3, 0xFE1EED30;
82 P3 = A0.w;
95 CHECKREG p3, 0xF18A7660;
111 P3 = A0.w;
124 CHECKREG p3, 0x00CA008C;
141 P3 = A0.w;
154 CHECKREG p3, 0xF2CF3598
[all...] |
| c_dsp32mac_pair_a0_u.s | 24 P3 = A0.w;
37 CHECKREG p3, 0x60FC9ACC;
53 P3 = A0.w;
66 CHECKREG p3, 0x05183CD2;
82 P3 = A0.w;
95 CHECKREG p3, 0x2E395300;
111 P3 = A0.w;
124 CHECKREG p3, 0xA8467E26;
141 P3 = A0.w;
154 CHECKREG p3, 0xBB41743F
[all...] |
| c_dsp32mac_pair_a1.s | 24 P3 = A1.w;
37 CHECKREG p3, 0xE8616512;
53 P3 = A1.w;
66 CHECKREG p3, 0x0117ACDA;
82 P3 = A1.w;
95 CHECKREG p3, 0xCABE16DA;
111 P3 = A1.w;
124 CHECKREG p3, 0x09DF3640;
|
| c_dsp32mac_pair_a1_i.s | 24 P3 = A1.w;
37 CHECKREG p3, 0xF9C9E563;
53 P3 = A1.w;
66 CHECKREG p3, 0xFF8595CD;
82 P3 = A1.w;
95 CHECKREG p3, 0xE54D2A3B;
111 P3 = A1.w;
124 CHECKREG p3, 0xB76A2BD8;
140 P3 = A1.w;
153 CHECKREG p3, 0xF81E0AF0
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| c_comp3op_pr_plus_pr_sh1.s | 10 imm32 p3, 0xdef01234;
17 P3 = P1 + ( P3 << 1 );
24 CHECKREG p3, 0x5AE17E35;
32 imm32 p3, 0xdef01224;
39 P3 = P2 + ( P3 << 1 );
46 CHECKREG p3, 0xC149F2CC;
54 imm32 p3, 0xdef01233;
59 P1 = P3 + ( P1 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 10 imm32 p3, 0xdef01234;
17 P3 = P1 + ( P3 << 2 );
24 CHECKREG p3, 0x2C17DE7B;
32 imm32 p3, 0xdef01224;
39 P3 = P2 + ( P3 << 2 );
46 CHECKREG p3, 0x2C1B4B6C;
54 imm32 p3, 0xdef01233;
59 P1 = P3 + ( P1 << 2 )
[all...] |
| c_dsp32mac_pair_a0.s | 25 P3 = A0.w;
38 CHECKREG p3, 0xF2CF3598;
55 P3 = A0.w;
68 CHECKREG p3, 0xFFA518F6;
84 P3 = A0.w;
97 CHECKREG p3, 0xF8876658;
113 P3 = A0.w;
126 CHECKREG p3, 0xFF1FB35E;
|
| c_ldimmhalf_lz_pr.s | 13 P3 = 0x0007 (Z);
20 CHECKREG p3, 0x00000007;
28 P3 = 0x0070 (Z);
36 CHECKREG p3, 0x00000070;
44 P3 = 0x0700 (Z);
51 CHECKREG p3, 0x00000700;
59 P3 = 0x7000 (Z);
66 CHECKREG p3, 0x00007000;
|
| c_ldimmhalf_lzhi_pr.s | 17 P3 = 0x0007 (Z);
18 P3.H = 0x0006;
29 CHECKREG p3, 0x00060007;
39 P3 = 0x0070 (Z);
40 P3.H = 0x0060;
52 CHECKREG p3, 0x00600070;
62 P3 = 0x0700 (Z);
63 P3.H = 0x0600;
74 CHECKREG p3, 0x06000700;
84 P3 = 0x7000 (Z)
[all...] |
| c_ptr2op_pr_sft_2_1.s | 10 imm32 p3, 0xd0d61407;
17 P3 = P1 << 2;
24 CHECKREG p3, 0x09212030;
32 imm32 p3, 0x60761007;
39 P3 = P2;
46 CHECKREG p3, 0x26041005;
54 imm32 p3, 0x20061007;
59 P1 = P3 << 2;
60 P2 = P3 >> 1;
61 P3 = P3 >> 2
[all...] |
| c_pushpopmultiple_preg.s | 15 P3 = 0xa3 (X);
21 P3 = 0;
27 CHECKREG p3, 0x000000a3;
32 P3 = 0xb3 (X);
37 P3 = 0;
43 CHECKREG p3, 0x000000b3;
47 P3 = 0xc3 (X);
51 P3 = 0;
57 CHECKREG p3, 0x000000c3;
69 CHECKREG p3, 0x000000c3
[all...] |
