| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| c_regmv_dr_pr.s | 20 P4 = R0;
25 CHECKREG p4, 0x20001001;
31 P4 = R1;
36 CHECKREG p4, 0x20021003;
42 P4 = R2;
47 CHECKREG p4, 0x20041005;
53 P4 = R3;
58 CHECKREG p4, 0x20061007;
64 P4 = R4;
69 CHECKREG p4, 0x20081009
[all...] |
| c_regmv_pr_pr.s | 11 imm32 p4, 0x20081009;
17 imm32 p4, 0x20081009;
22 P4 = P1;
27 CHECKREG p4, 0x20021003;
33 imm32 p4, 0x20081009;
38 P4 = P2;
43 CHECKREG p4, 0x20041005;
49 imm32 p4, 0x20081009;
52 P1 = P4;
53 P2 = P4;
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 11 imm32 p4, 0x23451899;
18 P4 = P1 + ( P4 << 1 );
25 CHECKREG p4, 0xE38B8AFF;
33 imm32 p4, 0x23456829;
40 P4 = P2 + ( P4 << 1 );
47 CHECKREG p4, 0x49F49ED6;
55 imm32 p4, 0x23456893;
62 P4 = P3 + ( P4 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 11 imm32 p4, 0x23451899;
18 P4 = P1 + ( P4 << 2 );
25 CHECKREG p4, 0x3D6BF80F;
33 imm32 p4, 0x23456829;
40 P4 = P2 + ( P4 << 2 );
47 CHECKREG p4, 0x3D70A380;
55 imm32 p4, 0x23456893;
62 P4 = P3 + ( P4 << 2 )
[all...] |
| c_dsp32mac_pair_a0.s | 27 P4 = A0.w;
39 CHECKREG p4, 0xF70DA834;
57 P4 = A0.w;
69 CHECKREG p4, 0xFFBC8F22;
86 P4 = A0.w;
98 CHECKREG p4, 0x1EA0F4F8;
115 P4 = A0.w;
127 CHECKREG p4, 0xF750102E;
|
| c_ldimmhalf_lz_pr.s | 14 P4 = 0x0009 (Z);
21 CHECKREG p4, 0x00000009;
29 P4 = 0x0090 (Z);
37 CHECKREG p4, 0x00000090;
45 P4 = 0x0900 (Z);
52 CHECKREG p4, 0x00000900;
60 P4 = 0x9000 (Z);
67 CHECKREG p4, 0x00009000;
|
| c_ldimmhalf_lzhi_pr.s | 19 P4 = 0x0009 (Z);
20 P4.H = 0x0008;
30 CHECKREG p4, 0x00080009;
41 P4 = 0x0090 (Z);
42 P4.H = 0x0080;
53 CHECKREG p4, 0x00800090;
64 P4 = 0x0900 (Z);
65 P4.H = 0x0800;
75 CHECKREG p4, 0x08000900;
86 P4 = 0x9000 (Z)
[all...] |
| c_ptr2op_pr_sft_2_1.s | 11 imm32 p4, 0xa00a1089;
18 P4 = P1 >> 1;
25 CHECKREG p4, 0x61242406;
33 imm32 p4, 0x20081009;
40 P4 = P2;
47 CHECKREG p4, 0x26041005;
55 imm32 p4, 0x20081009;
62 P4 = P3 << 2;
69 CHECKREG p4, 0x20061004;
77 imm32 p4, 0x250d1009
[all...] |
| c_pushpopmultiple_preg.s | 16 P4 = 0xa4 (X);
22 P4 = 0;
28 CHECKREG p4, 0x000000a4;
33 P4 = 0xb4 (X);
38 P4 = 0;
44 CHECKREG p4, 0x000000b4;
48 P4 = 0xc4 (X);
52 P4 = 0;
58 CHECKREG p4, 0x000000c4;
61 P4 = 0xd4 (X)
[all...] |
| dotproduct2.s | 18 P4 = 63;
19 LSETUP ( loop1 , loop1 ) LC0 = P4;
|
| stk6.s | 14 P4 = (8+6); // 8 data registers and 6 pointer registers are being stored.
15 LSETUP ( ls0 , le0 ) LC0 = P4;
35 R0 = P4; DBGA ( R0.L , 13 );
54 R0 = P4; DBGA ( R0.L , 13 );
|
| c_compi2opp_pr_eq_i7_n.s | 12 P4 = -4;
20 CHECKREG p4, -4;
29 P4 = -12;
37 CHECKREG p4, -12;
46 P4 = -20;
54 CHECKREG p4, -20;
63 P4 = -28;
71 CHECKREG p4, -28;
80 P4 = -36;
88 CHECKREG p4, -36
[all...] |
| c_compi2opp_pr_eq_i7_p.s | 12 P4 = 4;
19 CHECKREG p4, 4;
27 P4 = 12;
34 CHECKREG p4, 12;
42 P4 = 20;
49 CHECKREG p4, 20;
57 P4 = 28;
64 CHECKREG p4, 28;
73 P4 = 36;
81 CHECKREG p4, 36
[all...] |
| c_dsp32mac_pair_a0_i.s | 27 P4 = A0.w;
39 CHECKREG p4, 0xF857FE25;
57 P4 = A0.w;
69 CHECKREG p4, 0xFC8B26EA;
86 P4 = A0.w;
98 CHECKREG p4, 0x0B2A737B;
115 P4 = A0.w;
127 CHECKREG p4, 0x007295B5;
145 P4 = A0.w;
157 CHECKREG p4, 0xFA773773
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| c_regmv_dr_pr.s | 20 P4 = R0;
25 CHECKREG p4, 0x20001001;
31 P4 = R1;
36 CHECKREG p4, 0x20021003;
42 P4 = R2;
47 CHECKREG p4, 0x20041005;
53 P4 = R3;
58 CHECKREG p4, 0x20061007;
64 P4 = R4;
69 CHECKREG p4, 0x20081009
[all...] |
| c_regmv_pr_pr.s | 11 imm32 p4, 0x20081009;
17 imm32 p4, 0x20081009;
22 P4 = P1;
27 CHECKREG p4, 0x20021003;
33 imm32 p4, 0x20081009;
38 P4 = P2;
43 CHECKREG p4, 0x20041005;
49 imm32 p4, 0x20081009;
52 P1 = P4;
53 P2 = P4;
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 11 imm32 p4, 0x23451899;
18 P4 = P1 + ( P4 << 1 );
25 CHECKREG p4, 0xE38B8AFF;
33 imm32 p4, 0x23456829;
40 P4 = P2 + ( P4 << 1 );
47 CHECKREG p4, 0x49F49ED6;
55 imm32 p4, 0x23456893;
62 P4 = P3 + ( P4 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 11 imm32 p4, 0x23451899;
18 P4 = P1 + ( P4 << 2 );
25 CHECKREG p4, 0x3D6BF80F;
33 imm32 p4, 0x23456829;
40 P4 = P2 + ( P4 << 2 );
47 CHECKREG p4, 0x3D70A380;
55 imm32 p4, 0x23456893;
62 P4 = P3 + ( P4 << 2 )
[all...] |
| c_dsp32mac_pair_a0.s | 27 P4 = A0.w;
39 CHECKREG p4, 0xF70DA834;
57 P4 = A0.w;
69 CHECKREG p4, 0xFFBC8F22;
86 P4 = A0.w;
98 CHECKREG p4, 0x1EA0F4F8;
115 P4 = A0.w;
127 CHECKREG p4, 0xF750102E;
|
| c_ldimmhalf_lz_pr.s | 14 P4 = 0x0009 (Z);
21 CHECKREG p4, 0x00000009;
29 P4 = 0x0090 (Z);
37 CHECKREG p4, 0x00000090;
45 P4 = 0x0900 (Z);
52 CHECKREG p4, 0x00000900;
60 P4 = 0x9000 (Z);
67 CHECKREG p4, 0x00009000;
|
| c_ldimmhalf_lzhi_pr.s | 19 P4 = 0x0009 (Z);
20 P4.H = 0x0008;
30 CHECKREG p4, 0x00080009;
41 P4 = 0x0090 (Z);
42 P4.H = 0x0080;
53 CHECKREG p4, 0x00800090;
64 P4 = 0x0900 (Z);
65 P4.H = 0x0800;
75 CHECKREG p4, 0x08000900;
86 P4 = 0x9000 (Z)
[all...] |
| c_ptr2op_pr_sft_2_1.s | 11 imm32 p4, 0xa00a1089;
18 P4 = P1 >> 1;
25 CHECKREG p4, 0x61242406;
33 imm32 p4, 0x20081009;
40 P4 = P2;
47 CHECKREG p4, 0x26041005;
55 imm32 p4, 0x20081009;
62 P4 = P3 << 2;
69 CHECKREG p4, 0x20061004;
77 imm32 p4, 0x250d1009
[all...] |
| c_pushpopmultiple_preg.s | 16 P4 = 0xa4 (X);
22 P4 = 0;
28 CHECKREG p4, 0x000000a4;
33 P4 = 0xb4 (X);
38 P4 = 0;
44 CHECKREG p4, 0x000000b4;
48 P4 = 0xc4 (X);
52 P4 = 0;
58 CHECKREG p4, 0x000000c4;
61 P4 = 0xd4 (X)
[all...] |
| dotproduct2.s | 18 P4 = 63;
19 LSETUP ( loop1 , loop1 ) LC0 = P4;
|
| stk6.s | 14 P4 = (8+6); // 8 data registers and 6 pointer registers are being stored.
15 LSETUP ( ls0 , le0 ) LC0 = P4;
35 R0 = P4; DBGA ( R0.L , 13 );
54 R0 = P4; DBGA ( R0.L , 13 );
|
