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      1 /*	$NetBSD: algor_p4032reg.h,v 1.4 2024/05/24 20:13:37 andvar Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Memory map and register definitions for the Algorithmics P-4032.
     34  */
     35 
     36 #define	P4032_MEMORY		0x00000000UL	/* onboard DRAM memory */
     37 			/* 	256 MB		*/
     38 #define	P4032_ISAMEM		0x10000000UL	/* ISA window of PCI memory */
     39 			/*	8MB		*/
     40 #define	P4032_PCIMEM		0x11000000UL	/* PCI memory window */
     41 			/*	112MB		*/
     42 #define	P4032_PCIIO		0x1ed00000UL	/* PCI I/O window */
     43 			/*	1MB		*/
     44 #define	P4032_PCICFG		0x1ee00000UL	/* PCI config space */
     45 			/*	1MB		*/
     46 #define	P4032_V962PBC		0x1ef00000UL	/* V962PBC PCI controller */
     47 			/*	64KB		*/
     48 #define	P4032_CFGBOOT_W		0x1fc00000UL	/* configured bootstrap (W) */
     49 			/*	1MB or 512KB	*/
     50 #define	P4032_SOCKET_W		0x1fd00000UL	/* socket EPROM (W) */
     51 			/*	512KB		*/
     52 #define	P4032_FLASH_W		0x1fe00000UL	/* flash (W) */
     53 			/*	1MB		*/
     54 #define	P4032_RTC		0x1ff00000UL	/* RTC */
     55 #define	P4032_PCKBC		0x1ff10000UL	/* keyboard controller */
     56 #define	P4032_LED		0x1ff20010UL	/* LED display (4reg) */
     57 #define	P4032_LCD		0x1ff30000UL	/* LCD display */
     58 #define	P4032_GPIO		0x1ff40000UL	/* General purpose I/O */
     59 #define	P4032_FDC		0x1ff807c0UL	/* floppy controller */
     60 #define	P4032_GAME		0x1ff80800UL	/* game port (unused) */
     61 #define	P4032_COM2		0x1ff80be0UL	/* COM2 */
     62 #define	P4032_LPT		0x1ff80de0UL	/* parallel port */
     63 #define	P4032_COM1		0x1ff80fe0UL	/* COM1 */
     64 #define	P4032_IRR0		0x1ff90000UL	/* interrupt req. 0 */
     65 #define	P4032_IRR1		0x1ff90004UL	/* interrupt req. 1 */
     66 #define	P4032_IRR2		0x1ff90008UL	/* interrupt req. 2 */
     67 #define	P4032_XBAR0		0x1ff9000cUL	/* interrupt crossbar 0 */
     68 #define	P4032_XBAR1		0x1ff90010UL	/* interrupt crossbar 1 */
     69 #define	P4032_XBAR2		0x1ff90014UL	/* interrupt crossbar 2 */
     70 #define	P4032_VERSION		0x1ff9001cUL	/* board version */
     71 #define	P4032_FLOPPY_DMA_ACK	0x1ffa0fd4UL	/* floppy "DMA ACK" */
     72 #define	P4032_BOARD_CONFIG	0x1ffb0000UL	/* board configuration */
     73 #define	P4032_DRAM_CONFIG	0x1ffc0000UL	/* DRAM configuration */
     74 #define	P4032_OPTION		0x1ffd0000UL	/* option register */
     75 #define	P4032_PCIMEM_HI		0x20000000UL	/* PCI memory high window */
     76 			/*	3.5GB		*/
     77 
     78 /* IRR0 (8-bit devices) */
     79 #define	IRR0_PCICTLR	0x01	/* PCI controller */
     80 #define	IRR0_FLOPPY	0x02	/* floppy controller */
     81 #define	IRR0_PCKBC	0x04	/* keyboard controller */
     82 #define	IRR0_COM1	0x08	/* COM1 */
     83 #define	IRR0_COM2	0x10	/* COM2 */
     84 #define	IRR0_LPT	0x20	/* centronics */
     85 #define	IRR0_GPIO	0x40	/* general purpose I/O */
     86 #define	IRR0_RTC	0x80	/* real-time clock */
     87 
     88 /* IRR1 (error/clear) */
     89 #define	IRR1_DEBUG	0x01	/* debug switch */
     90 #define	IRR1_POWERFAIL	0x02	/* power fail */
     91 #define	IRR1_BUSERR	0x04	/* bus error */
     92 #define	IRR1_LPT_ACK	0x20	/* centronics interrupt ack. */
     93 
     94 /* IRR2 (PCI) */
     95 #define	IRR2_FLOPPY_DMA	0x08	/* floppy DMA request */
     96 #define	IRR2_PCIIRQ0	0x10	/* PCIIRQ 0 */
     97 #define	IRR2_PCIIRQ1	0x20	/* PCIIRQ 1 */
     98 #define	IRR2_PCIIRQ2	0x40	/* PCIIRQ 2 */
     99 #define	IRR2_PCIIRQ3	0x80	/* PCIIRQ 3 */
    100 
    101 /*
    102  * The Algorithmics PMON initializes two DMA windows:
    103  *
    104  *	PCI 8000.0000 -> Phys 0000.0000 (256MB)
    105  *	PCI c000.0000 -> Phys 0000.0000 (256MB)
    106  *
    107  * The latter has prefetching enabled, the former disabled, on
    108  * V962 < rev B2, which have broken DMA FIFOs.  The latter is
    109  * given to the on-board Ethernet.
    110  */
    111 #define	P4032_DMA_PCI_PCIBASE	0x80000000UL
    112 #define	P4032_DMA_PCI_PF_PCIBASE 0xc0000000UL
    113 #define	P4032_DMA_PCI_PHYSBASE	0x00000000UL
    114 #define	P4032_DMA_PCI_SIZE	(256 * 1024 * 1024)
    115