1 /* $NetBSD: p5pbreg.h,v 1.7 2012/07/11 17:13:31 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Reverse engineered Phase5 PCI bridge memory map (firmware 44.71): 34 * 35 * 0xFFFA0000 - PCI register space, 64KB 36 * 0xFFFC0000 - PCI configuration mechanism #1 data, 128KB 37 * 0xFFFE0000 - (unknown, probably PCI bridge configuration registers, 4KB) 38 * 39 * 0xE0000000 - Permedia RAM on CVPPC/BVPPC (1st aperture), 8MB 40 * 0xE0800000 - Permedia RAM on CVPPC/BVPPC (2nd aperture), 8MB 41 * 0xE1000000 - Permedia registers on CVPPC/BVPPC, 128KB 42 * 43 * 0x80000000 - PCI cards memory space on G-REX, variable size 44 * 45 * Note: this map may not look the same for every firmware revision. 46 * 47 * The bridge is certainly capable of DMA, but this needs further reverse 48 * engineering. 49 */ 50 #ifndef _AMIGA_P5PBREG_H_ 51 52 #define P5BUS_PCI_CONF_BASE 0xFFFC0000 53 #define P5BUS_PCI_CONF_SIZE 0x00020000 /* up to 128kB */ 54 55 #define OFF_PCI_CONF_DATA 0x00000000 /* also 0 on CVPPC */ 56 #define OFF_PCI_DEVICE 0x00001000 57 #define OFF_PCI_FUNCTION 0x00000100 58 59 #define P5BUS_PCI_IO_BASE 0xFFFA0000 60 #define P5BUS_PCI_IO_SIZE 0x00010000 /* 64kB */ 61 62 /* Bridge configuration */ 63 #define P5BUS_BRIDGE_BASE 0xFFFE0000 64 #define P5BUS_BRIDGE_SIZE 0x00001000 /* 64kB, 4kB on some fw revs */ 65 66 #define OFF_BRIDGE_ENDIAN 0x0000 /* PCI_BRIDGE_BASE + offset */ 67 #define P5BUS_BRIDGE_ENDIAN_BIG 0x02 /* to switch into BE mode */ 68 #define OFF_BRIDGE_INTR 0x0010 /* ? XXX interrupt enable? */ 69 #define P5BUS_BRIDGE_INTR_INT2 0x01 /* ? XXX INT2? */ 70 71 /* CVPPC/BVPPC defaults. */ 72 #define P5BUS_PCI_MEM_BASE 0xE0000000 73 /* #define P5BUS_PCI_MEM_BASE 0x80000000 */ /* default on G-REX */ 74 #define P5BUS_PCI_MEM_SIZE 0x01020000 75 76 /* typical configuration of Permedia 2 on CVPPC/BVPPC */ 77 #define OFF_P2_APERTURE_1 0x0 78 #define OFF_P2_APERTURE_2 0x00800000 79 #define OFF_P2_REGS 0x01000000 80 /* #define OFF_P2_REGS 0x0F000000 */ /* ? alt. Permedia regs */ 81 82 /* Permedia 2 vendor and product IDs, for CVPPC/BVPPC probe. */ 83 #define P5PB_PM2_VENDOR_ID 0x104C 84 #define P5PB_PM2_PRODUCT_ID 0x3D07 85 86 #endif /* _AMIGA_P5PBREG_H_ */ 87 88
Indexes created Tue Sep 30 20:09:53 GMT 2025