1 /* $NetBSD: p5reg.h,v 1.3 2022/02/16 23:49:26 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2000 Adam Ciarcinski. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Adam Ciarcinski for 18 * the NetBSD project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _P5REG_H_ 35 #define _P5REG_H_ 36 37 #define P5BASE 0xf60000 38 39 /* registers */ 40 #define P5_REG_RESET 0x00 41 #define P5_REG_ENABLE 0x08 42 #define P5_REG_WAITSTATE 0x10 43 #define P5_BPPC_MAGIC 0x13 44 #define P5_REG_SHADOW 0x18 45 #define P5_REG_LOCK 0x20 46 #define P5_REG_INT 0x28 47 #define P5_IPL_EMU 0x30 48 #define P5_INT_LVL 0x38 49 50 /* bit definitions */ 51 #define P5_SET_CLEAR 0x80 52 53 /* REQ_RESET */ 54 #define P5_PPC_RESET 0x10 55 #define P5_M68K_RESET 0x08 56 #define P5_AMIGA_RESET 0x04 57 #define P5_AUX_RESET 0x02 58 #define P5_SCSI_RESET 0x01 59 60 /* REG_WAITSTATE */ 61 #define P5_PPC_WRITE 0x08 62 #define P5_PPC_READ 0x04 63 #define P5_M68K_WRITE 0x02 64 #define P5_M68K_READ 0x01 65 66 /* REG_SHADOW */ 67 #define P5_SELF_RESET 0x40 68 #define P5_SHADOW 0x01 69 70 /* REG_LOCK */ 71 #define P5_MAGIC1 0x40 72 #define P5_MAGIC2 0x20 73 #define P5_MAGIC3 0x10 74 75 /* REG_INT */ 76 #define P5_ENABLE_IPL 0x02 77 #define P5_INT_MASTER 0x01 78 79 /* IPL_EMU */ 80 #define P5_DISABLE_INT 0x40 81 #define P5_M68K_IPL2 0x20 82 #define P5_M68K_IPL1 0x10 83 #define P5_M68K_IPL0 0x08 84 #define P5_PPC_IPL2 0x04 85 #define P5_PPC_IPL1 0x02 86 #define P5_PPC_IPL0 0x01 87 88 #define P5_IPL_MASK 0x07 89 90 /* INT_LVL */ 91 #define P5_LVL7 0x40 92 #define P5_LVL6 0x20 93 #define P5_LVL5 0x10 94 #define P5_LVL4 0x08 95 #define P5_LVL3 0x04 96 #define P5_LVL2 0x02 97 #define P5_LVL1 0x01 98 99 /* macros to read and write P5 registers */ 100 #define P5read(reg, val) \ 101 do { \ 102 (val) = *(volatile unsigned char *)(P5BASE + (reg)); \ 103 __asm volatile("eieio" ::: "memory"); \ 104 } while (0); 105 106 #define P5write(reg, val) \ 107 do { \ 108 *(volatile unsigned char *)(P5BASE + (reg)) = (val); \ 109 __asm volatile("eieio" ::: "memory"); \ 110 } while (0); 111 112 #endif /* _P5REG_H_ */ 113
Indexes created Tue Sep 30 07:10:03 GMT 2025