1 /* $NetBSD: trmreg.h,v 1.2 2012/05/10 03:16:50 macallan Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2001 Rui-Xiang Guo 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Ported from 34 * dc395x_trm.h 35 * 36 * Written for NetBSD 1.4.x by 37 * Erich Chen (erich (at) tekram.com.tw) 38 * 39 * Provided by 40 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 41 */ 42 43 #define TRM_BAR_PIO 0x10 44 /* DC-315 has an MMIO BAR */ 45 #define TRM_BAR_MMIO 0x14 46 47 /* 48 ********************************************************************** 49 * 50 * The SCSI register offset for TRM_S1040 51 * 52 ********************************************************************** 53 */ 54 #define TRM_SCSI_STATUS 0x80 /* SCSI Status (R) */ 55 #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */ 56 #define SCSIXFERDONE 0x0800 /* SCSI transfer done */ 57 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI transfer count to zero */ 58 #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */ 59 #define COMMANDABORT 0x0040 /* SCSI command abort */ 60 #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */ 61 #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */ 62 #define PARITYERROR 0x0008 /* SCSI parity error */ 63 #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */ 64 #define PH_DATA_OUT 0x00 /* Data out phase */ 65 #define PH_DATA_IN 0x01 /* Data in phase */ 66 #define PH_COMMAND 0x02 /* Command phase */ 67 #define PH_STATUS 0x03 /* Status phase */ 68 #define PH_BUS_FREE 0x05 /* Invalid phase as bus free */ 69 #define PH_MSG_OUT 0x06 /* Message out phase */ 70 #define PH_MSG_IN 0x07 /* Message in phase */ 71 #define TRM_SCSI_CONTROL 0x80 /* SCSI Control (W) */ 72 #define DO_CLRATN 0x0400 /* Clear ATN */ 73 #define DO_SETATN 0x0200 /* Set ATN */ 74 #define DO_CMDABORT 0x0100 /* Abort SCSI command */ 75 #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */ 76 #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */ 77 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */ 78 #define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */ 79 #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */ 80 #define TRM_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter (R) */ 81 #define SCSI_FIFOCNT_MASK 0x1F /* 5 bits SCSI FIFO counter */ 82 #define SCSI_FIFO_EMPTY 0x40 /* SCSI FIFO Empty */ 83 #define TRM_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */ 84 #define TRM_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */ 85 #define INT_SCAM 0x80 /* SCAM selection interrupt */ 86 #define INT_SELECT 0x40 /* Selection interrupt */ 87 #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */ 88 #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */ 89 #define INT_RESELECTED 0x08 /* Reselected interrupt */ 90 #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */ 91 #define INT_BUSSERVICE 0x02 /* Bus service interrupt */ 92 #define INT_CMDDONE 0x01 /* SCSI command done interrupt */ 93 #define TRM_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */ 94 /* 95 * Bit Name Definition 96 * 07-05 0 RSVD Reversed. Always 0. 97 * 04 0 OFFSET4 Reversed for LVDS. Always 0. 98 * 03-00 0 OFFSET[03:00] Offset number from 0 to 15 99 */ 100 #define TRM_SCSI_SYNC 0x85 /* SCSI Sync Control (R/W) */ 101 #define LVDS_SYNC 0x20 /* Enable LVDS sync */ 102 #define WIDE_SYNC 0x10 /* Enable WIDE sync */ 103 #define ALT_SYNC 0x08 /* Enable Fast-20 alternate sync */ 104 /* 105 * SYNCM 7 6 5 4 3 2 1 0 106 * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 107 * Default 0 0 0 0 0 0 0 0 108 * 109 * Bit Name Definition 110 * 07-06 0 RSVD Reversed. Always read 0 111 * 05 0 LVDS Reversed. Always read 0 112 * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer. 113 * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. 114 * 115 * @@ When this bit is set, 116 * the synchronous period bits 2:0 117 * in the Synchronous Mode register 118 * are used to transfer data 119 * at the Fast-20 rate. 120 * @@ When this bit is reset, 121 * the synchronous period bits 2:0 122 * in the Synchronous Mode Register 123 * are used to transfer data 124 * at the Fast-40 rate. 125 * 126 * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate. 127 * These 3 bits specify 128 * the Synchronous SCSI Transfer Rate 129 * for Fast-20 and Fast-10. 130 * These bits are also reset 131 * by a SCSI Bus reset. 132 * 133 * For Fast-10 bit ALTPD = 0 and LVDS = 0 134 * and bit2,bit1,bit0 is defined as follows : 135 * 136 * 000 100ns, 10.0 Mbytes/s 137 * 001 150ns, 6.6 Mbytes/s 138 * 010 200ns, 5.0 Mbytes/s 139 * 011 250ns, 4.0 Mbytes/s 140 * 100 300ns, 3.3 Mbytes/s 141 * 101 350ns, 2.8 Mbytes/s 142 * 110 400ns, 2.5 Mbytes/s 143 * 111 450ns, 2.2 Mbytes/s 144 * 145 * For Fast-20 bit ALTPD = 1 and LVDS = 0 146 * and bit2,bit1,bit0 is defined as follows : 147 * 148 * 000 50ns, 20.0 Mbytes/s 149 * 001 75ns, 13.3 Mbytes/s 150 * 010 100ns, 10.0 Mbytes/s 151 * 011 125ns, 8.0 Mbytes/s 152 * 100 150ns, 6.6 Mbytes/s 153 * 101 175ns, 5.7 Mbytes/s 154 * 110 200ns, 5.0 Mbytes/s 155 * 111 250ns, 4.0 Mbytes/s 156 * 157 * For Fast-40 bit ALTPD = 0 and LVDS = 1 158 * and bit2,bit1,bit0 is defined as follows : 159 * 160 * 000 25ns, 40.0 Mbytes/s 161 * 001 50ns, 20.0 Mbytes/s 162 * 010 75ns, 13.3 Mbytes/s 163 * 011 100ns, 10.0 Mbytes/s 164 * 100 125ns, 8.0 Mbytes/s 165 * 101 150ns, 6.6 Mbytes/s 166 * 110 175ns, 5.7 Mbytes/s 167 * 111 200ns, 5.0 Mbytes/s 168 */ 169 #define TRM_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */ 170 #define TRM_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */ 171 #define TRM_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */ 172 #define TRM_SCSI_XCNT 0x88 /* SCSI Transfer Counter (R/W) */ 173 #define SCSI_XCNT_MASK 0x00FFFFFF /* 24 bits SCSI transfer counter */ 174 #define TRM_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */ 175 #define EN_SCAM 0x80 /* Enable SCAM selection intr */ 176 #define EN_SELECT 0x40 /* Enable selection intr */ 177 #define EN_SELTIMEOUT 0x20 /* Enable selection timeout intr */ 178 #define EN_DISCONNECT 0x10 /* Enable bus disconnected intr */ 179 #define EN_RESELECTED 0x08 /* Enable reselected intr */ 180 #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected intr */ 181 #define EN_BUSSERVICE 0x02 /* Enable bus service intr */ 182 #define EN_CMDDONE 0x01 /* Enable SCSI command done intr */ 183 #define TRM_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */ 184 #define PHASELATCH 0x40 /* Enable phase latch */ 185 #define INITIATOR 0x20 /* Enable initiator mode */ 186 #define PARITYCHECK 0x10 /* Enable parity check */ 187 #define BLOCKRST 0x01 /* Disable SCSI reset */ 188 #define TRM_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */ 189 #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */ 190 #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */ 191 #define ACTIVE_NEG 0x02 /* Enable active negation */ 192 #define TRM_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */ 193 #define SCMD_COMP 0x12 /* Command complete */ 194 #define SCMD_SEL_ATN 0x60 /* Selection with ATN */ 195 #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */ 196 #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */ 197 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */ 198 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */ 199 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */ 200 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */ 201 #define SCMD_MSGACCEPT 0xD8 /* Message accept */ 202 /* 203 * Code Command Description 204 * 205 * 02 Enable reselection with FIFO 206 * 40 Select without ATN with FIFO 207 * 60 Select with ATN with FIFO 208 * 64 Select with ATN3 with FIFO 209 * A0 Select with ATN and stop with FIFO 210 * C0 Transfer information out with FIFO 211 * C1 Transfer information out with DMA 212 * C2 Transfer information in with FIFO 213 * C3 Transfer information in with DMA 214 * 12 Initiator command complete with FIFO 215 * 50 Initiator transfer information out sequence without ATN with FIFO 216 * 70 Initiator transfer information out sequence with ATN with FIFO 217 * 74 Initiator transfer information out sequence with ATN3 with FIFO 218 * 52 Initiator transfer information in sequence without ATN with FIFO 219 * 72 Initiator transfer information in sequence with ATN with FIFO 220 * 76 Initiator transfer information in sequence with ATN3 with FIFO 221 * 90 Initiator transfer information out command complete with FIFO 222 * 92 Initiator transfer information in command complete with FIFO 223 * D2 Enable selection 224 * 08 Reselection 225 * 48 Disconnect command with FIFO 226 * 88 Terminate command with FIFO 227 * C8 Target command complete with FIFO 228 * 18 SCAM Arbitration/ Selection 229 * 5A Enable reselection 230 * 98 Select without ATN with FIFO 231 * B8 Select with ATN with FIFO 232 * D8 Message Accepted 233 * 58 NOP 234 */ 235 #define TRM_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */ 236 #define SEL_TIMEOUT 153 /* 250ms selection timeout (@ 40 MHz) */ 237 #define TRM_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */ 238 #define TRM_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */ 239 #define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */ 240 #define TCR0_SYNC_NEGO_DONE 0x4000 /* Sync nego done */ 241 #define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS sync */ 242 #define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE sync */ 243 #define TCR0_ENABLE_ALT 0x0800 /* Enable alternate sync */ 244 #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */ 245 #define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */ 246 #define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */ 247 #define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */ 248 #define TCR0_OFFSET_MASK 0x001F /* Offset number */ 249 #define TRM_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */ 250 #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */ 251 #define NON_TAG_BUSY 0x0080 /* Non tag command active */ 252 #define ACTTAG_MASK 0x007F /* Active tags */ 253 /* 254 ********************************************************************** 255 * 256 * The DMA register offset for TRM_S1040 257 * 258 ********************************************************************** 259 */ 260 #define TRM_DMA_COMMAND 0xA0 /* DMA Command (R/W) */ 261 #define SGXFER 0x02 /* Scatter/Gather transfer */ 262 #define XFERDATAIN 0x01 /* Transfer data in */ 263 #define XFERDATAOUT 0x00 /* Transfer data out */ 264 #define TRM_DMA_CONTROL 0xA1 /* DMA Control (W) */ 265 #define STOPDMAXFER 0x08 /* Stop DMA transfer */ 266 #define ABORTXFER 0x04 /* Abort DMA transfer */ 267 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */ 268 #define STARTDMAXFER 0x01 /* Start DMA transfer */ 269 #define TRM_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */ 270 #define DMA_FIFOCNT_MASK 0xFF /* Data FIFO Count */ 271 #define TRM_DMA_FIFOSTATUS 0xA2 /* DMA FIFO Status (R) */ 272 #define DMA_FIFO_EMPTY 0x80 /* DMA FIFO Empty */ 273 #define DMA_FIFO_FULL 0x01 /* DMA FIFO Full */ 274 #define TRM_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */ 275 #define XFERPENDING 0x80 /* Transfer pending */ 276 #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ 277 #define SCSICOMP 0x01 /* SCSI complete interrupt */ 278 #define TRM_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */ 279 #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */ 280 #define TRM_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */ 281 #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */ 282 #define TRM_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W) */ 283 #define TRM_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */ 284 #define TRM_DMA_XLOWADDR 0xB0 /* DMA Xfer Physical Low Addr (R/W) */ 285 #define TRM_DMA_XHIGHADDR 0xB4 /* DMA Xfer Physical High Addr (R/W) */ 286 /* 287 ********************************************************************** 288 * 289 * The general register offset for TRM_S1040 290 * 291 ********************************************************************** 292 */ 293 #define TRM_GEN_CONTROL 0xD4 /* Global Control (R/W) */ 294 #define EN_LED 0x80 /* Enable Control onboard LED */ 295 #define EN_EEPROM 0x10 /* Enable EEPROM programming */ 296 #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */ 297 #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */ 298 #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */ 299 #define TRM_GEN_STATUS 0xD5 /* Global Status (R) */ 300 #define GTIMEOUT 0x80 /* Global timer reach 0 */ 301 #define CON5068 0x10 /* External 50/68 pin connected */ 302 #define CON68 0x08 /* Internal 68 pin connected */ 303 #define CON50 0x04 /* Internal 50 pin connected */ 304 #define WIDESCSI 0x02 /* Wide SCSI card */ 305 #define TRM_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port (R/W) */ 306 #define NVR_BITOUT 0x08 /* Serial data out */ 307 #define NVR_BITIN 0x04 /* Serial data in */ 308 #define NVR_CLOCK 0x02 /* Serial clock */ 309 #define NVR_SELECT 0x01 /* Serial select */ 310 #define TRM_GEN_EDATA 0xD7 /* Parallel EEPROM data port (R/W) */ 311 #define TRM_GEN_EADDRESS 0xD8 /* Parallel EEPROM address (R/W) */ 312 #define TRM_GEN_TIMER 0xDB /* Global timer (R/W) */ 313
Indexes created Sun Sep 21 16:09:51 GMT 2025