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      1 /* $NetBSD: pcihost_fdtvar.h,v 1.1 2026/09/20 11:00:34 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <machine/pci_machdep.h>
     30 
     31 /* Physical address format bit definitions */
     32 #define	PHYS_HI_RELO			__BIT(31)
     33 #define	PHYS_HI_PREFETCH		__BIT(30)
     34 #define	PHYS_HI_ALIASED			__BIT(29)
     35 #define	PHYS_HI_SPACE			__BITS(25,24)
     36 #define	 PHYS_HI_SPACE_CFG		0
     37 #define	 PHYS_HI_SPACE_IO		1
     38 #define	 PHYS_HI_SPACE_MEM32		2
     39 #define	 PHYS_HI_SPACE_MEM64		3
     40 #define	PHYS_HI_BUS			__BITS(23,16)
     41 #define	PHYS_HI_DEVICE			__BITS(15,11)
     42 #define	PHYS_HI_FUNCTION		__BITS(10,8)
     43 #define	PHYS_HI_REGISTER		__BITS(7,0)
     44 
     45 extern int pcihost_segment;
     46 
     47 enum pcihost_type {
     48 	PCIHOST_CAM = 1,
     49 	PCIHOST_ECAM,
     50 };
     51 
     52 struct pcihost_msi_handlers;
     53 
     54 struct pcih_bus_space {
     55 	struct bus_space	bst;
     56 
     57 	int		(*map)(void *, bus_addr_t, bus_size_t,
     58 			      int, bus_space_handle_t *);
     59 	int			flags;
     60 
     61 	struct space_range {
     62 		bus_addr_t	bpci;
     63 		bus_addr_t	bbus;
     64 		bus_size_t	size;
     65 	}			ranges[4];
     66 	size_t			nranges;
     67 };
     68 
     69 struct pcihost_softc {
     70 	device_t		sc_dev;
     71 	bus_dma_tag_t		sc_dmat;
     72 	bus_space_tag_t		sc_bst;
     73 	bus_space_handle_t	sc_bsh;
     74 	bus_space_tag_t		sc_pci_bst;
     75 	int			sc_phandle;
     76 
     77 	enum pcihost_type	sc_type;
     78 
     79 	u_int			sc_seg;
     80 	u_int			sc_bus_min;
     81 	u_int			sc_bus_max;
     82 
     83 	struct md_pci_chipset	sc_pc;
     84 
     85 	struct pcih_bus_space	sc_io;
     86 	struct pcih_bus_space	sc_mem;
     87 
     88 	int			sc_pci_flags;
     89 
     90 	const u_int		*sc_pci_ranges;
     91 	u_int			sc_pci_ranges_cells;
     92 
     93 #ifdef __HAVE_PCI_MSI_MSIX
     94 	kmutex_t 		sc_msi_handlers_mutex;
     95 	LIST_HEAD(, pcihost_msi_handler)
     96 				sc_msi_handlers;
     97 #endif
     98 };
     99 
    100 void	pcihost_init2(struct pcihost_softc *);
    101 void	pcihost_init(pci_chipset_tag_t, void *);
    102