1 /* $NetBSD: algor_p5064reg.h,v 1.3 2008/04/28 20:23:10 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Memory map and register definitions for the Algorithmics P-5064. 34 */ 35 36 #define P5064_MEMORY 0x00000000UL /* onboard DRAM memory */ 37 /* 256 MB */ 38 #define P5064_ISAMEM 0x10000000UL /* ISA window of PCI memory */ 39 /* 8MB */ 40 #define P5064_PCIMEM 0x11000000UL /* PCI memory window */ 41 /* 112MB */ 42 #define P5064_PCIIO 0x1d000000UL /* PCI I/O window */ 43 /* 16MB */ 44 #define P5064_PCICFG 0x1ee00000UL /* PCI config space */ 45 /* 1MB */ 46 #define P5064_V360EPC 0x1ef00000UL /* V360EPC PCI controller */ 47 /* 64KB */ 48 #define P5064_CFGBOOT_W 0x1f800000UL /* configured bootstrap (W) */ 49 /* 512KB */ 50 #define P5064_SOCKET_W 0x1f900000UL /* socket EPROM (W) */ 51 /* 512KB */ 52 #define P5064_FLASH_W 0x1fa00000UL /* flash (W) */ 53 /* 1MB */ 54 #define P5064_CFBOOT 0x1fc00000UL /* configured bootstrap */ 55 /* 512KB */ 56 #define P5064_SOCKET 0x1fd00000UL /* socket EPROM */ 57 /* 512KB */ 58 #define P5064_FLASH 0x1fe00000UL /* flash */ 59 /* 1MB */ 60 #define P5064_LED0 0x1ff00000UL /* LED (1reg) */ 61 #define P5064_LED1 0x1ff20010UL /* LED (4reg) */ 62 #define P5064_LCD 0x1ff30000UL /* LCD display */ 63 #define P5064_Z80GPIO 0x1ff40000UL /* Z80 GPIO (rev B only) */ 64 #define P5064_Z80GPIO_IACK 0x1ff50000UL /* intr. ack. for Z80 */ 65 #define P5064_DBG_UART 0x1ff60000UL /* UART on debug board */ 66 #define P5064_LOCINT 0x1ff90000UL /* local interrupts */ 67 #define P5064_PANIC 0x1ff90004UL /* panic interrupts */ 68 #define P5064_PCIINT 0x1ff90008UL /* PCI interrupts */ 69 #define P5064_ISAINT 0x1ff9000cUL /* ISA interrupts */ 70 #define P5064_XBAR0 0x1ff90010UL /* Int. xbar 0 */ 71 #define P5064_XBAR1 0x1ff90014UL /* Int. xbar 1 */ 72 #define P5064_XBAR2 0x1ff90018UL /* Int. xbar 2 */ 73 #define P5064_XBAR3 0x1ff9001cUL /* Int. xbar 3 */ 74 #define P5064_XBAR4 0x1ff90020UL /* Int. xbar 4 */ 75 #define P5064_KBDINT 0x1ff90024UL /* keyboard interrupts */ 76 #define P5064_LOGICREV 0x1ff9003cUL /* logic revision */ 77 #define P5064_CFG0 0x1ffa0000UL /* board configuration 0 */ 78 #define P5064_CFG1 0x1ffb0000UL /* board configuration 1 */ 79 #define P5064_DRAMCFG 0x1ffc0000UL /* DRAM configuration */ 80 #define P5064_BOARDREV 0x1ffd0000UL /* board revision */ 81 #define P5064_PCIMEM_HI 0x20000000UL /* PCI memory high window */ 82 /* 3.5GB */ 83 84 /* P5064_LOCINT */ 85 #define LOCINT_PCIBR 0x01 86 #define LOCINT_FLP 0x02 87 #define LOCINT_MKBD 0x04 88 #define LOCINT_COM1 0x08 89 #define LOCINT_COM2 0x10 90 #define LOCINT_CENT 0x20 91 #define LOCINT_RTC 0x80 92 93 /* P5064_PANIC */ 94 #define PANIC_DEBUG 0x01 95 #define PANIC_PFAIL 0x02 96 #define PANIC_BERR 0x04 97 #define PANIC_ISANMI 0x08 98 #define PANIC_IOPERR 0x10 99 #define PANIC_CENT 0x20 100 #define PANIC_EWAKE 0x40 101 #define PANIC_ECODERR 0x80 102 103 /* P5064_PCIINT */ 104 #define PCIINT_EMDINT 0x01 105 #define PCIINT_ETH 0x02 106 #define PCIINT_SCSI 0x04 107 #define PCIINT_USB 0x08 108 #define PCIINT_PCI0 0x10 109 #define PCIINT_PCI1 0x20 110 #define PCIINT_PCI2 0x40 111 #define PCIINT_PCI3 0x80 112 113 /* P5064_ISAINT */ 114 #define ISAINT_ISABR 0x01 115 #define ISAINT_IDE0 0x02 116 #define ISAINT_IDE1 0x04 117 118 /* P5064_KBDINT */ 119 #define KBDINT_KBD 0x01 120 #define KBDINT_MOUSE 0x02 121 122 /* 123 * The Algorithmics PMON initializes two DMA windows: 124 * 125 * THE MANUAL CLAIMS THIS: 126 * PCI 0080.0000 -> Phys 0080.0000 (8MB) 127 * 128 * THE PMON FIRMWARE DOES THIS: 129 * PCI 0080.0000 -> Phys 0000.0000 (8MB) 130 * 131 * PCI 8000.0000 -> Phys 0000.0000 (256MB) 132 */ 133 #define P5064_DMA_ISA_PCIBASE 0x00800000UL 134 #define P5064_DMA_ISA_PHYSBASE 0x00000000UL 135 #define P5064_DMA_ISA_SIZE (8 * 1024 * 1024) 136 137 #define P5064_DMA_PCI_PCIBASE 0x80000000UL 138 #define P5064_DMA_PCI_PHYSBASE 0x00000000UL 139 #define P5064_DMA_PCI_SIZE (256 * 1024 * 1024) 140
Indexes created Mon Sep 22 13:09:51 GMT 2025