1 /* $NetBSD: smu_helper.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef _SMU_HELPER_H_ 26 #define _SMU_HELPER_H_ 27 28 struct pp_atomctrl_voltage_table; 29 struct pp_hwmgr; 30 struct phm_ppt_v1_voltage_lookup_table; 31 struct Watermarks_t; 32 struct pp_wm_sets_with_clock_ranges_soc15; 33 34 uint8_t convert_to_vid(uint16_t vddc); 35 uint16_t convert_to_vddc(uint8_t vid); 36 37 struct watermark_row_generic_t { 38 uint16_t MinClock; 39 uint16_t MaxClock; 40 uint16_t MinUclk; 41 uint16_t MaxUclk; 42 43 uint8_t WmSetting; 44 uint8_t Padding[3]; 45 }; 46 47 struct watermarks { 48 struct watermark_row_generic_t WatermarkRow[2][4]; 49 uint32_t padding[7]; 50 }; 51 52 int phm_copy_clock_limits_array( 53 struct pp_hwmgr *hwmgr, 54 uint32_t **pptable_info_array, 55 const uint32_t *pptable_array, 56 uint32_t power_saving_clock_count); 57 58 int phm_copy_overdrive_settings_limits_array( 59 struct pp_hwmgr *hwmgr, 60 uint32_t **pptable_info_array, 61 const uint32_t *pptable_array, 62 uint32_t od_setting_count); 63 64 extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, 65 uint32_t index, 66 uint32_t value, uint32_t mask); 67 extern int phm_wait_for_indirect_register_unequal( 68 struct pp_hwmgr *hwmgr, 69 uint32_t indirect_port, uint32_t index, 70 uint32_t value, uint32_t mask); 71 72 73 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr); 74 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr); 75 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr); 76 77 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table); 78 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); 79 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); 80 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table); 81 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table); 82 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max); 83 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes); 84 extern int32_t phm_get_dpm_level_enable_mask_value(void *table); 85 extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table, 86 uint32_t voltage); 87 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage); 88 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci); 89 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level); 90 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, 91 uint16_t virtual_voltage_id, int32_t *sclk); 92 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); 93 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask); 94 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr); 95 96 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 97 uint32_t sclk, uint16_t id, uint16_t *voltage); 98 99 extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size); 100 101 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, 102 uint32_t value, uint32_t mask); 103 104 extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, 105 uint32_t indirect_port, 106 uint32_t index, 107 uint32_t value, 108 uint32_t mask); 109 110 int phm_irq_process(struct amdgpu_device *adev, 111 struct amdgpu_irq_src *source, 112 struct amdgpu_iv_entry *entry); 113 114 int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr); 115 116 void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size, 117 uint8_t *frev, uint8_t *crev); 118 119 int smu_get_voltage_dependency_table_ppt_v1( 120 const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table, 121 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table); 122 123 int smu_set_watermarks_for_clocks_ranges(void *wt_table, 124 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); 125 126 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 127 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK 128 129 #define PHM_SET_FIELD(origval, reg, field, fieldval) \ 130 (((origval) & ~PHM_FIELD_MASK(reg, field)) | \ 131 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field)))) 132 133 #define PHM_GET_FIELD(value, reg, field) \ 134 (((value) & PHM_FIELD_MASK(reg, field)) >> \ 135 PHM_FIELD_SHIFT(reg, field)) 136 137 138 /* Operations on named fields. */ 139 140 #define PHM_READ_FIELD(device, reg, field) \ 141 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) 142 143 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \ 144 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 145 reg, field) 146 147 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \ 148 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 149 reg, field) 150 151 #define PHM_WRITE_FIELD(device, reg, field, fieldval) \ 152 cgs_write_register(device, mm##reg, PHM_SET_FIELD( \ 153 cgs_read_register(device, mm##reg), reg, field, fieldval)) 154 155 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \ 156 cgs_write_ind_register(device, port, ix##reg, \ 157 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 158 reg, field, fieldval)) 159 160 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ 161 cgs_write_ind_register(device, port, ix##reg, \ 162 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 163 reg, field, fieldval)) 164 165 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \ 166 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask) 167 168 169 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ 170 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) 171 172 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ 173 PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ 174 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) 175 176 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \ 177 phm_wait_for_indirect_register_unequal(hwmgr, \ 178 mm##port##_INDEX, index, value, mask) 179 180 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ 181 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) 182 183 #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ 184 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ 185 (fieldval) << PHM_FIELD_SHIFT(reg, field), \ 186 PHM_FIELD_MASK(reg, field) ) 187 188 189 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ 190 port, index, value, mask) \ 191 phm_wait_for_indirect_register_unequal(hwmgr, \ 192 mm##port##_INDEX_11, index, value, mask) 193 194 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ 195 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) 196 197 #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ 198 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ 199 (fieldval) << PHM_FIELD_SHIFT(reg, field), \ 200 PHM_FIELD_MASK(reg, field)) 201 202 203 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \ 204 port, index, value, mask) \ 205 phm_wait_on_indirect_register(hwmgr, \ 206 mm##port##_INDEX_11, index, value, mask) 207 208 #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ 209 PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) 210 211 #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ 212 PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \ 213 (fieldval) << PHM_FIELD_SHIFT(reg, field), \ 214 PHM_FIELD_MASK(reg, field)) 215 216 #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ 217 index, value, mask) \ 218 phm_wait_for_register_unequal(hwmgr, \ 219 index, value, mask) 220 221 #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ 222 PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ 223 mm##reg, value, mask) 224 225 #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \ 226 PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \ 227 (fieldval) << PHM_FIELD_SHIFT(reg, field), \ 228 PHM_FIELD_MASK(reg, field)) 229 230 #endif /* _SMU_HELPER_H_ */ 231
Indexes created Sat Sep 27 22:09:54 GMT 2025