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    Searched defs:PHY_WRITE (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/arch/arm/amlogic/
mesongxl_usb2phy.c 68 #define PHY_WRITE(sc, reg, val) \
98 PHY_WRITE(sc, USB2PHY_REG0, val);
105 PHY_WRITE(sc, USB2PHY_REG0, val);
110 PHY_WRITE(sc, USB2PHY_REG0, val);
114 PHY_WRITE(sc, USB2PHY_REG0, val);
125 PHY_WRITE(sc, USB2PHY_REG0, val);
mesongxl_usb3phy.c 75 #define PHY_WRITE(sc, reg, val) \
108 PHY_WRITE(sc, USB3PHY_REG5, val);
113 PHY_WRITE(sc, USB3PHY_REG0, val);
117 PHY_WRITE(sc, USB3PHY_REG4, val);
123 PHY_WRITE(sc, USB3PHY_REG5, val);
143 PHY_WRITE(sc, USB3PHY_REG1, val);
meson_usbphy.c 82 #define PHY_WRITE(sc, reg, val) \
142 PHY_WRITE(sc, PREI_USB_PHY_CFG_REG, val);
149 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val);
155 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val);
166 PHY_WRITE(sc, PREI_USB_PHY_ADP_BC_REG, val);
  /src/sys/arch/arm/nxp/
imx8mq_usbphy.c 72 #define PHY_WRITE(sc, reg, val) \
118 PHY_WRITE(sc, PHY_CTL1_ADDR, val);
122 PHY_WRITE(sc, PHY_CTL0_ADDR, val);
126 PHY_WRITE(sc, PHY_CTL2_ADDR, val);
131 PHY_WRITE(sc, PHY_CTL1_ADDR, val);
  /src/sys/arch/arm/sunxi/
sun9i_a80_usbphy.c 76 #define PHY_WRITE(sc, reg, val) \
125 PHY_WRITE(sc, PMU_CFG, val);
129 PHY_WRITE(sc, PMU_CFG, val);
sunxi_usb3phy.c 93 #define PHY_WRITE(phy, reg, val) \
123 PHY_WRITE(phy, SUNXI_PHY_EXTERNAL_CONTROL, val);
127 PHY_WRITE(phy, SUNXI_PIPE_CLOCK_CONTROL, val);
131 PHY_WRITE(phy, SUNXI_APP, val);
133 PHY_WRITE(phy, SUNXI_PHY_TUNE_LOW, PTL_MAGIC);
144 PHY_WRITE(phy, SUNXI_PHY_TUNE_HIGH, val);
sunxi_hdmiphy.c 144 #define PHY_WRITE(sc, reg, val) \
151 PHY_WRITE((sc), (reg), _tval); \
208 PHY_WRITE(sc, ANA_CFG1, 0);
314 PHY_WRITE(sc, ANA_CFG1, ANA_CFG1_LDOEN | ANA_CFG1_ENVBS | ANA_CFG1_ENBI);
315 PHY_WRITE(sc, PLL_CFG1, 0);
332 PHY_WRITE(sc, PLL_CFG1, inittab->pll_cfg1 & ~PLL_CFG1_CKIN_SEL);
333 PHY_WRITE(sc, PLL_CFG2, (inittab->pll_cfg2 & ~PLL_CFG2_PREDIV) | prediv);
335 PHY_WRITE(sc, PLL_CFG3, inittab->pll_cfg3);
355 PHY_WRITE(sc, ANA_CFG1, inittab->ana_cfg1);
356 PHY_WRITE(sc, ANA_CFG2, inittab->ana_cfg2 | rcalib)
    [all...]
  /src/sys/arch/arm/samsung/
exynos_usbphy.c 101 #define PHY_WRITE(sc, reg, val) \
174 PHY_WRITE(sc, USB_PHY_HOST_CTRL0, val);
180 PHY_WRITE(sc, USB_PHY_HOST_CTRL0, val);
196 PHY_WRITE(sc, reg, val);
201 PHY_WRITE(sc, reg, val);
215 PHY_WRITE(sc, USB_PHY_HOST_EHCICTRL, val);
exynos_usbdrdphy.c 120 #define PHY_WRITE(sc, reg, val) \
176 PHY_WRITE(sc, PHY_REG0, 0);
182 PHY_WRITE(sc, PHY_PARAM0, val);
184 PHY_WRITE(sc, PHY_RESUME, 0);
190 PHY_WRITE(sc, PHY_LINK_SYSTEM, val);
195 PHY_WRITE(sc, PHY_PARAM1, val);
199 PHY_WRITE(sc, PHY_BATCHG, val);
204 PHY_WRITE(sc, PHY_TEST, val);
206 PHY_WRITE(sc, PHY_UTMI, PHY_UTMI_OTGDISABLE);
217 PHY_WRITE(sc, PHY_CLK_RST, val)
    [all...]
  /src/sys/dev/mii/
miivar.h 247 #define PHY_WRITE(p, r, v) \
265 if ((rv = PHY_WRITE(sc, MII_MMDACR, (daddr & ~MMDACR_FUNCMASK))) != 0)
269 if ((rv = PHY_WRITE(sc, MII_MMDAADR, regnum)) != 0)
273 rv = PHY_WRITE(sc, MII_MMDACR, daddr);
299 return PHY_WRITE(sc, MII_MMDAADR, val);
  /src/sys/dev/ic/
bwivar.h 844 #define PHY_WRITE(mac, ctrl, val) bwi_phy_write((mac), (ctrl), (val))
848 PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) | (bits))
850 PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) & ~(bits))
852 PHY_WRITE((mac), (ctrl), (PHY_READ((mac), (ctrl)) & (filt)) | (bits))

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