1 /* $Id: at91rm9200reg.h,v 1.4 2021/09/17 08:13:06 andvar Exp $ */ 2 /* $NetBSD: at91rm9200reg.h,v 1.4 2021/09/17 08:13:06 andvar Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Embedtronics Oy 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _AT91RM9200REG_H_ 31 #define _AT91RM9200REG_H_ 32 33 #include <arm/at91/at91reg.h> 34 35 /* 36 * Physical memory map for the AT91RM9200 37 */ 38 39 /* 40 * ffff ffff --------------------------- 41 * System Peripherals 42 * fffe 4000 --------------------------- 43 * User Peripherals 44 * fffa 0000 --------------------------- 45 * (not used) 46 * 9000 0000 --------------------------- 47 * EBI Chip Select 7 48 * 8000 0000 --------------------------- 49 * EBI Chip Select 6 / CF logic 50 * 7000 0000 --------------------------- 51 * EBI Chip Select 5 / CF logic 52 * 6000 0000 --------------------------- 53 * EBI Chip Select 4 / CF logic 54 * 5000 0000 --------------------------- 55 * EBI Chip Select 3 / NANDFlash 56 * 4000 0000 --------------------------- 57 * EBI Chip Select 2 58 * 3000 0000 --------------------------- 59 * EBI Chip Select 1 / SDRAM 60 * 2000 0000 --------------------------- 61 * EBI Chip Select 0 / BFC 62 * 1000 0000 --------------------------- 63 * (not used) 64 * 0030 0000 --------------------------- 65 * USB HOST User Interface 66 * 0020 0000 --------------------------- 67 * SRAM 68 * 0010 0000 --------------------------- 69 * Boot memory 70 * 0000 0000 --------------------------- 71 */ 72 73 74 /* 75 * Virtual memory map for the AT91RM9200 integrated devices 76 * 77 * Some device registers are statically mapped on upper address region. 78 * because we have to access them before bus_space is initialized. 79 * Most devices are dynamically mapped by bus_space_map(). In this case, 80 * the actual mapped (virtual) address are not cared by device drivers. 81 */ 82 83 /* 84 * FFFF FFFF --------------------------- 85 * APB bus (1 MB) 86 * FFF0 0000 --------------------------- 87 * (not used) 88 * E000 0000 --------------------------- 89 * Kernel text and data 90 * C000 0000 --------------------------- 91 * (not used) 92 * 0000 0000 --------------------------- 93 * 94 */ 95 96 #define AT91RM9200_BOOTMEM_BASE 0x00000000U 97 #define AT91RM9200_BOOTMEM_SIZE 0x00100000U 98 99 #define AT91RM9200_ROM_BASE 0x00100000U 100 #define AT91RM9200_ROM_SIZE 0x00100000U 101 102 #define AT91RM9200_SRAM_BASE 0x00200000U 103 #define AT91RM9200_SRAM_SIZE 0x00004000U 104 105 #define AT91RM9200_UHP_BASE 0x00300000U 106 #define AT91RM9200_UHP_SIZE 0x00100000U 107 108 #define AT91RM9200_CS0_BASE 0x10000000U 109 #define AT91RM9200_CS0_SIZE 0x10000000U 110 111 #define AT91RM9200_CS1_BASE 0x20000000U 112 #define AT91RM9200_CS1_SIZE 0x10000000U 113 114 #define AT91RM9200_SDRAM_BASE AT91RM9200_CS1_BASE 115 116 #define AT91RM9200_CS2_BASE 0x30000000U 117 #define AT91RM9200_CS2_SIZE 0x10000000U 118 119 #define AT91RM9200_CS3_BASE 0x40000000U 120 #define AT91RM9200_CS3_SIZE 0x10000000U 121 122 #define AT91RM9200_CS4_BASE 0x50000000U 123 #define AT91RM9200_CS4_SIZE 0x10000000U 124 125 #define AT91RM9200_CS5_BASE 0x60000000U 126 #define AT91RM9200_CS5_SIZE 0x10000000U 127 128 #define AT91RM9200_CS6_BASE 0x70000000U 129 #define AT91RM9200_CS6_SIZE 0x10000000U 130 131 #define AT91RM9200_CS7_BASE 0x80000000U 132 #define AT91RM9200_CS7_SIZE 0x10000000U 133 134 /* Virtual address for I/O space */ 135 #define AT91RM9200_APB_VBASE 0xfff00000U 136 #define AT91RM9200_APB_HWBASE 0xfff00000U 137 #define AT91RM9200_APB_SIZE 0x00100000U 138 139 /* Peripherals: */ 140 #include <arm/at91/at91pdcreg.h> 141 142 #define AT91RM9200_TC0_BASE 0xFFFA0000U 143 #define AT91RM9200_TC1_BASE 0xFFFA0040U 144 #define AT91RM9200_TC2_BASE 0xFFFA0080U 145 #define AT91RM9200_TCB012_BASE 0xFFFA00C0U 146 #define AT91RM9200_TC3_BASE 0xFFFA4000U 147 #define AT91RM9200_TC4_BASE 0xFFFA4040U 148 #define AT91RM9200_TC5_BASE 0xFFFA4080U 149 #define AT91RM9200_TCB345_BASE 0xFFFA40C0U 150 #define AT91RM9200_TC_SIZE 0x4000U 151 //#include <arm/at91/at91tcreg.h> 152 153 #define AT91RM9200_UDP_BASE 0xFFF80000U 154 #define AT91RM9200_UDP_SIZE 0x4000U 155 //#include <arm/at91/at91udpreg.h> 156 157 #define AT91RM9200_MCI_BASE 0xFFFB4000U 158 #define AT91RM9200_TWI_BASE 0xFFFB8000U 159 #include <arm/at91/at91twireg.h> 160 161 #define AT91RM9200_EMAC_BASE 0xFFFBC000U 162 #define AT91RM9200_EMAC_SIZE 0x4000U 163 #include <arm/at91/at91emacreg.h> 164 165 #define AT91RM9200_USART0_BASE 0xFFFC0000U 166 #define AT91RM9200_USART1_BASE 0xFFFC4000U 167 #define AT91RM9200_USART2_BASE 0xFFFC8000U 168 #define AT91RM9200_USART3_BASE 0xFFFCC000U 169 #define AT91RM9200_USART_SIZE 0x4000U 170 #include <arm/at91/at91usartreg.h> 171 172 #define AT91RM9200_SSC0_BASE 0xFFFD0000U 173 #define AT91RM9200_SSC1_BASE 0xFFFD4000U 174 #define AT91RM9200_SSC2_BASE 0xFFFD8000U 175 #define AT91RM9200_SSC_SIZE 0x4000U 176 //#include <arm/at91/at91sscreg.h> 177 178 #define AT91RM9200_SPI_BASE 0xFFFE0000U 179 #define AT91RM9200_SPI_SIZE 0x4000U 180 #include <arm/at91/at91spireg.h> 181 182 #define AT91RM9200_AIC_BASE 0xFFFFF000U 183 #define AT91RM9200_AIC_SIZE 0x200U 184 #include <arm/at91/at91aicreg.h> 185 186 #define AT91RM9200_DBGU_BASE 0xFFFFF200U 187 #define AT91RM9200_DBGU_SIZE 0x200U 188 #include <arm/at91/at91dbgureg.h> 189 190 #define AT91RM9200_PIOA_BASE 0xFFFFF400U 191 #define AT91RM9200_PIOB_BASE 0xFFFFF600U 192 #define AT91RM9200_PIOC_BASE 0xFFFFF800U 193 #define AT91RM9200_PIOD_BASE 0xFFFFFA00U 194 #define AT91RM9200_PIO_SIZE 0x200U 195 #define AT91_PIO_SIZE AT91RM9200_PIO_SIZE // for generic AT91 code 196 #include <arm/at91/at91pioreg.h> 197 198 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOA_BASE + (_reg))) 199 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOA_BASE + (_reg))) = (_val);} while (0) 200 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOB_BASE + (_reg))) 201 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOB_BASE + (_reg))) = (_val);} while (0) 202 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOC_BASE + (_reg))) 203 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOC_BASE + (_reg))) = (_val);} while (0) 204 #define PIOD_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOD_BASE + (_reg))) 205 #define PIOD_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOD_BASE + (_reg))) = (_val);} while (0) 206 207 208 #define AT91RM9200_PMC_BASE 0xFFFFFC00U 209 #define AT91RM9200_PMC_SIZE 0x100U 210 #include <arm/at91/at91pmcreg.h> 211 212 #define AT91RM9200_ST_BASE 0xFFFFFD00U 213 #define AT91RM9200_ST_SIZE 0x100U 214 #include <arm/at91/at91streg.h> 215 216 #define AT91RM9200_RTC_BASE 0xFFFFFE00U 217 #define AT91RM9200_RTC_SIZE 0x100U 218 //#include <arm/at91/at91rtcreg.h> 219 220 // peripheral identifiers: 221 /* peripheral identifiers: */ 222 enum { 223 PID_FIQ = 0, /* 0 */ 224 PID_SYSIRQ, /* 1 */ 225 PID_PIOA, /* 2 */ 226 PID_PIOB, /* 3 */ 227 PID_PIOC, /* 4 */ 228 PID_PIOD, /* 5 */ 229 PID_US0, /* 6 */ 230 PID_US1, /* 7 */ 231 PID_US2, /* 8 */ 232 PID_US3, /* 9 */ 233 PID_MCI, /* 10 */ 234 PID_UDP, /* 11 */ 235 PID_TWI, /* 12 */ 236 PID_SPI, /* 13 */ 237 PID_SSC0, /* 14 */ 238 PID_SSC1, /* 15 */ 239 PID_SSC2, /* 16 */ 240 PID_TC0, /* 17 */ 241 PID_TC1, /* 18 */ 242 PID_TC2, /* 19 */ 243 PID_TC3, /* 20 */ 244 PID_TC4, /* 21 */ 245 PID_TC5, /* 22 */ 246 PID_UHP, /* 23 */ 247 PID_EMAC, /* 24 */ 248 PID_IRQ0, /* 25 */ 249 PID_IRQ1, /* 26 */ 250 PID_IRQ2, /* 27 */ 251 PID_IRQ3, /* 28 */ 252 PID_IRQ4, /* 29 */ 253 PID_IRQ5, /* 30 */ 254 PID_IRQ6, /* 31 */ 255 }; 256 257 #endif /* _AT91RM9200REG_H_ */ 258
Indexes created Mon Sep 22 13:09:51 GMT 2025