1 /************************************************************************** 2 * 3 * Copyright 2007 VMware, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #ifndef PIPE_DEFINES_H 29 #define PIPE_DEFINES_H 30 31 #include "p_compiler.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /** 38 * Gallium error codes. 39 * 40 * - A zero value always means success. 41 * - A negative value always means failure. 42 * - The meaning of a positive value is function dependent. 43 */ 44 enum pipe_error 45 { 46 PIPE_OK = 0, 47 PIPE_ERROR = -1, /**< Generic error */ 48 PIPE_ERROR_BAD_INPUT = -2, 49 PIPE_ERROR_OUT_OF_MEMORY = -3, 50 PIPE_ERROR_RETRY = -4 51 /* TODO */ 52 }; 53 54 enum pipe_blendfactor { 55 PIPE_BLENDFACTOR_ONE = 1, 56 PIPE_BLENDFACTOR_SRC_COLOR, 57 PIPE_BLENDFACTOR_SRC_ALPHA, 58 PIPE_BLENDFACTOR_DST_ALPHA, 59 PIPE_BLENDFACTOR_DST_COLOR, 60 PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE, 61 PIPE_BLENDFACTOR_CONST_COLOR, 62 PIPE_BLENDFACTOR_CONST_ALPHA, 63 PIPE_BLENDFACTOR_SRC1_COLOR, 64 PIPE_BLENDFACTOR_SRC1_ALPHA, 65 66 PIPE_BLENDFACTOR_ZERO = 0x11, 67 PIPE_BLENDFACTOR_INV_SRC_COLOR, 68 PIPE_BLENDFACTOR_INV_SRC_ALPHA, 69 PIPE_BLENDFACTOR_INV_DST_ALPHA, 70 PIPE_BLENDFACTOR_INV_DST_COLOR, 71 72 PIPE_BLENDFACTOR_INV_CONST_COLOR = 0x17, 73 PIPE_BLENDFACTOR_INV_CONST_ALPHA, 74 PIPE_BLENDFACTOR_INV_SRC1_COLOR, 75 PIPE_BLENDFACTOR_INV_SRC1_ALPHA, 76 }; 77 78 enum pipe_blend_func { 79 PIPE_BLEND_ADD, 80 PIPE_BLEND_SUBTRACT, 81 PIPE_BLEND_REVERSE_SUBTRACT, 82 PIPE_BLEND_MIN, 83 PIPE_BLEND_MAX, 84 }; 85 86 enum pipe_logicop { 87 PIPE_LOGICOP_CLEAR, 88 PIPE_LOGICOP_NOR, 89 PIPE_LOGICOP_AND_INVERTED, 90 PIPE_LOGICOP_COPY_INVERTED, 91 PIPE_LOGICOP_AND_REVERSE, 92 PIPE_LOGICOP_INVERT, 93 PIPE_LOGICOP_XOR, 94 PIPE_LOGICOP_NAND, 95 PIPE_LOGICOP_AND, 96 PIPE_LOGICOP_EQUIV, 97 PIPE_LOGICOP_NOOP, 98 PIPE_LOGICOP_OR_INVERTED, 99 PIPE_LOGICOP_COPY, 100 PIPE_LOGICOP_OR_REVERSE, 101 PIPE_LOGICOP_OR, 102 PIPE_LOGICOP_SET, 103 }; 104 105 #define PIPE_MASK_R 0x1 106 #define PIPE_MASK_G 0x2 107 #define PIPE_MASK_B 0x4 108 #define PIPE_MASK_A 0x8 109 #define PIPE_MASK_RGBA 0xf 110 #define PIPE_MASK_Z 0x10 111 #define PIPE_MASK_S 0x20 112 #define PIPE_MASK_ZS 0x30 113 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS) 114 115 116 /** 117 * Inequality functions. Used for depth test, stencil compare, alpha 118 * test, shadow compare, etc. 119 */ 120 enum pipe_compare_func { 121 PIPE_FUNC_NEVER, 122 PIPE_FUNC_LESS, 123 PIPE_FUNC_EQUAL, 124 PIPE_FUNC_LEQUAL, 125 PIPE_FUNC_GREATER, 126 PIPE_FUNC_NOTEQUAL, 127 PIPE_FUNC_GEQUAL, 128 PIPE_FUNC_ALWAYS, 129 }; 130 131 /** Polygon fill mode */ 132 enum { 133 PIPE_POLYGON_MODE_FILL, 134 PIPE_POLYGON_MODE_LINE, 135 PIPE_POLYGON_MODE_POINT, 136 PIPE_POLYGON_MODE_FILL_RECTANGLE, 137 }; 138 139 /** Polygon face specification, eg for culling */ 140 #define PIPE_FACE_NONE 0 141 #define PIPE_FACE_FRONT 1 142 #define PIPE_FACE_BACK 2 143 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK) 144 145 /** Stencil ops */ 146 enum pipe_stencil_op { 147 PIPE_STENCIL_OP_KEEP, 148 PIPE_STENCIL_OP_ZERO, 149 PIPE_STENCIL_OP_REPLACE, 150 PIPE_STENCIL_OP_INCR, 151 PIPE_STENCIL_OP_DECR, 152 PIPE_STENCIL_OP_INCR_WRAP, 153 PIPE_STENCIL_OP_DECR_WRAP, 154 PIPE_STENCIL_OP_INVERT, 155 }; 156 157 /** Texture types. 158 * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D 159 */ 160 enum pipe_texture_target 161 { 162 PIPE_BUFFER, 163 PIPE_TEXTURE_1D, 164 PIPE_TEXTURE_2D, 165 PIPE_TEXTURE_3D, 166 PIPE_TEXTURE_CUBE, 167 PIPE_TEXTURE_RECT, 168 PIPE_TEXTURE_1D_ARRAY, 169 PIPE_TEXTURE_2D_ARRAY, 170 PIPE_TEXTURE_CUBE_ARRAY, 171 PIPE_MAX_TEXTURE_TYPES, 172 }; 173 174 enum pipe_tex_face { 175 PIPE_TEX_FACE_POS_X, 176 PIPE_TEX_FACE_NEG_X, 177 PIPE_TEX_FACE_POS_Y, 178 PIPE_TEX_FACE_NEG_Y, 179 PIPE_TEX_FACE_POS_Z, 180 PIPE_TEX_FACE_NEG_Z, 181 PIPE_TEX_FACE_MAX, 182 }; 183 184 enum pipe_tex_wrap { 185 PIPE_TEX_WRAP_REPEAT, 186 PIPE_TEX_WRAP_CLAMP, 187 PIPE_TEX_WRAP_CLAMP_TO_EDGE, 188 PIPE_TEX_WRAP_CLAMP_TO_BORDER, 189 PIPE_TEX_WRAP_MIRROR_REPEAT, 190 PIPE_TEX_WRAP_MIRROR_CLAMP, 191 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE, 192 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER, 193 }; 194 195 /** Between mipmaps, ie mipfilter */ 196 enum pipe_tex_mipfilter { 197 PIPE_TEX_MIPFILTER_NEAREST, 198 PIPE_TEX_MIPFILTER_LINEAR, 199 PIPE_TEX_MIPFILTER_NONE, 200 }; 201 202 /** Within a mipmap, ie min/mag filter */ 203 enum pipe_tex_filter { 204 PIPE_TEX_FILTER_NEAREST, 205 PIPE_TEX_FILTER_LINEAR, 206 }; 207 208 enum pipe_tex_compare { 209 PIPE_TEX_COMPARE_NONE, 210 PIPE_TEX_COMPARE_R_TO_TEXTURE, 211 }; 212 213 enum pipe_tex_reduction_mode { 214 PIPE_TEX_REDUCTION_WEIGHTED_AVERAGE, 215 PIPE_TEX_REDUCTION_MIN, 216 PIPE_TEX_REDUCTION_MAX, 217 }; 218 219 /** 220 * Clear buffer bits 221 */ 222 #define PIPE_CLEAR_DEPTH (1 << 0) 223 #define PIPE_CLEAR_STENCIL (1 << 1) 224 #define PIPE_CLEAR_COLOR0 (1 << 2) 225 #define PIPE_CLEAR_COLOR1 (1 << 3) 226 #define PIPE_CLEAR_COLOR2 (1 << 4) 227 #define PIPE_CLEAR_COLOR3 (1 << 5) 228 #define PIPE_CLEAR_COLOR4 (1 << 6) 229 #define PIPE_CLEAR_COLOR5 (1 << 7) 230 #define PIPE_CLEAR_COLOR6 (1 << 8) 231 #define PIPE_CLEAR_COLOR7 (1 << 9) 232 /** Combined flags */ 233 /** All color buffers currently bound */ 234 #define PIPE_CLEAR_COLOR (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \ 235 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \ 236 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \ 237 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7) 238 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL) 239 240 /** 241 * CPU access map flags 242 */ 243 enum pipe_map_flags 244 { 245 /** 246 * Resource contents read back (or accessed directly) at transfer 247 * create time. 248 */ 249 PIPE_MAP_READ = 1 << 0, 250 251 /** 252 * Resource contents will be written back at buffer/texture_unmap 253 * time (or modified as a result of being accessed directly). 254 */ 255 PIPE_MAP_WRITE = 1 << 1, 256 257 /** 258 * Read/modify/write 259 */ 260 PIPE_MAP_READ_WRITE = PIPE_MAP_READ | PIPE_MAP_WRITE, 261 262 /** 263 * The transfer should map the texture storage directly. The driver may 264 * return NULL if that isn't possible, and the gallium frontend needs to cope 265 * with that and use an alternative path without this flag. 266 * 267 * E.g. the gallium frontend could have a simpler path which maps textures and 268 * does read/modify/write cycles on them directly, and a more complicated 269 * path which uses minimal read and write transfers. 270 * 271 * This flag supresses implicit "DISCARD" for buffer_subdata. 272 */ 273 PIPE_MAP_DIRECTLY = 1 << 2, 274 275 /** 276 * Discards the memory within the mapped region. 277 * 278 * It should not be used with PIPE_MAP_READ. 279 * 280 * See also: 281 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag. 282 */ 283 PIPE_MAP_DISCARD_RANGE = 1 << 3, 284 285 /** 286 * Fail if the resource cannot be mapped immediately. 287 * 288 * See also: 289 * - Direct3D's D3DLOCK_DONOTWAIT flag. 290 * - Mesa's MESA_MAP_NOWAIT_BIT flag. 291 * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag. 292 */ 293 PIPE_MAP_DONTBLOCK = 1 << 4, 294 295 /** 296 * Do not attempt to synchronize pending operations on the resource when mapping. 297 * 298 * It should not be used with PIPE_MAP_READ. 299 * 300 * See also: 301 * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag. 302 * - Direct3D's D3DLOCK_NOOVERWRITE flag. 303 * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag. 304 */ 305 PIPE_MAP_UNSYNCHRONIZED = 1 << 5, 306 307 /** 308 * Written ranges will be notified later with 309 * pipe_context::transfer_flush_region. 310 * 311 * It should not be used with PIPE_MAP_READ. 312 * 313 * See also: 314 * - pipe_context::transfer_flush_region 315 * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag. 316 */ 317 PIPE_MAP_FLUSH_EXPLICIT = 1 << 6, 318 319 /** 320 * Discards all memory backing the resource. 321 * 322 * It should not be used with PIPE_MAP_READ. 323 * 324 * This is equivalent to: 325 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT 326 * - BufferData(NULL) on a GL buffer 327 * - Direct3D's D3DLOCK_DISCARD flag. 328 * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag. 329 * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag 330 * - D3D10's D3D10_MAP_WRITE_DISCARD flag. 331 */ 332 PIPE_MAP_DISCARD_WHOLE_RESOURCE = 1 << 7, 333 334 /** 335 * Allows the resource to be used for rendering while mapped. 336 * 337 * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating 338 * the resource. 339 * 340 * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER) 341 * must be called to ensure the device can see what the CPU has written. 342 */ 343 PIPE_MAP_PERSISTENT = 1 << 8, 344 345 /** 346 * If PERSISTENT is set, this ensures any writes done by the device are 347 * immediately visible to the CPU and vice versa. 348 * 349 * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating 350 * the resource. 351 */ 352 PIPE_MAP_COHERENT = 1 << 9, 353 354 /** 355 * Map a resource in a thread-safe manner, because the calling thread can 356 * be any thread. It can only be used if both WRITE and UNSYNCHRONIZED are 357 * set. 358 */ 359 PIPE_MAP_THREAD_SAFE = 1 << 10, 360 361 /** 362 * Map only the depth aspect of a resource 363 */ 364 PIPE_MAP_DEPTH_ONLY = 1 << 11, 365 366 /** 367 * Map only the stencil aspect of a resource 368 */ 369 PIPE_MAP_STENCIL_ONLY = 1 << 12, 370 371 /** 372 * Mapping will be used only once (never remapped). 373 */ 374 PIPE_MAP_ONCE = 1 << 13, 375 376 /** 377 * This and higher bits are reserved for private use by drivers. Drivers 378 * should use this as (PIPE_MAP_DRV_PRV << i). 379 */ 380 PIPE_MAP_DRV_PRV = 1 << 14, 381 }; 382 383 /** 384 * Flags for the flush function. 385 */ 386 enum pipe_flush_flags 387 { 388 PIPE_FLUSH_END_OF_FRAME = (1 << 0), 389 PIPE_FLUSH_DEFERRED = (1 << 1), 390 PIPE_FLUSH_FENCE_FD = (1 << 2), 391 PIPE_FLUSH_ASYNC = (1 << 3), 392 PIPE_FLUSH_HINT_FINISH = (1 << 4), 393 PIPE_FLUSH_TOP_OF_PIPE = (1 << 5), 394 PIPE_FLUSH_BOTTOM_OF_PIPE = (1 << 6), 395 }; 396 397 /** 398 * Flags for pipe_context::dump_debug_state. 399 */ 400 #define PIPE_DUMP_DEVICE_STATUS_REGISTERS (1 << 0) 401 402 /** 403 * Create a compute-only context. Use in pipe_screen::context_create. 404 * This disables draw, blit, and clear*, render_condition, and other graphics 405 * functions. Interop with other graphics contexts is still allowed. 406 * This allows scheduling jobs on a compute-only hardware command queue that 407 * can run in parallel with graphics without stalling it. 408 */ 409 #define PIPE_CONTEXT_COMPUTE_ONLY (1 << 0) 410 411 /** 412 * Gather debug information and expect that pipe_context::dump_debug_state 413 * will be called. Use in pipe_screen::context_create. 414 */ 415 #define PIPE_CONTEXT_DEBUG (1 << 1) 416 417 /** 418 * Whether out-of-bounds shader loads must return zero and out-of-bounds 419 * shader stores must be dropped. 420 */ 421 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2) 422 423 /** 424 * Prefer threaded pipe_context. It also implies that video codec functions 425 * will not be used. (they will be either no-ops or NULL when threading is 426 * enabled) 427 */ 428 #define PIPE_CONTEXT_PREFER_THREADED (1 << 3) 429 430 /** 431 * Create a high priority context. 432 */ 433 #define PIPE_CONTEXT_HIGH_PRIORITY (1 << 4) 434 435 /** 436 * Create a low priority context. 437 */ 438 #define PIPE_CONTEXT_LOW_PRIORITY (1 << 5) 439 440 /** Stop execution if the device is reset. */ 441 #define PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET (1 << 6) 442 443 /** 444 * Flags for pipe_context::memory_barrier. 445 */ 446 #define PIPE_BARRIER_MAPPED_BUFFER (1 << 0) 447 #define PIPE_BARRIER_SHADER_BUFFER (1 << 1) 448 #define PIPE_BARRIER_QUERY_BUFFER (1 << 2) 449 #define PIPE_BARRIER_VERTEX_BUFFER (1 << 3) 450 #define PIPE_BARRIER_INDEX_BUFFER (1 << 4) 451 #define PIPE_BARRIER_CONSTANT_BUFFER (1 << 5) 452 #define PIPE_BARRIER_INDIRECT_BUFFER (1 << 6) 453 #define PIPE_BARRIER_TEXTURE (1 << 7) 454 #define PIPE_BARRIER_IMAGE (1 << 8) 455 #define PIPE_BARRIER_FRAMEBUFFER (1 << 9) 456 #define PIPE_BARRIER_STREAMOUT_BUFFER (1 << 10) 457 #define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11) 458 #define PIPE_BARRIER_UPDATE_BUFFER (1 << 12) 459 #define PIPE_BARRIER_UPDATE_TEXTURE (1 << 13) 460 #define PIPE_BARRIER_ALL ((1 << 14) - 1) 461 462 #define PIPE_BARRIER_UPDATE \ 463 (PIPE_BARRIER_UPDATE_BUFFER | PIPE_BARRIER_UPDATE_TEXTURE) 464 465 /** 466 * Flags for pipe_context::texture_barrier. 467 */ 468 #define PIPE_TEXTURE_BARRIER_SAMPLER (1 << 0) 469 #define PIPE_TEXTURE_BARRIER_FRAMEBUFFER (1 << 1) 470 471 /** 472 * Resource binding flags -- gallium frontends must specify in advance all 473 * the ways a resource might be used. 474 */ 475 #define PIPE_BIND_DEPTH_STENCIL (1 << 0) /* create_surface */ 476 #define PIPE_BIND_RENDER_TARGET (1 << 1) /* create_surface */ 477 #define PIPE_BIND_BLENDABLE (1 << 2) /* create_surface */ 478 #define PIPE_BIND_SAMPLER_VIEW (1 << 3) /* create_sampler_view */ 479 #define PIPE_BIND_VERTEX_BUFFER (1 << 4) /* set_vertex_buffers */ 480 #define PIPE_BIND_INDEX_BUFFER (1 << 5) /* draw_elements */ 481 #define PIPE_BIND_CONSTANT_BUFFER (1 << 6) /* set_constant_buffer */ 482 #define PIPE_BIND_DISPLAY_TARGET (1 << 7) /* flush_front_buffer */ 483 /* gap */ 484 #define PIPE_BIND_STREAM_OUTPUT (1 << 10) /* set_stream_output_buffers */ 485 #define PIPE_BIND_CURSOR (1 << 11) /* mouse cursor */ 486 #define PIPE_BIND_CUSTOM (1 << 12) /* gallium frontend/winsys usages */ 487 #define PIPE_BIND_GLOBAL (1 << 13) /* set_global_binding */ 488 #define PIPE_BIND_SHADER_BUFFER (1 << 14) /* set_shader_buffers */ 489 #define PIPE_BIND_SHADER_IMAGE (1 << 15) /* set_shader_images */ 490 #define PIPE_BIND_COMPUTE_RESOURCE (1 << 16) /* set_compute_resources */ 491 #define PIPE_BIND_COMMAND_ARGS_BUFFER (1 << 17) /* pipe_draw_info.indirect */ 492 #define PIPE_BIND_QUERY_BUFFER (1 << 18) /* get_query_result_resource */ 493 494 /** 495 * The first two flags above were previously part of the amorphous 496 * TEXTURE_USAGE, most of which are now descriptions of the ways a 497 * particular texture can be bound to the gallium pipeline. The two flags 498 * below do not fit within that and probably need to be migrated to some 499 * other place. 500 * 501 * Scanout is used to ask for a texture suitable for actual scanout (hence 502 * the name), which implies extra layout constraints on some hardware. 503 * It may also have some special meaning regarding mouse cursor images. 504 * 505 * The shared flag is quite underspecified, but certainly isn't a 506 * binding flag - it seems more like a message to the winsys to create 507 * a shareable allocation. 508 * 509 * The third flag has been added to be able to force textures to be created 510 * in linear mode (no tiling). 511 */ 512 #define PIPE_BIND_SCANOUT (1 << 19) /* */ 513 #define PIPE_BIND_SHARED (1 << 20) /* get_texture_handle ??? */ 514 #define PIPE_BIND_LINEAR (1 << 21) 515 #define PIPE_BIND_PROTECTED (1 << 22) /* Resource will be protected/encrypted */ 516 #define PIPE_BIND_SAMPLER_REDUCTION_MINMAX (1 << 23) /* PIPE_CAP_SAMPLER_REDUCTION_MINMAX */ 517 518 519 /** 520 * Flags for the driver about resource behaviour: 521 */ 522 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0) 523 #define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1) 524 #define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2) 525 #define PIPE_RESOURCE_FLAG_SPARSE (1 << 3) 526 #define PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE (1 << 4) 527 #define PIPE_RESOURCE_FLAG_ENCRYPTED (1 << 5) 528 #define PIPE_RESOURCE_FLAG_DONT_OVER_ALLOCATE (1 << 6) 529 #define PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY (1 << 7) /* for small visible VRAM */ 530 #define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 8) /* driver/winsys private */ 531 #define PIPE_RESOURCE_FLAG_FRONTEND_PRIV (1 << 24) /* gallium frontend private */ 532 533 /** 534 * Hint about the expected lifecycle of a resource. 535 * Sorted according to GPU vs CPU access. 536 */ 537 enum pipe_resource_usage { 538 PIPE_USAGE_DEFAULT, /* fast GPU access */ 539 PIPE_USAGE_IMMUTABLE, /* fast GPU access, immutable */ 540 PIPE_USAGE_DYNAMIC, /* uploaded data is used multiple times */ 541 PIPE_USAGE_STREAM, /* uploaded data is used once */ 542 PIPE_USAGE_STAGING, /* fast CPU access */ 543 }; 544 545 /** 546 * Shaders 547 */ 548 enum pipe_shader_type { 549 PIPE_SHADER_VERTEX, 550 PIPE_SHADER_FRAGMENT, 551 PIPE_SHADER_GEOMETRY, 552 PIPE_SHADER_TESS_CTRL, 553 PIPE_SHADER_TESS_EVAL, 554 PIPE_SHADER_COMPUTE, 555 PIPE_SHADER_TYPES, 556 }; 557 558 /** 559 * Primitive types: 560 */ 561 enum pipe_prim_type { 562 PIPE_PRIM_POINTS, 563 PIPE_PRIM_LINES, 564 PIPE_PRIM_LINE_LOOP, 565 PIPE_PRIM_LINE_STRIP, 566 PIPE_PRIM_TRIANGLES, 567 PIPE_PRIM_TRIANGLE_STRIP, 568 PIPE_PRIM_TRIANGLE_FAN, 569 PIPE_PRIM_QUADS, 570 PIPE_PRIM_QUAD_STRIP, 571 PIPE_PRIM_POLYGON, 572 PIPE_PRIM_LINES_ADJACENCY, 573 PIPE_PRIM_LINE_STRIP_ADJACENCY, 574 PIPE_PRIM_TRIANGLES_ADJACENCY, 575 PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY, 576 PIPE_PRIM_PATCHES, 577 PIPE_PRIM_MAX, 578 } ENUM_PACKED; 579 580 /** 581 * Tessellator spacing types 582 */ 583 enum pipe_tess_spacing { 584 PIPE_TESS_SPACING_FRACTIONAL_ODD, 585 PIPE_TESS_SPACING_FRACTIONAL_EVEN, 586 PIPE_TESS_SPACING_EQUAL, 587 }; 588 589 /** 590 * Query object types 591 */ 592 enum pipe_query_type { 593 PIPE_QUERY_OCCLUSION_COUNTER, 594 PIPE_QUERY_OCCLUSION_PREDICATE, 595 PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE, 596 PIPE_QUERY_TIMESTAMP, 597 PIPE_QUERY_TIMESTAMP_DISJOINT, 598 PIPE_QUERY_TIME_ELAPSED, 599 PIPE_QUERY_PRIMITIVES_GENERATED, 600 PIPE_QUERY_PRIMITIVES_EMITTED, 601 PIPE_QUERY_SO_STATISTICS, 602 PIPE_QUERY_SO_OVERFLOW_PREDICATE, 603 PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE, 604 PIPE_QUERY_GPU_FINISHED, 605 PIPE_QUERY_PIPELINE_STATISTICS, 606 PIPE_QUERY_PIPELINE_STATISTICS_SINGLE, 607 PIPE_QUERY_TYPES, 608 /* start of driver queries, see pipe_screen::get_driver_query_info */ 609 PIPE_QUERY_DRIVER_SPECIFIC = 256, 610 }; 611 612 /** 613 * Index for PIPE_QUERY_PIPELINE_STATISTICS subqueries. 614 */ 615 enum pipe_statistics_query_index { 616 PIPE_STAT_QUERY_IA_VERTICES, 617 PIPE_STAT_QUERY_IA_PRIMITIVES, 618 PIPE_STAT_QUERY_VS_INVOCATIONS, 619 PIPE_STAT_QUERY_GS_INVOCATIONS, 620 PIPE_STAT_QUERY_GS_PRIMITIVES, 621 PIPE_STAT_QUERY_C_INVOCATIONS, 622 PIPE_STAT_QUERY_C_PRIMITIVES, 623 PIPE_STAT_QUERY_PS_INVOCATIONS, 624 PIPE_STAT_QUERY_HS_INVOCATIONS, 625 PIPE_STAT_QUERY_DS_INVOCATIONS, 626 PIPE_STAT_QUERY_CS_INVOCATIONS, 627 }; 628 629 /** 630 * Conditional rendering modes 631 */ 632 enum pipe_render_cond_flag { 633 PIPE_RENDER_COND_WAIT, 634 PIPE_RENDER_COND_NO_WAIT, 635 PIPE_RENDER_COND_BY_REGION_WAIT, 636 PIPE_RENDER_COND_BY_REGION_NO_WAIT, 637 }; 638 639 /** 640 * Point sprite coord modes 641 */ 642 enum pipe_sprite_coord_mode { 643 PIPE_SPRITE_COORD_UPPER_LEFT, 644 PIPE_SPRITE_COORD_LOWER_LEFT, 645 }; 646 647 /** 648 * Texture & format swizzles 649 */ 650 enum pipe_swizzle { 651 PIPE_SWIZZLE_X, 652 PIPE_SWIZZLE_Y, 653 PIPE_SWIZZLE_Z, 654 PIPE_SWIZZLE_W, 655 PIPE_SWIZZLE_0, 656 PIPE_SWIZZLE_1, 657 PIPE_SWIZZLE_NONE, 658 PIPE_SWIZZLE_MAX, /**< Number of enums counter (must be last) */ 659 }; 660 661 /** 662 * Viewport swizzles 663 */ 664 enum pipe_viewport_swizzle { 665 PIPE_VIEWPORT_SWIZZLE_POSITIVE_X, 666 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_X, 667 PIPE_VIEWPORT_SWIZZLE_POSITIVE_Y, 668 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_Y, 669 PIPE_VIEWPORT_SWIZZLE_POSITIVE_Z, 670 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_Z, 671 PIPE_VIEWPORT_SWIZZLE_POSITIVE_W, 672 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_W, 673 }; 674 675 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull 676 677 678 /** 679 * Device reset status. 680 */ 681 enum pipe_reset_status 682 { 683 PIPE_NO_RESET, 684 PIPE_GUILTY_CONTEXT_RESET, 685 PIPE_INNOCENT_CONTEXT_RESET, 686 PIPE_UNKNOWN_CONTEXT_RESET, 687 }; 688 689 690 /** 691 * Conservative rasterization modes. 692 */ 693 enum pipe_conservative_raster_mode 694 { 695 PIPE_CONSERVATIVE_RASTER_OFF, 696 697 /** 698 * The post-snap mode means the conservative rasterization occurs after 699 * the conversion from floating-point to fixed-point coordinates 700 * on the subpixel grid. 701 */ 702 PIPE_CONSERVATIVE_RASTER_POST_SNAP, 703 704 /** 705 * The pre-snap mode means the conservative rasterization occurs before 706 * the conversion from floating-point to fixed-point coordinates. 707 */ 708 PIPE_CONSERVATIVE_RASTER_PRE_SNAP, 709 }; 710 711 712 /** 713 * resource_get_handle flags. 714 */ 715 /* Requires pipe_context::flush_resource before external use. */ 716 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0) 717 /* Expected external use of the resource: */ 718 #define PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE (1 << 1) 719 #define PIPE_HANDLE_USAGE_SHADER_WRITE (1 << 2) 720 721 /** 722 * pipe_image_view access flags. 723 */ 724 #define PIPE_IMAGE_ACCESS_READ (1 << 0) 725 #define PIPE_IMAGE_ACCESS_WRITE (1 << 1) 726 #define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \ 727 PIPE_IMAGE_ACCESS_WRITE) 728 729 /** 730 * Implementation capabilities/limits which are queried through 731 * pipe_screen::get_param() 732 */ 733 enum pipe_cap 734 { 735 PIPE_CAP_GRAPHICS, 736 PIPE_CAP_NPOT_TEXTURES, 737 PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS, 738 PIPE_CAP_ANISOTROPIC_FILTER, 739 PIPE_CAP_POINT_SPRITE, 740 PIPE_CAP_MAX_RENDER_TARGETS, 741 PIPE_CAP_OCCLUSION_QUERY, 742 PIPE_CAP_QUERY_TIME_ELAPSED, 743 PIPE_CAP_TEXTURE_SHADOW_MAP, 744 PIPE_CAP_TEXTURE_SWIZZLE, 745 PIPE_CAP_MAX_TEXTURE_2D_SIZE, 746 PIPE_CAP_MAX_TEXTURE_3D_LEVELS, 747 PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS, 748 PIPE_CAP_TEXTURE_MIRROR_CLAMP, 749 PIPE_CAP_BLEND_EQUATION_SEPARATE, 750 PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS, 751 PIPE_CAP_PRIMITIVE_RESTART, 752 /** subset of PRIMITIVE_RESTART where the restart index is always the fixed 753 * maximum value for the index type 754 */ 755 PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX, 756 /** blend enables and write masks per rendertarget */ 757 PIPE_CAP_INDEP_BLEND_ENABLE, 758 /** different blend funcs per rendertarget */ 759 PIPE_CAP_INDEP_BLEND_FUNC, 760 PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS, 761 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT, 762 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT, 763 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER, 764 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER, 765 PIPE_CAP_DEPTH_CLIP_DISABLE, 766 PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE, 767 PIPE_CAP_DEPTH_CLAMP_ENABLE, 768 PIPE_CAP_SHADER_STENCIL_EXPORT, 769 PIPE_CAP_TGSI_INSTANCEID, 770 PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR, 771 PIPE_CAP_FRAGMENT_COLOR_CLAMPED, 772 PIPE_CAP_MIXED_COLORBUFFER_FORMATS, 773 PIPE_CAP_SEAMLESS_CUBE_MAP, 774 PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE, 775 PIPE_CAP_MIN_TEXEL_OFFSET, 776 PIPE_CAP_MAX_TEXEL_OFFSET, 777 PIPE_CAP_CONDITIONAL_RENDER, 778 PIPE_CAP_TEXTURE_BARRIER, 779 PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS, 780 PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS, 781 PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME, 782 PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS, 783 PIPE_CAP_VERTEX_COLOR_UNCLAMPED, 784 PIPE_CAP_VERTEX_COLOR_CLAMPED, 785 PIPE_CAP_GLSL_FEATURE_LEVEL, 786 PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY, 787 PIPE_CAP_ESSL_FEATURE_LEVEL, 788 PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION, 789 PIPE_CAP_USER_VERTEX_BUFFERS, 790 PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY, 791 PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY, 792 PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY, 793 PIPE_CAP_COMPUTE, 794 PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT, 795 PIPE_CAP_START_INSTANCE, 796 PIPE_CAP_QUERY_TIMESTAMP, 797 PIPE_CAP_TEXTURE_MULTISAMPLE, 798 PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT, 799 PIPE_CAP_CUBE_MAP_ARRAY, 800 PIPE_CAP_TEXTURE_BUFFER_OBJECTS, 801 PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT, 802 PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY, 803 PIPE_CAP_TGSI_TEXCOORD, 804 PIPE_CAP_TEXTURE_BUFFER_SAMPLER, 805 PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER, 806 PIPE_CAP_QUERY_PIPELINE_STATISTICS, 807 PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK, 808 PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE, 809 PIPE_CAP_MAX_VIEWPORTS, 810 PIPE_CAP_ENDIANNESS, 811 PIPE_CAP_MIXED_FRAMEBUFFER_SIZES, 812 PIPE_CAP_TGSI_VS_LAYER_VIEWPORT, 813 PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES, 814 PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS, 815 PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS, 816 PIPE_CAP_TEXTURE_GATHER_SM5, 817 PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT, 818 PIPE_CAP_FAKE_SW_MSAA, 819 PIPE_CAP_TEXTURE_QUERY_LOD, 820 PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET, 821 PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET, 822 PIPE_CAP_SAMPLE_SHADING, 823 PIPE_CAP_TEXTURE_GATHER_OFFSETS, 824 PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION, 825 PIPE_CAP_MAX_VERTEX_STREAMS, 826 PIPE_CAP_DRAW_INDIRECT, 827 PIPE_CAP_TGSI_FS_FINE_DERIVATIVE, 828 PIPE_CAP_VENDOR_ID, 829 PIPE_CAP_DEVICE_ID, 830 PIPE_CAP_ACCELERATED, 831 PIPE_CAP_VIDEO_MEMORY, 832 PIPE_CAP_UMA, 833 PIPE_CAP_CONDITIONAL_RENDER_INVERTED, 834 PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE, 835 PIPE_CAP_SAMPLER_VIEW_TARGET, 836 PIPE_CAP_CLIP_HALFZ, 837 PIPE_CAP_VERTEXID_NOBASE, 838 PIPE_CAP_POLYGON_OFFSET_CLAMP, 839 PIPE_CAP_MULTISAMPLE_Z_RESOLVE, 840 PIPE_CAP_RESOURCE_FROM_USER_MEMORY, 841 PIPE_CAP_RESOURCE_FROM_USER_MEMORY_COMPUTE_ONLY, 842 PIPE_CAP_DEVICE_RESET_STATUS_QUERY, 843 PIPE_CAP_MAX_SHADER_PATCH_VARYINGS, 844 PIPE_CAP_TEXTURE_FLOAT_LINEAR, 845 PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR, 846 PIPE_CAP_DEPTH_BOUNDS_TEST, 847 PIPE_CAP_TGSI_TXQS, 848 PIPE_CAP_FORCE_PERSAMPLE_INTERP, 849 PIPE_CAP_SHAREABLE_SHADERS, 850 PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS, 851 PIPE_CAP_CLEAR_TEXTURE, 852 PIPE_CAP_CLEAR_SCISSORED, 853 PIPE_CAP_DRAW_PARAMETERS, 854 PIPE_CAP_TGSI_PACK_HALF_FLOAT, 855 PIPE_CAP_MULTI_DRAW_INDIRECT, 856 PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS, 857 PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL, 858 PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL, 859 PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL, 860 PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT, 861 PIPE_CAP_INVALIDATE_BUFFER, 862 PIPE_CAP_GENERATE_MIPMAP, 863 PIPE_CAP_STRING_MARKER, 864 PIPE_CAP_SURFACE_REINTERPRET_BLOCKS, 865 PIPE_CAP_QUERY_BUFFER_OBJECT, 866 PIPE_CAP_QUERY_MEMORY_INFO, 867 PIPE_CAP_PCI_GROUP, 868 PIPE_CAP_PCI_BUS, 869 PIPE_CAP_PCI_DEVICE, 870 PIPE_CAP_PCI_FUNCTION, 871 PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT, 872 PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR, 873 PIPE_CAP_CULL_DISTANCE, 874 PIPE_CAP_TGSI_VOTE, 875 PIPE_CAP_MAX_WINDOW_RECTANGLES, 876 PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED, 877 PIPE_CAP_VIEWPORT_SUBPIXEL_BITS, 878 PIPE_CAP_RASTERIZER_SUBPIXEL_BITS, 879 PIPE_CAP_MIXED_COLOR_DEPTH_BITS, 880 PIPE_CAP_TGSI_ARRAY_COMPONENTS, 881 PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS, 882 PIPE_CAP_TGSI_CAN_READ_OUTPUTS, 883 PIPE_CAP_NATIVE_FENCE_FD, 884 PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY, 885 PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS, 886 PIPE_CAP_FBFETCH, 887 PIPE_CAP_TGSI_MUL_ZERO_WINS, 888 PIPE_CAP_DOUBLES, 889 PIPE_CAP_INT64, 890 PIPE_CAP_INT64_DIVMOD, 891 PIPE_CAP_TGSI_TEX_TXF_LZ, 892 PIPE_CAP_TGSI_CLOCK, 893 PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE, 894 PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE, 895 PIPE_CAP_TGSI_BALLOT, 896 PIPE_CAP_TGSI_TES_LAYER_VIEWPORT, 897 PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX, 898 PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION, 899 PIPE_CAP_POST_DEPTH_COVERAGE, 900 PIPE_CAP_BINDLESS_TEXTURE, 901 PIPE_CAP_NIR_SAMPLERS_AS_DEREF, 902 PIPE_CAP_QUERY_SO_OVERFLOW, 903 PIPE_CAP_MEMOBJ, 904 PIPE_CAP_LOAD_CONSTBUF, 905 PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS, 906 PIPE_CAP_TILE_RASTER_ORDER, 907 PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES, 908 PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS, 909 PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET, 910 PIPE_CAP_CONTEXT_PRIORITY_MASK, 911 PIPE_CAP_FENCE_SIGNAL, 912 PIPE_CAP_CONSTBUF0_FLAGS, 913 PIPE_CAP_PACKED_UNIFORMS, 914 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES, 915 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES, 916 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES, 917 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES, 918 PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS, 919 PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE, 920 PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE, 921 PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS, 922 PIPE_CAP_MAX_GS_INVOCATIONS, 923 PIPE_CAP_MAX_SHADER_BUFFER_SIZE, 924 PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE, 925 PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS, 926 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS, 927 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS, 928 PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET, 929 PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET, 930 PIPE_CAP_SURFACE_SAMPLE_COUNT, 931 PIPE_CAP_TGSI_ATOMFADD, 932 PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE, 933 PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND, 934 PIPE_CAP_DEST_SURFACE_SRGB_CONTROL, 935 PIPE_CAP_NIR_COMPACT_ARRAYS, 936 PIPE_CAP_MAX_VARYINGS, 937 PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK, 938 PIPE_CAP_COMPUTE_SHADER_DERIVATIVES, 939 PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS, 940 PIPE_CAP_IMAGE_LOAD_FORMATTED, 941 PIPE_CAP_THROTTLE, 942 PIPE_CAP_DMABUF, 943 PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA, 944 PIPE_CAP_FRAGMENT_SHADER_INTERLOCK, 945 PIPE_CAP_FBFETCH_COHERENT, 946 PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED, 947 PIPE_CAP_ATOMIC_FLOAT_MINMAX, 948 PIPE_CAP_TGSI_DIV, 949 PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD, 950 PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES, 951 PIPE_CAP_VERTEX_SHADER_SATURATE, 952 PIPE_CAP_TEXTURE_SHADOW_LOD, 953 PIPE_CAP_SHADER_SAMPLES_IDENTICAL, 954 PIPE_CAP_TGSI_ATOMINC_WRAP, 955 PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF, 956 PIPE_CAP_GL_SPIRV, 957 PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS, 958 PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION, 959 PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE, 960 PIPE_CAP_FLATSHADE, 961 PIPE_CAP_ALPHA_TEST, 962 PIPE_CAP_POINT_SIZE_FIXED, 963 PIPE_CAP_TWO_SIDED_COLOR, 964 PIPE_CAP_CLIP_PLANES, 965 PIPE_CAP_MAX_VERTEX_BUFFERS, 966 PIPE_CAP_OPENCL_INTEGER_FUNCTIONS, 967 PIPE_CAP_INTEGER_MULTIPLY_32X16, 968 /* Turn draw, dispatch, blit into NOOP */ 969 PIPE_CAP_FRONTEND_NOOP, 970 PIPE_CAP_NIR_IMAGES_AS_DEREF, 971 PIPE_CAP_PACKED_STREAM_OUTPUT, 972 PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED, 973 PIPE_CAP_PSIZ_CLAMPED, 974 PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE, 975 PIPE_CAP_VIEWPORT_SWIZZLE, 976 PIPE_CAP_SYSTEM_SVM, 977 PIPE_CAP_VIEWPORT_MASK, 978 PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL, 979 PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE, 980 PIPE_CAP_GLSL_ZERO_INIT, 981 PIPE_CAP_BLEND_EQUATION_ADVANCED, 982 PIPE_CAP_NIR_ATOMICS_AS_DEREF, 983 PIPE_CAP_NO_CLIP_ON_COPY_TEX, 984 PIPE_CAP_MAX_TEXTURE_MB, 985 PIPE_CAP_SHADER_ATOMIC_INT64, 986 PIPE_CAP_DEVICE_PROTECTED_CONTENT, 987 PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0, 988 PIPE_CAP_GL_CLAMP, 989 PIPE_CAP_TEXRECT, 990 PIPE_CAP_SAMPLER_REDUCTION_MINMAX, 991 PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB, 992 PIPE_CAP_ALLOW_DYNAMIC_VAO_FASTPATH, 993 PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART, 994 PIPE_CAP_SUPPORTED_PRIM_MODES, 995 PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART, 996 PIPE_CAP_PREFER_BACK_BUFFER_REUSE, 997 PIPE_CAP_DRAW_VERTEX_STATE, 998 999 PIPE_CAP_LAST, 1000 /* XXX do not add caps after PIPE_CAP_LAST! */ 1001 }; 1002 1003 /** 1004 * Possible bits for PIPE_CAP_CONTEXT_PRIORITY_MASK param, which should 1005 * return a bitmask of the supported priorities. If the driver does not 1006 * support prioritized contexts, it can return 0. 1007 * 1008 * Note that these match __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_* 1009 */ 1010 #define PIPE_CONTEXT_PRIORITY_LOW (1 << 0) 1011 #define PIPE_CONTEXT_PRIORITY_MEDIUM (1 << 1) 1012 #define PIPE_CONTEXT_PRIORITY_HIGH (1 << 2) 1013 1014 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0) 1015 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1) 1016 1017 enum pipe_endian 1018 { 1019 PIPE_ENDIAN_LITTLE = 0, 1020 PIPE_ENDIAN_BIG = 1, 1021 #if UTIL_ARCH_LITTLE_ENDIAN 1022 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE 1023 #elif UTIL_ARCH_BIG_ENDIAN 1024 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG 1025 #endif 1026 }; 1027 1028 /** 1029 * Implementation limits which are queried through 1030 * pipe_screen::get_paramf() 1031 */ 1032 enum pipe_capf 1033 { 1034 PIPE_CAPF_MAX_LINE_WIDTH, 1035 PIPE_CAPF_MAX_LINE_WIDTH_AA, 1036 PIPE_CAPF_MAX_POINT_WIDTH, 1037 PIPE_CAPF_MAX_POINT_WIDTH_AA, 1038 PIPE_CAPF_MAX_TEXTURE_ANISOTROPY, 1039 PIPE_CAPF_MAX_TEXTURE_LOD_BIAS, 1040 PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE, 1041 PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE, 1042 PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY, 1043 }; 1044 1045 /** Shader caps not specific to any single stage */ 1046 enum pipe_shader_cap 1047 { 1048 PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */ 1049 PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS, 1050 PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS, 1051 PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS, 1052 PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH, 1053 PIPE_SHADER_CAP_MAX_INPUTS, 1054 PIPE_SHADER_CAP_MAX_OUTPUTS, 1055 PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE, 1056 PIPE_SHADER_CAP_MAX_CONST_BUFFERS, 1057 PIPE_SHADER_CAP_MAX_TEMPS, 1058 /* boolean caps */ 1059 PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED, 1060 PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR, 1061 PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR, 1062 PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR, 1063 PIPE_SHADER_CAP_INDIRECT_CONST_ADDR, 1064 PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */ 1065 PIPE_SHADER_CAP_INTEGERS, 1066 PIPE_SHADER_CAP_INT64_ATOMICS, 1067 PIPE_SHADER_CAP_FP16, 1068 PIPE_SHADER_CAP_FP16_DERIVATIVES, 1069 PIPE_SHADER_CAP_FP16_CONST_BUFFERS, 1070 PIPE_SHADER_CAP_INT16, 1071 PIPE_SHADER_CAP_GLSL_16BIT_CONSTS, 1072 PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS, 1073 PIPE_SHADER_CAP_PREFERRED_IR, 1074 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED, 1075 PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS, 1076 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */ 1077 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED, 1078 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED, 1079 PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE, 1080 PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT, 1081 PIPE_SHADER_CAP_MAX_SHADER_BUFFERS, 1082 PIPE_SHADER_CAP_SUPPORTED_IRS, 1083 PIPE_SHADER_CAP_MAX_SHADER_IMAGES, 1084 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD, 1085 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS, 1086 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED, 1087 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS, 1088 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS, 1089 }; 1090 1091 /** 1092 * Shader intermediate representation. 1093 * 1094 * Note that if the driver requests something other than TGSI, it must 1095 * always be prepared to receive TGSI in addition to its preferred IR. 1096 * If the driver requests TGSI as its preferred IR, it will *always* 1097 * get TGSI. 1098 * 1099 * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with 1100 * gallium frontends that only understand TGSI. 1101 */ 1102 enum pipe_shader_ir 1103 { 1104 PIPE_SHADER_IR_TGSI = 0, 1105 PIPE_SHADER_IR_NATIVE, 1106 PIPE_SHADER_IR_NIR, 1107 PIPE_SHADER_IR_NIR_SERIALIZED, 1108 }; 1109 1110 /** 1111 * Compute-specific implementation capability. They can be queried 1112 * using pipe_screen::get_compute_param. 1113 */ 1114 enum pipe_compute_cap 1115 { 1116 PIPE_COMPUTE_CAP_ADDRESS_BITS, 1117 PIPE_COMPUTE_CAP_IR_TARGET, 1118 PIPE_COMPUTE_CAP_GRID_DIMENSION, 1119 PIPE_COMPUTE_CAP_MAX_GRID_SIZE, 1120 PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE, 1121 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, 1122 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, 1123 PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE, 1124 PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE, 1125 PIPE_COMPUTE_CAP_MAX_INPUT_SIZE, 1126 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, 1127 PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY, 1128 PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS, 1129 PIPE_COMPUTE_CAP_IMAGES_SUPPORTED, 1130 PIPE_COMPUTE_CAP_SUBGROUP_SIZE, 1131 PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK, 1132 }; 1133 1134 /** 1135 * Resource parameters. They can be queried using 1136 * pipe_screen::get_resource_param. 1137 */ 1138 enum pipe_resource_param 1139 { 1140 PIPE_RESOURCE_PARAM_NPLANES, 1141 PIPE_RESOURCE_PARAM_STRIDE, 1142 PIPE_RESOURCE_PARAM_OFFSET, 1143 PIPE_RESOURCE_PARAM_MODIFIER, 1144 PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED, 1145 PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS, 1146 PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD, 1147 PIPE_RESOURCE_PARAM_LAYER_STRIDE, 1148 }; 1149 1150 /** 1151 * Types of parameters for pipe_context::set_context_param. 1152 */ 1153 enum pipe_context_param 1154 { 1155 /* A hint for the driver that it should pin its execution threads to 1156 * a group of cores sharing a specific L3 cache if the CPU has multiple 1157 * L3 caches. This is needed for good multithreading performance on 1158 * AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have 1159 * any internal threads or don't run on affected CPUs can ignore this. 1160 */ 1161 PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE, 1162 }; 1163 1164 /** 1165 * Composite query types 1166 */ 1167 1168 /** 1169 * Query result for PIPE_QUERY_SO_STATISTICS. 1170 */ 1171 struct pipe_query_data_so_statistics 1172 { 1173 uint64_t num_primitives_written; 1174 uint64_t primitives_storage_needed; 1175 }; 1176 1177 /** 1178 * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT. 1179 */ 1180 struct pipe_query_data_timestamp_disjoint 1181 { 1182 uint64_t frequency; 1183 bool disjoint; 1184 }; 1185 1186 /** 1187 * Query result for PIPE_QUERY_PIPELINE_STATISTICS. 1188 */ 1189 struct pipe_query_data_pipeline_statistics 1190 { 1191 uint64_t ia_vertices; /**< Num vertices read by the vertex fetcher. */ 1192 uint64_t ia_primitives; /**< Num primitives read by the vertex fetcher. */ 1193 uint64_t vs_invocations; /**< Num vertex shader invocations. */ 1194 uint64_t gs_invocations; /**< Num geometry shader invocations. */ 1195 uint64_t gs_primitives; /**< Num primitives output by a geometry shader. */ 1196 uint64_t c_invocations; /**< Num primitives sent to the rasterizer. */ 1197 uint64_t c_primitives; /**< Num primitives that were rendered. */ 1198 uint64_t ps_invocations; /**< Num pixel shader invocations. */ 1199 uint64_t hs_invocations; /**< Num hull shader invocations. */ 1200 uint64_t ds_invocations; /**< Num domain shader invocations. */ 1201 uint64_t cs_invocations; /**< Num compute shader invocations. */ 1202 }; 1203 1204 /** 1205 * For batch queries. 1206 */ 1207 union pipe_numeric_type_union 1208 { 1209 uint64_t u64; 1210 uint32_t u32; 1211 float f; 1212 }; 1213 1214 /** 1215 * Query result (returned by pipe_context::get_query_result). 1216 */ 1217 union pipe_query_result 1218 { 1219 /* PIPE_QUERY_OCCLUSION_PREDICATE */ 1220 /* PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE */ 1221 /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */ 1222 /* PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE */ 1223 /* PIPE_QUERY_GPU_FINISHED */ 1224 bool b; 1225 1226 /* PIPE_QUERY_OCCLUSION_COUNTER */ 1227 /* PIPE_QUERY_TIMESTAMP */ 1228 /* PIPE_QUERY_TIME_ELAPSED */ 1229 /* PIPE_QUERY_PRIMITIVES_GENERATED */ 1230 /* PIPE_QUERY_PRIMITIVES_EMITTED */ 1231 /* PIPE_DRIVER_QUERY_TYPE_UINT64 */ 1232 /* PIPE_DRIVER_QUERY_TYPE_BYTES */ 1233 /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */ 1234 /* PIPE_DRIVER_QUERY_TYPE_HZ */ 1235 uint64_t u64; 1236 1237 /* PIPE_DRIVER_QUERY_TYPE_UINT */ 1238 uint32_t u32; 1239 1240 /* PIPE_DRIVER_QUERY_TYPE_FLOAT */ 1241 /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */ 1242 float f; 1243 1244 /* PIPE_QUERY_SO_STATISTICS */ 1245 struct pipe_query_data_so_statistics so_statistics; 1246 1247 /* PIPE_QUERY_TIMESTAMP_DISJOINT */ 1248 struct pipe_query_data_timestamp_disjoint timestamp_disjoint; 1249 1250 /* PIPE_QUERY_PIPELINE_STATISTICS */ 1251 struct pipe_query_data_pipeline_statistics pipeline_statistics; 1252 1253 /* batch queries (variable length) */ 1254 union pipe_numeric_type_union batch[1]; 1255 }; 1256 1257 enum pipe_query_value_type 1258 { 1259 PIPE_QUERY_TYPE_I32, 1260 PIPE_QUERY_TYPE_U32, 1261 PIPE_QUERY_TYPE_I64, 1262 PIPE_QUERY_TYPE_U64, 1263 }; 1264 1265 union pipe_color_union 1266 { 1267 float f[4]; 1268 int i[4]; 1269 unsigned int ui[4]; 1270 }; 1271 1272 enum pipe_driver_query_type 1273 { 1274 PIPE_DRIVER_QUERY_TYPE_UINT64, 1275 PIPE_DRIVER_QUERY_TYPE_UINT, 1276 PIPE_DRIVER_QUERY_TYPE_FLOAT, 1277 PIPE_DRIVER_QUERY_TYPE_PERCENTAGE, 1278 PIPE_DRIVER_QUERY_TYPE_BYTES, 1279 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS, 1280 PIPE_DRIVER_QUERY_TYPE_HZ, 1281 PIPE_DRIVER_QUERY_TYPE_DBM, 1282 PIPE_DRIVER_QUERY_TYPE_TEMPERATURE, 1283 PIPE_DRIVER_QUERY_TYPE_VOLTS, 1284 PIPE_DRIVER_QUERY_TYPE_AMPS, 1285 PIPE_DRIVER_QUERY_TYPE_WATTS, 1286 }; 1287 1288 /* Whether an average value per frame or a cumulative value should be 1289 * displayed. 1290 */ 1291 enum pipe_driver_query_result_type 1292 { 1293 PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 1294 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE, 1295 }; 1296 1297 /** 1298 * Some hardware requires some hardware-specific queries to be submitted 1299 * as batched queries. The corresponding query objects are created using 1300 * create_batch_query, and at most one such query may be active at 1301 * any time. 1302 */ 1303 #define PIPE_DRIVER_QUERY_FLAG_BATCH (1 << 0) 1304 1305 /* Do not list this query in the HUD. */ 1306 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1) 1307 1308 struct pipe_driver_query_info 1309 { 1310 const char *name; 1311 unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */ 1312 union pipe_numeric_type_union max_value; /* max value that can be returned */ 1313 enum pipe_driver_query_type type; 1314 enum pipe_driver_query_result_type result_type; 1315 unsigned group_id; 1316 unsigned flags; 1317 }; 1318 1319 struct pipe_driver_query_group_info 1320 { 1321 const char *name; 1322 unsigned max_active_queries; 1323 unsigned num_queries; 1324 }; 1325 1326 enum pipe_fd_type 1327 { 1328 PIPE_FD_TYPE_NATIVE_SYNC, 1329 PIPE_FD_TYPE_SYNCOBJ, 1330 }; 1331 1332 /** 1333 * counter type and counter data type enums used by INTEL_performance_query 1334 * APIs in gallium drivers. 1335 */ 1336 enum pipe_perf_counter_type 1337 { 1338 PIPE_PERF_COUNTER_TYPE_EVENT, 1339 PIPE_PERF_COUNTER_TYPE_DURATION_NORM, 1340 PIPE_PERF_COUNTER_TYPE_DURATION_RAW, 1341 PIPE_PERF_COUNTER_TYPE_THROUGHPUT, 1342 PIPE_PERF_COUNTER_TYPE_RAW, 1343 PIPE_PERF_COUNTER_TYPE_TIMESTAMP, 1344 }; 1345 1346 enum pipe_perf_counter_data_type 1347 { 1348 PIPE_PERF_COUNTER_DATA_TYPE_BOOL32, 1349 PIPE_PERF_COUNTER_DATA_TYPE_UINT32, 1350 PIPE_PERF_COUNTER_DATA_TYPE_UINT64, 1351 PIPE_PERF_COUNTER_DATA_TYPE_FLOAT, 1352 PIPE_PERF_COUNTER_DATA_TYPE_DOUBLE, 1353 }; 1354 1355 #define PIPE_UUID_SIZE 16 1356 1357 #ifdef PIPE_OS_UNIX 1358 #define PIPE_MEMORY_FD 1359 #endif 1360 1361 #ifdef __cplusplus 1362 } 1363 #endif 1364 1365 #endif 1366
Indexes created Wed Jul 22 00:25:13 UTC 2026