1 /* $NetBSD: plcomreg.h,v 1.9 2024/02/05 22:08:04 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #ifndef _SYS_ARCH_EVBARM_DEV_PLCOMREG_H_ 33 #define _SYS_ARCH_EVBARM_DEV_PLCOMREG_H_ 34 35 #define PLCOM_FREQ 1843200 /* 16-bit baud rate divisor */ 36 #define PLCOM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ 37 38 /* control register */ 39 #define PL011_CR_CTSEN 0x8000 /* CTS HW flow control enable */ 40 #define PL011_CR_RTSEN 0x4000 /* RTS HW flow control enable */ 41 #define PL011_CR_OUT2 0x2000 /* Complement of UART Out2 MSR */ 42 #define PL011_CR_OUT1 0x1000 /* Complement of UART Out1 MSR */ 43 #define PL011_CR_RTS 0x0800 /* Request to send */ 44 #define PL011_CR_DTR 0x0400 /* Data transmit Ready */ 45 #define PL011_CR_RXE 0x0200 /* Receive enable */ 46 #define PL011_CR_TXE 0x0100 /* Transmit enable */ 47 #define PL01X_CR_LBE 0x0080 /* Loopback enable */ 48 #define PL010_CR_RTIE 0x0040 /* Receive timeout interrupt enable */ 49 #define PL010_CR_TIE 0x0020 /* Transmit interrupt enable */ 50 #define PL010_CR_RIE 0x0010 /* Receive interrupt enable */ 51 #define PL010_CR_MSIE 0x0008 /* Modem status interrupt enable */ 52 #define PL01X_CR_SIRLP 0x0004 /* IrDA SIR Low power mode */ 53 #define PL01X_CR_SIREN 0x0002 /* SIR Enable */ 54 #define PL01X_CR_UARTEN 0x0001 /* Uart enable */ 55 56 /* interrupt identification register */ 57 #define PL010_IIR_RTIS 0x08 58 #define PL010_IIR_TIS 0x04 59 #define PL010_IIR_RIS 0x02 60 #define PL010_IIR_MIS 0x01 61 #define PL010_IIR_IMASK \ 62 (PL010_IIR_RTIS | PL010_IIR_TIS | PL010_IIR_RIS | PL010_IIR_MIS) 63 64 /* line control register */ 65 #define PL011_LCR_SPS 0x80 /* Stick parity select */ 66 #define PL01X_LCR_WLEN 0x60 /* Mask of size bits */ 67 #define PL01X_LCR_8BITS 0x60 /* 8 bits per serial word */ 68 #define PL01X_LCR_7BITS 0x40 /* 7 bits */ 69 #define PL01X_LCR_6BITS 0x20 /* 6 bits */ 70 #define PL01X_LCR_5BITS 0x00 /* 5 bits */ 71 #define PL01X_LCR_FEN 0x10 /* FIFO enable */ 72 #define PL01X_LCR_STP2 0x08 /* 2 stop bits per serial word */ 73 #define PL01X_LCR_EPS 0x04 /* Even parity select */ 74 #define PL01X_LCR_PEN 0x02 /* Parity enable */ 75 #define PL01X_LCR_PEVEN (PL01X_LCR_PEN | PL01X_LCR_EPS) 76 #define PL01X_LCR_PODD PL01X_LCR_PEN 77 #define PL01X_LCR_PNONE 0x00 /* No parity */ 78 #define PL01X_LCR_BRK 0x01 /* Break Control */ 79 80 /* modem control register */ 81 #define PL01X_MCR_RTS 0x02 /* Request To Send */ 82 #define PL01X_MCR_DTR 0x01 /* Data Terminal Ready */ 83 #define PL011_MCR(mcr) ((mcr) << 10) /* MCR to CR bit values for PL011 */ 84 85 /* receive status register */ 86 #define PL01X_RSR_OE 0x08 /* Overrun Error */ 87 #define PL01X_RSR_BE 0x04 /* Break */ 88 #define PL01X_RSR_PE 0x02 /* Parity Error */ 89 #define PL01X_RSR_FE 0x01 /* Framing Error */ 90 #define PL01X_RSR_ERROR \ 91 (PL01X_RSR_OE | PL01X_RSR_BE | PL01X_RSR_PE | PL01X_RSR_FE) 92 93 /* flag register */ 94 #define PL011_FR_RI 0x100 /* Ring Indicator */ 95 #define PL01X_FR_TXFE 0x080 /* Transmit fifo empty */ 96 #define PL01X_FR_RXFF 0x040 /* Receive fifo full */ 97 #define PL01X_FR_TXFF 0x020 /* Transmit fifo full */ 98 #define PL01X_FR_RXFE 0x010 /* Receive fifo empty */ 99 #define PL01X_FR_BUSY 0x008 /* Uart Busy */ 100 #define PL01X_FR_DCD 0x004 /* Data carrier detect */ 101 #define PL01X_FR_DSR 0x002 /* Data set ready */ 102 #define PL01X_FR_CTS 0x001 /* Clear to send */ 103 104 /* modem status register */ 105 /* All deltas are from the last read of the MSR. */ 106 #define PL01X_MSR_DCD PL01X_FR_DCD 107 #define PL01X_MSR_DSR PL01X_FR_DSR 108 #define PL01X_MSR_CTS PL01X_FR_CTS 109 #define PL011_MSR_RI PL011_FR_RI 110 111 /* ifls */ 112 #define PL011_IFLS_MASK 0x001f 113 #define PL011_IFLS_1EIGHTH 0 114 #define PL011_IFLS_1QUARTER 1 115 #define PL011_IFLS_1HALF 2 116 #define PL011_IFLS_3QUARTERS 3 117 #define PL011_IFLS_7EIGHTHS 4 118 #define PL011_IFLS_RXIFLS(x) (((x) & 0x7) << 3) 119 #define PL011_IFLS_TXIFLS(x) (((x) & 0x7) << 0) 120 121 /* All interrupt status/clear registers */ 122 #define PL011_INT_OE 0x400 123 #define PL011_INT_BE 0x200 124 #define PL011_INT_PE 0x100 125 #define PL011_INT_FE 0x080 126 #define PL011_INT_RT 0x040 127 #define PL011_INT_TX 0x020 128 #define PL011_INT_RX 0x010 129 #define PL011_INT_DSR 0x008 130 #define PL011_INT_DCD 0x004 131 #define PL011_INT_CTS 0x002 132 #define PL011_INT_RIR 0x001 133 #define PL011_INT_MSMASK \ 134 (PL011_INT_DSR | PL011_INT_DCD | PL011_INT_CTS | PL011_INT_RIR) 135 136 #define PL011_INT_ALLMASK \ 137 (PL011_INT_RT | PL011_INT_TX | PL011_INT_RX | PL011_INT_MSMASK) 138 139 /* PL011 HW revision bits in PID (0..3 combined little endian) */ 140 #define PL011_HWREV_MASK 0x00f00000 141 #define PL011_DESIGNER_MASK 0x000ff000 142 #define PL011_DESIGNER_ARM 0x00041000 143 144 /* DMA control registers */ 145 #define PL011_DMA_ONERR 0x4 146 #define PL011_DMA_TXE 0x2 147 #define PL011_DMA_RXE 0x1 148 149 /* Register offsets */ 150 #define PL01XCOM_DR 0x00 /* Data Register */ 151 #define PL01XCOM_RSR 0x04 /* Receive status register */ 152 #define PL01XCOM_ECR 0x04 /* Error clear register - same as RSR */ 153 #define PL010COM_LCR 0x08 /* Line Control Register */ 154 #define PL010COM_DLBH 0x0c 155 #define PL010COM_DLBL 0x10 156 #define PL010COM_CR 0x14 157 #define PL01XCOM_FR 0x18 /* Flag Register */ 158 #define PL010COM_IIR 0x1c 159 #define PL010COM_ICR 0x1c 160 #define PL01XCOM_ILPR 0x20 /* IrDA low-power control register */ 161 #define PL011COM_IBRD 0x24 /* Integer baud rate divisor register */ 162 #define PL011COM_FBRD 0x28 /* Fractional baud rate divisor register */ 163 #define PL011COM_LCRH 0x2c /* Line control register */ 164 #define PL011COM_CR 0x30 /* Control register */ 165 #define PL011COM_IFLS 0x34 /* Interrupt FIFO level select register */ 166 #define PL011COM_IMSC 0x38 /* Interrupt mask set/clear register */ 167 #define PL011COM_RIS 0x3c /* Raw interrupt status register */ 168 #define PL011COM_MIS 0x40 /* Masked interrupt status register */ 169 #define PL011COM_ICR 0x44 /* Interrupt clear register register */ 170 #define PL011COM_DMACR 0x48 /* DMA control register register */ 171 #define PL011COM_PID0 0xfe0 /* Peripheral ID register 0 */ 172 #define PL011COM_PID1 0xfe4 /* Peripheral ID register 1 */ 173 #define PL011COM_PID2 0xfe8 /* Peripheral ID register 2 */ 174 #define PL011COM_PID3 0xfec /* Peripheral ID register 3 */ 175 176 #define PL010COM_UART_SIZE 0x100 177 #define PL011COM_UART_SIZE 0x1000 178 179 #endif /* _SYS_ARCH_EVBARM_DEV_PLCOMREG_H_ */ 180
Indexes created Mon Sep 22 05:09:51 GMT 2025