1 /* $NetBSD: e500reg.h,v 1.17 2022/05/24 20:50:18 andvar Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 #ifdef _LOCORE 40 #define __PPCBIT(n) (1 << (31 - (n))) 41 #define __PPCBITS(m, n) (((1 << ((n) - (m) + 1)) - 1) << (31 - (m))) 42 #else 43 #define __PPCBIT(n) __BIT(31-(n)) 44 #define __PPCBITS(m,n) __BITS(31-(n),31-(m)) 45 #endif 46 47 #define GUR_SIZE 0x100000 48 #define GUR_BPTR 0x0020 /* Boot Page Translation */ 49 #define BPTR_EN __PPCBIT(0) /* Boot Page Enabled */ 50 #define BPTR_BOOT_PAGE __PPCBITS(8,31) /* high 24 bits of phys addr */ 51 52 #define DDRC1_BASE 0x02000 53 #define DDRC2_BASE 0x06000 54 #define DDRC_SIZE 0x01000 55 56 #ifdef DDRC_PRIVATE 57 #define CS_BNDS(n) (0x000 + 0x008 * (n)) 58 #define BNDS_SA __PPCBITS(4,15) 59 #define BNDS_SA_GET(n) (((n) & BNDS_SA) << 8) 60 #define BNDS_EA __PPCBITS(20,31) 61 #define BNDS_EA_GET(n) (((n) & BNDS_EA) << 24) 62 #define BNDS_SIZE_GET(n) \ 63 ((((((n) & BNDS_EA) + __LOWEST_SET_BIT(BNDS_EA)) << 16) - (((n) & BNDS_SA))) << 8) 64 #define CS_CONFIG(n) (0x080 + 0x004 * (n)) 65 #define CS_CONFIG_EN __PPCBIT(0) 66 67 #define DDR_SDRAM_CFG 0x110 68 #define SDRAM_CFG_MEM_EN __PPCBIT(0) 69 #define SDRAM_CFG_SREN __PPCBIT(1) 70 #define SDRAM_CFG_ECC_EN __PPCBIT(2) 71 #define SDRAM_CFG_RDEN __PPCBIT(3) 72 #define SDRAM_CFG_TYPE __PPCBITS(5,7) 73 #define SDRAM_CFG_TYPE_DDR2 3 74 #define SDRAM_CFG_TYPE_DDR3 7 75 #define SDRAM_CFG_DYN_PWR __PPCBIT(10) 76 #define SDRAM_CFG_DBW __PPCBITS(11,12) 77 #define SDRAM_CFG_DBW_64BIT 0 78 #define SDRAM_CFG_DBW_32BIT 1 79 80 #define CAPTURE_DATA_HI 0xe20 81 #define CAPTURE_DATA_LO 0xe24 82 #define CAPTURE_ECC 0xe28 83 84 #define ERR_DETECT 0xe40 85 #define ERR_DISABLE 0xe44 86 #define ERR_INT_EN 0xe48 87 88 #define ERR_MMEE __PPCBIT(0) 89 #define ERR_APEE __PPCBIT(23) 90 #define ERR_ACEE __PPCBIT(24) 91 #define ERR_MBEE __PPCBIT(28) 92 #define ERR_SBEE __PPCBIT(29) 93 #define ERR_MSEE __PPCBIT(31) 94 95 #define CAPTURE_ATTRIBUTES 0xe4c 96 #define CATTR_BNUM __PPCBITS(1,3) 97 #define CATTR_TSIZ __PPCBITS(5,7) 98 #define CATTR_TSRC __PPCBITS(11,15) 99 #define CATTR_TTYP __PPCBITS(18,19) 100 #define CATTR_VLD __PPCBIT(31) 101 102 #define CAPTURE_ADDRESS 0xe50 103 #define CAPTURE_EXT_ADDRESS 0xe54 104 105 #define ERR_SBE 0xe58 106 #define ERR_SBE_SBET __PPCBITS(8,15) 107 #define ERR_SBE_SBEC __PPCBITS(24,31) 108 109 #endif /* DDRC_PRIVATE */ 110 111 #define GPIO_BASE 0x0fc00 112 #define GPIO_SIZE 0x00020 113 114 #ifdef GPIO_PRIVATE 115 116 #define GPDIR 0x00 /* GPIO direction register */ 117 #define GPODR 0x04 /* GPIO open drain register */ 118 #define GPDAT 0x08 /* GPIO data register */ 119 #define GPIER 0x0C /* GPIO interrupt event register */ 120 #define GPIMR 0x10 /* GPIO interrupt mask register */ 121 #define GPICR 0x14 /* GPIO external interrupt control register */ 122 123 #endif /* GPIO_PRIVATE */ 124 125 #define PCIE1_BASE 0x0a000 126 #define PCIE2_MPC8572_BASE 0x09000 /* P2020 too */ 127 #define PCIE3_MPC8572_BASE 0x08000 /* P2020 too */ 128 #define PCIX1_MPC8548_BASE 0x08000 129 #define PCIX2_MPC8548_BASE 0x09000 130 #define PCIE2_MPC8544_BASE 0x09000 /* MPC8536 too */ 131 #define PCIE3_MPC8544_BASE 0x0b000 /* MPC8536 too */ 132 #define PCIX1_MPC8544_BASE 0x08000 /* MPC8536 too */ 133 #define PCI_SIZE 0x01000 134 135 #ifdef PCI_PRIVATE 136 137 /* PCI Express Configuration Access Registers */ 138 #define PEX_CONFIG_ADDR 0x000 /* PCI Express configuration address register */ 139 #define PCI_CONFIG_ADDR PEX_CONFIG_ADDR 140 #define PEX_CONFIG_ADDR_EN __PPCBIT(0) 141 #define PEX_CONFIG_ADDR_TAG(b,d,f,r) (((b) << 16) | ((d) << 11) | ((f) << 8) | (r)) 142 #define PEX_CONFIG_DATA 0x004 /* PCI Express configuration data register */ 143 #define PCI_CONFIG_DATA PEX_CONFIG_DATA 144 #define PCI_INT_ACK 0x008 /* PCI Interrupt Acknowledge */ 145 #define PEX_OTB_CPL_TOR 0x00C /* PCI Express outbound completion timeout register */ 146 #define PEX_CONF_RTY_TOR 0x010 /* PCI Express configuration retry timeout register */ 147 #define PEX_CONFIG 0x014 /* PCI Express configuration register */ 148 149 /* PCI Express Power Management Event & Message Registers */ 150 #define PEX_PME_MES_DR 0x020 /* PCI Express PME & message detect register */ 151 #define PEX_PME_MES_DISR 0x024 /* PCI Express PME & message disable register */ 152 #define PEX_PME_MES_IER 0x028 /* PCI Express PME & message interrupt enable register */ 153 #define PEX_PMCR 0x02C /* PCI Express power management command register */ 154 155 /* PCI Express IP Block Revision Registers */ 156 #define PEX_IP_BLK_REV1 0xBF8 /* IP block revision register 1 */ 157 #define PEX_IP_BLK_REV2 0xBFC /* IP block revision register 2 */ 158 159 /* PCI Express / PCI-X ATMU Registers */ 160 #define PEXOWAR_EN __PPCBIT(0) /* enable window */ 161 #define PEXOWAR_ROE __PPCBIT(3) /* relaxed ordering enable */ 162 #define PEXOWAR_NS __PPCBIT(4) /* no snoop enable */ 163 #define PEXOWAR_TC __PPCBITS(8,10) /* traffic class PCIEX only */ 164 #define PEXOWAR_TC0 __SHIFTIN(0, PEXOWAR_TC) 165 #define PEXOWAR_TC1 __SHIFTIN(1, PEXOWAR_TC) 166 #define PEXOWAR_TC2 __SHIFTIN(2, PEXOWAR_TC) 167 #define PEXOWAR_TC3 __SHIFTIN(3, PEXOWAR_TC) 168 #define PEXOWAR_TC4 __SHIFTIN(4, PEXOWAR_TC) 169 #define PEXOWAR_TC5 __SHIFTIN(5, PEXOWAR_TC) 170 #define PEXOWAR_TC6 __SHIFTIN(6, PEXOWAR_TC) 171 #define PEXOWAR_TC7 __SHIFTIN(7, PEXOWAR_TC) 172 #define PEXOWAR_RTT __PPCBITS(12,15) /* read transaction type */ 173 #define PEXOWAR_RTT_CONF __SHIFTIN(2, PEXOWAR_RTT) /* PCIEX only */ 174 #define PEXOWAR_RTT_MEM __SHIFTIN(4, PEXOWAR_RTT) 175 #define PEXOWAR_RTT_IO __SHIFTIN(8, PEXOWAR_RTT) 176 #define PEXOWAR_WTT __PPCBITS(16,19) /* write transaction type */ 177 #define PEXOWAR_WTT_CONF __SHIFTIN(2, PEXOWAR_WTT) /* PCIEX only */ 178 #define PEXOWAR_WTT_MEM __SHIFTIN(4, PEXOWAR_WTT) 179 #define PEXOWAR_WTT_IO __SHIFTIN(8, PEXOWAR_WTT) 180 #define PEXOWAR_OWS __PPCBITS(26,31) /* encoded as 2^(N+1) bytes */ 181 182 /* PCI Express / PCI-X ATMU Registers */ 183 #define PEXIWAR_EN __PPCBIT(0) /* enable window */ 184 #define PEXIWAR_PF __PPCBIT(3) /* prefetchable */ 185 #define PEXIWAR_TRGT __PPCBITS(8,11) /* traffic class PCIEX only */ 186 #define PEXIWAR_TRGT_PCI1 __SHIFTIN(0, PEXIWAR_TRGT) 187 #define PEXIWAR_TRGT_PCI2 __SHIFTIN(1, PEXIWAR_TRGT) 188 #define PEXIWAR_TRGT_PCIEX __SHIFTIN(2, PEXIWAR_TRGT) 189 #define PEXIWAR_TRGT_SRIO __SHIFTIN(12, PEXIWAR_TRGT) 190 #define PEXIWAR_TRGT_LOCALMEM __SHIFTIN(15, PEXIWAR_TRGT) 191 #define PEXIWAR_RTT __PPCBITS(12,15) /* read transaction type */ 192 #define PEXIWAR_RTT_MEM __SHIFTIN(4, PEXIWAR_RTT) 193 #define PEXIWAR_RTT_MEM_NOSNOOP __SHIFTIN(4, PEXIWAR_RTT) 194 #define PEXIWAR_RTT_MEM_SNOOP __SHIFTIN(5, PEXIWAR_RTT) 195 #define PEXIWAR_RTT_MEM_ULCKL2 __SHIFTIN(7, PEXIWAR_RTT) 196 #define PEXIWAR_WTT __PPCBITS(16,19) /* write transaction type */ 197 #define PEXIWAR_WTT_MEM_NOSNOOP __SHIFTIN(4, PEXIWAR_WTT) 198 #define PEXIWAR_WTT_MEM_SNOOP __SHIFTIN(5, PEXIWAR_WTT) 199 #define PEXIWAR_WTT_MEM_ALLOL2 __SHIFTIN(6, PEXIWAR_WTT) 200 #define PEXIWAR_WTT_MEM_ALCKL2 __SHIFTIN(7, PEXIWAR_WTT) 201 #define PEXIWAR_IWS __PPCBITS(26,31) /* encoded as 2^(N+1) bytes */ 202 #define PEXIWAR_IWS_GET(n) __SHIFTOUT((n), PEXIWAR_IWS) 203 204 /* Outbound Window 0 (Default) */ 205 #define PEXOTAR0 0xC00 /* PCI Express outbound translation address register 0 (default) */ 206 #define PEXOTEAR0 0xC04 /* PCI Express outbound translation extended address register 0 (default) */ 207 #define PEXOWAR0 0xC10 /* PCI Express outbound window attributes register 0 (default) */ 208 209 /* Outbound Window 1 */ 210 #define PEXOTAR1 0xC20 /* PCI Express outbound translation address register 1 */ 211 #define PEXOTEAR1 0xC24 /* PCI Express outbound translation extended address register 1 */ 212 #define PEXOWBAR1 0xC28 /* PCI Express outbound window base address register 1 */ 213 #define PEXOWAR1 0xC30 /* PCI Express outbound window attributes register 1 */ 214 215 /* Outbound Window 2 */ 216 #define PEXOTAR2 0xC40 /* PCI Express outbound translation address register 2 */ 217 #define PEXOTEAR2 0xC44 /* PCI Express outbound translation extended address register 2 */ 218 #define PEXOWBAR2 0xC48 /* PCI Express outbound window base address register 2 */ 219 #define PEXOWAR2 0xC50 /* PCI Express outbound window attributes register 2 */ 220 221 /* Outbound Window 3 */ 222 #define PEXOTAR3 0xC60 /* PCI Express outbound translation address register 3 */ 223 #define PEXOTEAR3 0xC64 /* PCI Express outbound translation extended address register 3 */ 224 #define PEXOWBAR3 0xC68 /* PCI Express outbound window base address register 3 */ 225 #define PEXOWAR3 0xC70 /* PCI Express outbound window attributes register 3 */ 226 227 /* Outbound Window 4 */ 228 #define PEXOTAR4 0xC80 /* PCI Express outbound translation address register 4 */ 229 #define PEXOTEAR4 0xC84 /* PCI Express outbound translation extended address register 4 */ 230 #define PEXOWBAR4 0xC88 /* PCI Express outbound window base address register 4 */ 231 #define PEXOWAR4 0xC90 /* PCI Express outbound window attributes register 4 */ 232 233 /* Inbound Window 3 */ 234 #define PEXITAR3 0xDA0 /* PCI Express inbound translation address register 3 */ 235 #define PEXIWBAR3 0xDA8 /* PCI Express inbound window base address register 3 */ 236 #define PEXIWBEAR3 0xDAC /* PCI Express inbound window base extended address register 3 */ 237 #define PEXIWAR3 0xDB0 /* PCI Express inbound window attributes register 3 */ 238 239 /* Inbound Window 2 */ 240 #define PEXITAR2 0xDC0 /* PCI Express inbound translation address register 2 */ 241 #define PEXIWBAR2 0xDC8 /* PCI Express inbound window base address register 2 */ 242 #define PEXIWBEAR2 0xDCC /* PCI Express inbound window base extended address register 2 */ 243 #define PEXIWAR2 0xDD0 /* PCI Express inbound window attributes register 2 */ 244 245 /* Inbound Window 1 */ 246 #define PEXITAR1 0xDE0 /* PCI Express inbound translation address register 1 */ 247 #define PEXIWBAR1 0xDE8 /* PCI Express inbound window base address register 1 */ 248 #define PEXIWAR1 0xDF0 /* PCI Express inbound window attributes register 1 */ 249 250 /* PCI Express Error Management Registers */ 251 #define PEX_ERR_DR 0xE00 /* PCI Express error detect register */ 252 #define PEXERRDR_ICCA __PPCBIT(14) 253 #define PEX_ERR_EN 0xE08 /* PCI Express error interrupt enable register */ 254 #define PEX_ERR_DISR 0xE10 /* PCI Express error disable register */ 255 #define PEX_ERR_CAP_STAT 0xE20 /* PCI Express error capture status register */ 256 #define PEX_ERR_CAP_R0 0xE28 /* PCI Express error capture register 0 */ 257 #define PEX_ERR_CAP_R1 0xE2C /* PCI Express error capture register 1 */ 258 #define PEX_ERR_CAP_R2 0xE30 /* PCI Express error capture register 2 */ 259 #define PEX_ERR_CAP_R3 0xE34 /* PCI Express error capture register 3 */ 260 261 /* PCI Express Private Configuration Space */ 262 263 #define PEX_LTSSM 0x404 264 #define LTSSM_L0 16 265 266 #define PCI_PBFR 0x44 /* Bus Function Register */ 267 #define PBFR_PAH __BIT(0) 268 269 #endif /* PCI_PRIVATE */ 270 271 #define OPENPIC_BASE 0x40000 272 #define OPENPIC_SIZE 0x40000 273 274 #define L2CACHE_BASE 0x20000 275 #define L2CACHE_SIZE 0x01000 276 277 #ifdef L2CACHE_PRIVATE 278 #define L2CTL 0x000 279 #define L2CTL_L2E __PPCBIT(0) 280 #define L2CTL_L2I __PPCBIT(1) 281 #define L2CTL_L2SIZ __PPCBITS(2,3) 282 #define L2CTL_L2SIZ_GET(x) (1 << (17 + __SHIFTOUT((x), L2CTL_L2SIZ))) 283 #define L2CTL_L2DO __PPCBIT(9) 284 #define L2CTL_L2IO __PPCBIT(10) 285 #define L2CTL_L2INTDIS __PPCBIT(12) 286 #define L2CTL_L2SRAM __PPCBITS(13,15) 287 #define L2CTL_L2LO __PPCBIT(18) 288 #define L2CTL_L2SLC __PPCBIT(19) 289 #define L2CTL_L2LFR __PPCBIT(21) 290 #define L2CTL_L2LFRID __PPCBITS(22,23) 291 #define L2CTL_L2STASHDIS __PPCBIT(28) 292 #define L2CTL_L2STASH __PPCBITS(30,31) 293 294 #endif /* L2CACHE_PRIVATE */ 295 296 #define I2C1_BASE 0x3000 297 #define I2C2_BASE 0x3100 298 #define I2C_SIZE 0x0100 299 300 #ifdef I2C_PRIVATE 301 #define I2CADR 0x000 /* i2c address register */ 302 #define I2CFDR 0x004 /* i2c frequency divider register */ 303 #define I2CCR 0x008 /* i2c control register */ 304 #define I2CSR 0x00c /* i2c status register */ 305 #define I2CDR 0x010 /* i2c data register */ 306 #define I2CDFSSR 0x014 /* i2c address register */ 307 #endif /* I2C_PRIVATE */ 308 309 #define DUART1_BASE 0x4500 310 #define DUART2_BASE 0x4600 311 #define DUART_SIZE 0x0100 312 313 #define SPI_BASE 0x7000 /* MPC8536 */ 314 #define SPI_SIZE 0x1000 315 316 #ifdef SPI_PRIVATE 317 #define SPMODE 0x000 /* mode register */ 318 #define SPMODE_EN __PPCBIT(0) /* Enable eSPI: 0=disabled, 1=enabled */ 319 #define SPMODE_LOOP __PPCBIT(1) /* Loop mode: 0=normal, 1=loopback */ 320 #define SPMODE_OD __PPCBIT(2) /* P1023: Open drain mode: 0=actively driven, 1=open drain */ 321 #define SPMODE_HO_ADJ __PPCBITS(13,15) /* Data output hold adjustment */ 322 #define SPMODE_TXTHR __PPCBITS(18,23) /* Tx FIFO Threshold: 1-32 */ 323 #define SPMODE_RXTHR __PPCBITS(27,31) /* Rx FIFO threshold: 0-31 */ 324 #define SPIE 0x004 /* event register */ 325 #define SPIE_RXCNT __PPCBITS(2,7) /* current number of full Rx FIFO bytes */ 326 #define SPIE_TXCNT __PPCBITS(10,15) /* current number of full Tx FIFO bytes */ 327 #define SPIE_TXE __PPCBIT(16) /* Tx FIFO is empty */ 328 #define SPIE_DON __PPCBIT(17) /* Last character was transmitted */ 329 #define SPIE_RXT __PPCBIT(18) /* Rx FIFO has more than RXTHR bytes */ 330 #define SPIE_RXF __PPCBIT(19) /* Rx FIFO is full */ 331 #define SPIE_TXT __PPCBIT(20) /* Tx FIFO has less than TXTHR bytes */ 332 #define SPIE_RNE __PPCBIT(22) /* Not empty: 0=empty, 1=not empty */ 333 #define SPIE_TNF __PPCBIT(23) /* Tx FIFO not full: 0=full, 1=not full */ 334 #define SPIM 0x008 /* mask register */ 335 #define SPIM_TXE __PPCBIT(16) 336 #define SPIM_DON __PPCBIT(17) 337 #define SPIM_RXT __PPCBIT(18) 338 #define SPIM_RXF __PPCBIT(19) 339 #define SPIM_TXT __PPCBIT(20) 340 #define SPIM_RNE __PPCBIT(22) 341 #define SPIM_TNF __PPCBIT(23) 342 #define SPCOM 0x00c /* command register */ 343 #define SPCOM_CS __PPCBITS(0,1) /* Chip select: 0=CS0, 1=CS1, 2=CS2(P1025), 3=CS3(P1025) */ 344 #define SPCOM_RXDELAY __PPCBIT(2) /* 0=normal eSPI operation */ 345 #define SPCOM_DO __PPCBIT(3) /* 0=normal eSPI operation, 1=Winbond dual output read */ 346 #define SPCOM_TO __PPCBIT(4) /* Transmit only: 0=normal operation, 1=No reception is done for the frame */ 347 #define SPCOM_HLD __PPCBIT(5) /* 0=normal operation, 1=Mask first generated SPI_CLK */ 348 #define SPCOM_LS __PPCBIT(6) /* P1023: Late sample: 0=normal operation, 1=Late data sample */ 349 #define SPCOM_RXSKIP __PPCBITS(8,15) /* if RxSKIP != 0: Number of characters skipped for reception from frame start */ 350 #define SPCOM_TRANLEN __PPCBITS(16,31) /* Transaction length */ 351 #define SPITF 0x010 /* transmit FIFO access register */ 352 #define SPIRF 0x014 /* receive FIFO access register */ 353 #define SPMODE0 0x020 /* CS0 mode register */ 354 #define SPMODE1 0x024 /* CS1 mode register */ 355 #define SPMODE2 0x028 /* CS2 mode register (P1025) */ 356 #define SPMODE3 0x02c /* CS3 mode register (P1025) */ 357 #define SPMODEn(n) (0x020+(n)*4) 358 #define SPMODEn_CI __PPCBIT(0) /* Clock invert: 0=inactive state of SPI_CLK is low, 1=high */ 359 #define SPMODEn_CP __PPCBIT(1) /* Clock phase: SPI_CLK starts toggling at the middle of the data transfer, 1=beginning */ 360 #define SPMODEn_REV __PPCBIT(2) /* Reverse data mode: 0=LSB of the character sent and received first, 1=MSB */ 361 #define SPMODEn_DIV16 __PPCBIT(3) /* Divide by 16: 0=System clock, 1=System clock/16 */ 362 #define SPMODEn_PM __PPCBITS(4,7) /* Prescale modulus select */ 363 #define SPMODEn_ODD __PPCBIT(8) /* 0=Even division, 1=Odd dividion */ 364 #define SPMODEn_POL __PPCBIT(11) /* CS polarity: 0=Asserted high/Negated low, 1=Asserted low/Negated high */ 365 #define SPMODEn_LEN __PPCBITS(12,15) /* Character length in bits per character */ 366 #define SPMODEn_CSBEF __PPCBITS(16,19) /* CS assertion time in bits before frame start */ 367 #define SPMODEn_CSAFT __PPCBITS(20,23) /* CS assertion time in bits after frame end */ 368 #define SPMODEn_CSCG __PPCBITS(24,28) /* Clock gap */ 369 #endif 370 371 #define SATA1_BASE 0x18000 /* MPC8536 */ 372 #define SATA2_BASE 0x19000 /* MPC8536 */ 373 #define SATA_SIZE 0x01000 374 375 #define USB1_BASE 0x22100 /* MPC8536 */ 376 #define USB2_BASE 0x23100 /* MPC8536 */ 377 #define USB3_BASE 0x2b100 /* MPC8536 */ 378 #define USB_SNOOP1 0x0300 /* DMA Snooping Register 1 */ 379 #define USB_SNOOP2 0x0304 /* DMA Snooping Register 2 */ 380 #define USB_CONTROL 0x0400 /* USB General Purpose Register */ 381 #define USB_EN __PPCBIT(29) 382 #define USB_ULPI_INT_EN __PPCBIT(31) 383 #define USB_SIZE 0x00f00 384 385 #define SNOOP_2GB 0x1e 386 387 #define ETSEC1_BASE 0x24000 388 #define ETSEC2_BASE 0x25000 389 #define ETSEC3_BASE 0x26000 390 #define ETSEC4_BASE 0x27000 391 #define ETSEC1_G0_BASE 0xB0000 392 #define ETSEC2_G0_BASE 0xB1000 393 #define ETSEC3_G0_BASE 0xB2000 394 #define ETSEC1_G1_BASE 0xB4000 395 #define ETSEC2_G1_BASE 0xB5000 396 #define ETSEC3_G1_BASE 0xB6000 397 #define ETSEC_SIZE 0x01000 398 399 #define ESDHC_BASE 0x2e000 400 #define ESDHC_SIZE 0x01000 401 402 #ifdef ESDHC_PRIVATE 403 404 #define DCR 0x40c /* DMA Control Register */ 405 406 #define DCR_SNOOP __PPCBIT(25) /* DMA transactions are snooped */ 407 #define DCR_RD_SAFE __PPCBIT(29) /* memory is read safe */ 408 #define DCR_RD_PFE __PPCBIT(30) /* memory is prefetch safe */ 409 #define DCR_RD_PF_SIZE __PPCBIT(31) /* prefetch size is 32-bytes */ 410 411 #endif 412 413 #define GLOBAL_BASE 0xe0000 414 #define GLOBAL_SIZE 0x01000 415 416 #ifdef GLOBAL_PRIVATE 417 418 /* Power-On Reset Configuration Values */ 419 #define PORPLLSR 0x000 /* POR PLL ratio status register */ 420 #define E500_RATIO2 __PPCBITS(2,7) 421 #define E500_RATIO2_GET(n) __SHIFTOUT(n, E500_RATIO2) 422 #define E500_RATIO __PPCBITS(10,15) 423 #define E500_RATIO_GET(n) __SHIFTOUT(n, E500_RATIO) 424 #define PCI1_CLK_SEL __PPCBIT(16) 425 #define PCI2_CLK_SEL __PPCBIT(17) 426 #define PLAT_RATIO __PPCBITS(26,30) 427 #define PLAT_RATIO_GET(n) __SHIFTOUT(n, PLAT_RATIO) 428 #define PORBMSR 0x004 /* POR boot mode status register */ 429 #define PORBMSR_BCFG __PPCBITS(0,1) 430 #define PORBMSR_HA __PPCBITS(13,15) 431 #define PORBMSR_HA_GET(n) __SHIFTOUT(m, PORBMSR_HA) 432 #define PORBMSR_HA_PEXSRIO_AGENT 0 /* PCI Express & SRIO agent mode */ 433 #define PORBMSR_HA_SRIO_AGENT 1 /* SRIO agent mode */ 434 #define PORBMSR_HA_PEX_AGENT 2 /* PCI Express agent mode */ 435 #define PORBMSR_HA_PEXPCI_AGENT2 3 /* PCI[-X] & PCI Express agent mode */ 436 #define PORBMSR_HA_PCISRIO_AGENT2 4 /* PCI[-X] & SRIO mode */ 437 #define PORBMSR_HA_SRIO_AGENT2 5 /* SRIO agent mode */ 438 #define PORBMSR_HA_PCI_AGENT2 6 /* PCI[-X] agent mode */ 439 #define PORBMSR_HA_HOST 7 /* Host mode */ 440 #define PORIMPSCR 0x008 /* POR I/O impedance status and control register */ 441 #define PORDEVSR 0x00C /* POR I/O device status register */ 442 #define PORDEVSR_ECW1 __PPCBIT(0) 443 #define PORDEVSR_ECW2 __PPCBIT(1) 444 #define PORDEVSR_SGMII1_DIS1 __PPCBIT(2) 445 #define PORDEVSR_SGMII1_DIS2 __PPCBIT(3) 446 #define PORDEVSR_SGMII1_DIS3 __PPCBIT(4) 447 #define PORDEVSR_SGMII1_DIS4 __PPCBIT(5) 448 #define PORDEVSR_ECP1 __PPCBITS(6,7) 449 #define PORDEVSR_PCI1 __PPCBIT(8) 450 #define PCI1_PCIX 0 451 #define PCI1_PCI1 1 452 #define PORDEVSR_IOSEL_P1023 __PPCBITS(9,10) 453 #define IOSEL_P1023_PCIE12_X1 0 454 #define IOSEL_P1023_PCIE123_X1 1 455 #define IOSEL_P1023_PCIE123_X1_SGMII2 2 456 #define IOSEL_P1023_PCIE12_X1_SGMII12 3 457 #define PORDEVSR_IOSEL __PPCBITS(9,12) 458 #define IOSEL_MPC8536_OFF 0x01 459 #define IOSEL_MPC8536_PCIE1_X4 0x02 460 #define IOSEL_MPC8536_PCIE1_X8 0x03 461 #define IOSEL_MPC8536_PCIE12_X4 0x05 462 #define IOSEL_MPC8536_PCIE1_X4_PCI23_X2 0x07 463 #define IOSEL_MPC8544_OFF 0x00 464 #define IOSEL_MPC8544_SGMII_ON 0x01 465 #define IOSEL_MPC8544_PCIE1_ON 0x02 466 #define IOSEL_MPC8544_PCIE1_SGMII_ON 0x03 467 #define IOSEL_MPC8544_PCIE12_ON 0x04 468 #define IOSEL_MPC8544_PCIE12_SGMII_ON 0x05 469 #define IOSEL_MPC8544_PCIE123_ON 0x06 470 #define IOSEL_MPC8544_PCIE123_SGMII_ON 0x07 471 #define IOSEL_MPC8548_SRIO2500_PCIE1_X4 3 472 #define IOSEL_MPC8548_SRIO1250_PCIE1_X4 4 473 #define IOSEL_MPC8548_SRIO3125 5 474 #define IOSEL_MPC8548_SRIO1250 6 475 #define IOSEL_MPC8548_PCIE1_X8 7 476 #define IOSEL_MPC8572_PCIE1_X4 2 477 #define IOSEL_MPC8572_PCIE12_X4 3 478 #define IOSEL_MPC8572_SRIO2500 6 479 #define IOSEL_MPC8572_PCIE1_X4_23_X2 7 480 #define IOSEL_MPC8572_SRIO2500_PCIE1_X4 11 481 #define IOSEL_MPC8572_SRIO1250_PCIE1_X4 12 482 #define IOSEL_MPC8572_SRIO3125 13 483 #define IOSEL_MPC8572_SRIO1250 14 484 #define IOSEL_MPC8572_PCIE1_X8 15 485 #define IOSEL_P20x0_PCIE1_X1 0 486 #define IOSEL_P20x0_PCIE12_X1_3_X2 2 487 #define IOSEL_P20x0_PCIE13_X2 4 488 #define IOSEL_P20x0_PCIE1_X4 6 489 #define IOSEL_P20x0_PCIE1_X1_SRIO2500_1X 13 490 #define IOSEL_P20x0_PCIE12_X1_SGMII23 14 491 #define IOSEL_P20x0_PCIE1_X2_SGMII23 15 492 #define IOSEL_P1025_PCIE1_X1 0 /* same at P20x10 */ 493 #define IOSEL_P1025_PCIE1_X4 6 /* same at P20x10 */ 494 #define IOSEL_P1025_PCIE12_X1_SGMII23 14 /* same at P20x10 */ 495 #define IOSEL_P1025_PCIE1_X2_SGMII23 15 /* same at P20x10 */ 496 #define PORDEVSR_PCI2_ARB __PPCBIT(13) 497 #define PORDEVSR_PCI1_ARB __PPCBIT(14) 498 #define PORDEVSR_PCI32 __PPCBIT(15) 499 #define PCI32_FALSE 0 500 #define PCI32_TRUE 1 501 #define PORDEVSR_PCI1_SPD __PPCBIT(16) 502 #define PORDEVSR_PCI2_SPD __PPCBIT(17) 503 #define PORDEVSR_SYS_SPD __PPCBIT(17) /* MPC8536 */ 504 #define PORDEVSR_CORE_SPD __PPCBIT(18) /* MPC8536 */ 505 #define PORDEVSR_ECP2 __PPCBITS(18,19) 506 #define PORDEVSR_ECP3 __PPCBITS(20,21) 507 #define PORDEVSR_ECP4 __PPCBITS(22,23) 508 #define PORDEVSR_FEC_DIS __PPCBIT(24) 509 #define PORDEVSR_RTPE __PPCBIT(25) 510 #define PORDEVSR_RIO_CTLS __PPCBIT(28) 511 #define PORDEVSR_DEV_ID __PPCBITs(29,31) 512 #define PORDBGMSR 0x010 /* POR debug mode status register */ 513 #define PORDEVSR2 0x014 /* POR I/O device status register 2 */ 514 #define GPPORCR 0x020 /* General-purpose POR configuration register */ 515 516 /* Signal Multiplexing and GPIO Controls */ 517 #define GPIOCR 0x030 /* GPIO control register */ 518 #define GPIOCR_TX2 __PPCBIT(6) /* Enable TSEC2_TX[7:0] as GP output */ 519 #define GPIOCR_RX2 __PPCBIT(7) /* Enable TSEC2_RX[7:0] as GP input */ 520 #define GPIOCR_PCIOUT __PPCBIT(14) /* Enable PCI2_AD[15:8] as GP output */ 521 #define GPIOCR_PCIIN __PPCBIT(15) /* Enable PCI2_AD[7:0] as GP input */ 522 #define GPIOCR_GPOUT __PPCBIT(22) /* Enable GPOUT[24:31] as GP output */ 523 #define GPOUTDR 0x040 /* General-purpose output data register */ 524 #define GPOUTDR_TX2 0x040 /* General-purpose output data register */ 525 #define GPOUTDR_PCI 0x041 /* General-purpose output data register */ 526 #define GPOUTDR_GPOUT 0x043 /* General-purpose output data register */ 527 #define GPINDR 0x050 /* General-purpose input data register */ 528 #define GPINDR_RX2 0x059 529 #define GPINDR_PCI 0x051 530 531 #define PMUXCR 0x060 /* Alternate function signal multiplex control */ 532 #define PMUXCR_SD_DATA __PPCBIT(0) 533 #define PMUXCR_SDHC_CD __PPCBIT(1) 534 #define PMUXCR_SDHC_WP __PPCBIT(2) 535 #define PMUXCR_PCI_REQGNT3 __PPCBIT(3) 536 #define PMUXCR_TSEC1_TS __PPCBIT(3) 537 #define PMUXCR_PCI_REQGNT4 __PPCBIT(4) 538 #define PMUXCR_TSEC2_TS __PPCBIT(4) 539 #define PMUXCR_USB1 __PPCBIT(5) 540 #define PMUXCR_TSEC3_TS __PPCBIT(5) 541 #define PMUXCR_USB2 __PPCBIT(6) 542 #define PMUXCR_USB_PCTL __PPCBITS(6,5) 543 #define PMUXCR_USB __PPCBIT(6) 544 #define PMUXCR_TSEC1 __PPCBIT(14) 545 #define PMUXCR_DMA0 __PPCBIT(14) 546 #define PMUXCR_DMA2 __PPCBIT(15) 547 #define PMUXCR_QE0 __PPCBIT(16) 548 #define PMUXCR_QE1 __PPCBIT(17) 549 #define PMUXCR_QE2 __PPCBIT(18) 550 #define PMUXCR_QE3 __PPCBIT(19) 551 #define PMUXCR_QE8 __PPCBIT(24) 552 #define PMUXCR_QE9 __PPCBIT(25) 553 #define PMUXCR_QE10 __PPCBIT(26) 554 #define PMUXCR_QE11 __PPCBIT(27) 555 #define PMUXCR_QE12 __PPCBIT(28) 556 #define PMUXCR_DMA1 __PPCBIT(30) 557 #define PMUXCR_DMA3 __PPCBIT(31) 558 559 #define PMUXCR2 0x064 /* Alternate function signal multiplex control2 */ 560 561 /* Device Disables */ 562 #define DEVDISR 0x070 /* Device disable control */ 563 #define DEVDISR_PCI1 __PPCBIT(0) 564 #define DEVDISR_QMAN_BMAN __PPCBIT(0) /* P1023 */ 565 #define DEVDISR_PCI2 __PPCBIT(1) 566 #define DEVDISR_FMAN __PPCBIT(1) /* P1023 */ 567 #define DEVDISR_PCIE __PPCBIT(2) 568 #define DEVDISR_MACSEC __PPCBIT(3) /* P1023 */ 569 #define DEVDISR_LBC __PPCBIT(4) 570 #define DEVDISR_PCIE2 __PPCBIT(5) 571 #define DEVDISR_PCIE3 __PPCBIT(6) 572 #define DEVDISR_SEC __PPCBIT(7) 573 #define DEVDISR_PME __PPCBIT(8) 574 #define DEVDISR_USB1 __PPCBIT(8) /* MPC8536 */ 575 #define DEVDISR_TLU1 __PPCBIT(9) 576 #define DEVDISR_USB2 __PPCBIT(9) /* MPC8536 */ 577 #define DEVDISR_TLU2 __PPCBIT(10) 578 #define DEVDISR_ESDHC_10 __PPCBIT(10) 579 #define DEVDISR_USB3 __PPCBIT(10) /* MPC8536 */ 580 #define DEVDISR_L2 __PPCBIT(11) /* MPC8536 */ 581 #define DEVDISR_SRIO __PPCBIT(12) 582 #define DEVDISR_ESDHC_12 __PPCBIT(12) /* MPC8536 */ 583 #define DEVDISR_RMSG __PPCBIT(13) 584 #define DEVDISR_SATA1 __PPCBIT(13) /* MPC8536 */ 585 #define DEVDISR_DDR2_14 __PPCBIT(14) 586 #define DEVDISR_DDR_15 __PPCBIT(15) 587 #define DEVDISR_SPI_15 __PPCBIT(15) /* MPC8536 */ 588 #define DEVDISR_E500 __PPCBIT(16) 589 #define DEVDISR_DDR_16 __PPCBIT(16) /* MPC8536 */ 590 #define DEVDISR_TB __PPCBIT(17) 591 #define DEVDISR_E500_1 __PPCBIT(18) 592 #define DEVDISR_TB_1 __PPCBIT(19) 593 #define DEVDISR_SATA2 __PPCBIT(20) /* MPC8536 */ 594 #define DEVDISR_DMA __PPCBIT(21) 595 #define DEVDISR_DMA2 __PPCBIT(22) 596 #define DEVDISR_SRDS2 __PPCBIT(22) /* MPC8536 */ 597 #define DEVDISR_TSEC1 __PPCBIT(24) 598 #define DEVDISR_TSEC2 __PPCBIT(25) 599 #define DEVDISR_TSEC3 __PPCBIT(26) 600 #define DEVDISR_TSEC4 __PPCBIT(27) 601 #define DEVDISR_FEC __PPCBIT(28) 602 #define DEVDISR_SPI_28 __PPCBIT(28) /* P2020 */ 603 #define DEVDISR_I2C __PPCBIT(29) 604 #define DEVDISR_DUART __PPCBIT(30) 605 #define DEVDISR_SRDS1 __PPCBIT(31) /* MPC8536 */ 606 607 /* Power Management Registers */ 608 #define POWMGTCSR 0x080 /* Power management status and control register */ 609 610 /* Interrupt and Reset Status and Control */ 611 #define MCPSUMR 0x090 /* Machine check summary register */ 612 #define RSTRSCR 0x094 /* Reset request status and control register */ 613 614 /* Version Registers */ 615 #define PVR 0x0A0 /* Processor version register */ 616 #define SVR 0x0A4 /* System version register */ 617 618 /* Control Pin Registers (GPIO) for P1025 */ 619 #define CPBASE(n) (0x100+0x20*(n)) /* Control Pin (GPIO) base */ 620 #define CPODR 0x0000 /* Open Drain */ 621 #define CPDAT 0x0004 /* Output Data */ 622 #define CPDIR1 0x0008 /* Direction1 */ 623 #define CPDIR2 0x000c /* Direction2 */ 624 #define CPPAR1 0x0010 /* Pin Assignment1 */ 625 #define CPPAR2 0x0014 /* Pin Assignment2 */ 626 627 #define CPDIR_DIS 0 628 #define CPDIR_OUT 1 629 #define CPDIR_IN 2 630 #define CPDIR_INOUT 3 631 632 #define CPPAR_FUNC0 0 633 #define CPPAR_FUNC1 1 634 #define CPPAR_FUNC2 2 635 #define CPPAR_FUNC3 3 636 637 /* Status Registers */ 638 #define RSTCR 0x0B0 /* Reset control register */ 639 #define HRESET_REQ __PPCBIT(30) /* hardware reset request */ 640 #define LBCVSELCR 0x0C0 /* LBC voltage select control register */ 641 #define DDRCSR 0xB20 /* DDR calibration status register */ 642 #define DDRCDR 0xB24 /* DDR control driver register */ 643 #define DDRCLKDR 0xB28 /* DDR clock disable register */ 644 645 /* Debug Control */ 646 #define CLKOCR 0xE00 /* Clock out control register */ 647 #define SRDSCR0 0xF04 /* LSerDes control register 0 */ 648 #define SRDSCR1 0xF08 /* LSerDes control register 1 */ 649 #define TSEC12IOOVCR 0xF28 /* eTSEC 1 & 2 overdrive control register */ 650 #define TSEC34IOOVCR 0xF2C /* eTSEC 3 & 4 overdrive control register */ 651 #endif /* GLOBAL_PRIVATE */ 652 653 #define LBC_BASE 0x5000 654 #define LBC_SIZE 0x0fff 655 656 #ifdef LBC_PRIVATE 657 658 #define BR_BA __PPCBITS(0,16) 659 #define BR_XBA __PPCBITS(17,18) 660 #define BR_PS __PPCBITS(19,20) 661 #define BR_PS_8BIT __SHIFTIN(1,BR_PS) 662 #define BR_PS_16BIT __SHIFTIN(2,BR_PS) 663 #define BR_PS_32BIT __SHIFTIN(3,BR_PS) 664 #define BR_DECC __PPCBITS(21,22) 665 #define BR_DECC_NONE __SHIFTIN(0,BR_DECC) 666 #define BR_DECC_PARITY __SHIFTIN(1,BR_DECC) 667 #define BR_DECC_RMWPAR __SHIFTIN(2,BR_DECC) 668 #define BR_WP __PPCBIT(23) 669 #define BR_MSEL __PPCBITS(24,26) 670 #define BR_MSEL_GPCM __SHIFTIN(0,BR_MSEL) 671 #define BR_MSEL_FCM __SHIFTIN(1,BR_MSEL) 672 #define BR_MSEL_SDRAM __SHIFTIN(3,BR_MSEL) 673 #define BR_MSEL_UPMA __SHIFTIN(4,BR_MSEL) 674 #define BR_MSEL_UPMB __SHIFTIN(5,BR_MSEL) 675 #define BR_MSEL_UPMC __SHIFTIN(6,BR_MSEL) 676 #define BR_ATOM __PPCBITS(28,29) 677 #define BR_ATOM_NONE __SHIFTIN(0,BR_ATOM) 678 #define BR_ATOM_RAWA __SHIFTIN(1,BR_ATOM) 679 #define BR_ATOM_WARA __SHIFTIN(2,BR_ATOM) 680 #define BR_V __PPCBIT(31) 681 682 #define OR_AM __PPCBITS(0,16) 683 #define OR_XAM __PPCBITS(17,18) 684 #define OR_BCTLD __PPCBIT(19) 685 #define OR_CSNT __PPCBIT(20) 686 #define OR_ACS __PPCBITS(21,22) 687 #define OR_XACS __PPCBIT(23) 688 #define OR_SCY __PPCBITS(24,27) 689 #define OR_SETA __PPCBIT(28) 690 #define OR_TRLX __PPCBIT(29) 691 #define OR_EHTR __PPCBIT(30) 692 #define OR_EAD __PPCBIT(31) 693 694 #define BRn(n) (BR0 + 8*(n)) 695 #define ORn(n) (OR0 + 8*(n)) 696 #define BR0 0x000 /* Base register 0 */ 697 #define OR0 0x004 /* Options register 0 */ 698 #define BR1 0x008 /* Base register 1 */ 699 #define OR1 0x00C /* Options register 1 */ 700 #define BR2 0x010 /* Base register 2 */ 701 #define OR2 0x014 /* Options register 2 */ 702 #define BR3 0x018 /* Base register 3 */ 703 #define OR3 0x01C /* Options register 3 */ 704 #define BR4 0x020 /* Base register 4 */ 705 #define OR4 0x024 /* Options register 4 */ 706 #define BR5 0x028 /* Base register 5 */ 707 #define OR5 0x02C /* Options register 5 */ 708 #define BR6 0x030 /* Base register 6 */ 709 #define OR6 0x034 /* Options register 6 */ 710 #define BR7 0x038 /* Base register 7 */ 711 #define OR7 0x03C /* Options register 7 */ 712 #define MAR 0x068 /* UPM address register */ 713 #define MAMR 0x070 /* UPMA mode register */ 714 #define MBMR 0x074 /* UPMB mode register */ 715 #define MCMR 0x078 /* UPMC mode register */ 716 #define MRTPR 0x084 /* Memory refresh timer prescaler register */ 717 #define MDR 0x088 /* UPM/FCM data register */ 718 #define MDR_AS3 __PPCBITS(0,7) 719 #define MDR_AS2 __PPCBITS(8,15) 720 #define MDR_AS1 __PPCBITS(16,23) 721 #define MDR_AS0 __PPCBITS(24,31) 722 #define LSOR 0x090 /* Special Operation Initiation register */ 723 #define LSDMR 0x094 /* SDRAM mode register */ 724 #define LURT 0x0A0 /* UPM refresh timer */ 725 #define LSRT 0x0A4 /* SDRAM refresh timer */ 726 #define LTESR 0x0B0 /* Transfer error status register */ 727 #define LTESR_BM __PPCBIT(0) 728 #define LTESR_FCT __PPCBIT(1) 729 #define LTESR_PAR __PPCBIT(2) 730 #define LTESR_WP __PPCBIT(5) 731 #define LTESR_ATMW __PPCBIT(8) 732 #define LTESR_ATMR __PPCBIT(9) 733 #define LTESR_CS __PPCBIT(12) 734 #define LTESR_UCC __PPCBIT(30) 735 #define LTESR_CC __PPCBIT(31) 736 #define LTEDR 0x0B4 /* Transfer error disable register */ 737 #define LTEDR_BMD __PPCBIT(0) 738 #define LTEDR_FCTD __PPCBIT(1) 739 #define LTEDR_PARD __PPCBIT(2) 740 #define LTEDR_WPD __PPCBIT(5) 741 #define LTEDR_WARA __PPCBIT(8) 742 #define LTEDR_RAWA __PPCBIT(9) 743 #define LTEDR_CSD __PPCBIT(12) 744 #define LTEDR_UCCD __PPCBIT(30) 745 #define LTEDR_CCD __PPCBIT(31) 746 #define LTEIR 0x0B8 /* Transfer error interrupt register */ 747 #define LTEIR_BMI __PPCBIT(0) 748 #define LTEIR_FCTI __PPCBIT(1) 749 #define LTEIR_PARI __PPCBIT(2) 750 #define LTEIR_WPI __PPCBIT(5) 751 #define LTEIR_WARA __PPCBIT(8) 752 #define LTEIR_RAWA __PPCBIT(9) 753 #define LTEIR_CSI __PPCBIT(12) 754 #define LTEIR_UCCI __PPCBIT(30) 755 #define LTEIR_CCI __PPCBIT(31) 756 #define LTEATR 0x0BC /* Transfer error attributes register */ 757 #define LTEATR_RWB __PPCBIT(3) 758 #define LTEATR_SRCID __PPCBITS(11,15) 759 #define LTEATR_PB __PPCBITS(16,19) 760 #define LTEATR_BNK __PPCBITS(20,27) 761 #define LTEATR_V __PPCBIT(31) 762 #define LTEAR 0x0C0 /* Transfer error address register */ 763 #define LTECCR 0x0C4 /* Transfer error ECC register */ 764 #define LTECCR_SBCE __PPCBITS(12,15) 765 #define LTECCR_MBUE __PPCBITS(28,31) 766 #define LBCR 0x0D0 /* Configuration register */ 767 #define LCRR 0x0D4 /* Clock ratio register */ 768 769 #define FMR 0x0E0 /* Flash Mode Register */ 770 #define FMR_CWTO __PPCBITS(16,19) 771 #define FMR_BOOT __PPCBIT(20) 772 #define FMR_ECCM __PPCBIT(23) 773 #define FMR_AL __PPCBITS(26,27) 774 #define FMR_OP __PPCBITS(30,31) 775 #define FIR 0x0E4 /* Flash Instruction Register */ 776 #define FIR_OP0 __PPCBITS(0,3) 777 #define FIR_OP1 __PPCBITS(4,7) 778 #define FIR_OP2 __PPCBITS(8,11) 779 #define FIR_OP3 __PPCBITS(12,15) 780 #define FIR_OP4 __PPCBITS(16,19) 781 #define FIR_OP5 __PPCBITS(20,23) 782 #define FIR_OP6 __PPCBITS(24,27) 783 #define FIR_OP7 __PPCBITS(28,31) 784 #define FIR_OP_NOP 0 785 #define FIR_OP_CA 1 /* Issue current column address */ 786 #define FIR_OP_PA 2 /* Issue current block+page address */ 787 #define FIR_OP_UA 3 /* Issue user-defined address byte */ 788 #define FIR_OP_CM0 4 /* Issue command from FCR[CMD0] */ 789 #define FIR_OP_CM1 5 /* Issue command from FCR[CMD1] */ 790 #define FIR_OP_CM2 6 /* Issue command from FCR[CMD2] */ 791 #define FIR_OP_CM3 7 /* Issue command from FCR[CMD3] */ 792 #define FIR_OP_WB 8 /* Write FBCR bytes of data */ 793 #define FIR_OP_WS 9 /* Write one byte of data from MDR */ 794 #define FIR_OP_RB 10 /* Read FBCR bytes of data */ 795 #define FIR_OP_RS 11 /* Read one byte of data into MDR */ 796 #define FIR_OP_CW0 12 /* Wait for LFRB then FCR[CMD0] */ 797 #define FIR_OP_CW1 13 /* Wait for LFRB then FCR[CMD1] */ 798 #define FIR_OP_RBW 14 /* Wait for LFRB then read FBCR bytes */ 799 #define FIR_OP_RSW 15 /* Wait for LFRB then byte into MDR */ 800 #define FCR 0xE8 /* Flash Command Register */ 801 #define FCR_CMD0 __PPCBITS(0,7) 802 #define FCR_CMD1 __PPCBITS(8,15) 803 #define FCR_CMD2 __PPCBITS(16,23) 804 #define FCR_CMD3 __PPCBITS(24,31) 805 #define FBAR 0xEC /* Flash Block Address Register */ 806 #define FBAR_BLK __PPCBITS(8,31) 807 #define FPAR 0xF0 /* Flash Page Address Register */ 808 #define FPAR_S_PI __PPCBITS(17,21) /* Page Index */ 809 #define FPAR_S_MS __PPCBIT(22) /* Main(0)/Spare(1) */ 810 #define FPAR_S_CI __PPCBITS(23,31) /* Column Index */ 811 #define FPAR_L_PI __PPCBITS(14,19) /* Page Index */ 812 #define FPAR_L_MS __PPCBIT(20) /* Main(0)/Spare(1) */ 813 #define FPAR_L_CI __PPCBITS(21,31) /* Column Index */ 814 #define FBCR 0xF4 /* Flash Byte Count Register */ 815 #define FBCR_BC __PPCBITS(20,31) 816 #define FECC0 0x100 817 #define FECC_V __PPCBIT(0) 818 #define FECC_ECC __PPCBIT(8,31) 819 #define FECC1 0x104 820 #define FECC2 0x108 821 #define FECC3 0x10C 822 823 #define MXMR_RFEN __PPCBIT(1) /* Refresh enable */ 824 #define MXMR_OP __PPCBITS(2,3) /* Command opcode */ 825 #define MXMR_OP_NORMAL __SHIFTIN(0, MXMR_OP) /* Normal Operation */ 826 #define MXMR_OP_WRITE __SHIFTIN(1, MXMR_OP) /* Write to UPM memory */ 827 #define MXMR_OP_READ __SHIFTIN(2, MXMR_OP) /* Read from UPM memory */ 828 #define MXMR_OP_RUN __SHIFTIN(3, MXMR_OP) /* Run Pattern */ 829 #define MXMR_UWPL __PPCBIT(3) /* LUPWAIT is active low */ 830 #define MXMR_AM __PPCBITS(5,7) /* Address multiplex size */ 831 #define MXMR_DS __PPCBITS(8,9) /* Disable timer period */ 832 #define MXMR_DS_1CYCLE __SHIFTIN(0,MXMR_DS) 833 #define MXMR_DS_2CYCLE __SHIFTIN(1,MXMR_DS) 834 #define MXMR_DS_3CYCLE __SHIFTIN(2,MXMR_DS) 835 #define MXMR_DS_4CYCLE __SHIFTIN(3,MXMR_DS) 836 #define MXMR_G0CL __PPCBITS(10,12) /* General line 0 control */ 837 #define MXMR_G0CL_A12 __SHIFTIN(0,MXMR_G0CL) 838 #define MXMR_G0CL_A11 __SHIFTIN(1,MXMR_G0CL) 839 #define MXMR_G0CL_A10 __SHIFTIN(2,MXMR_G0CL) 840 #define MXMR_G0CL_A9 __SHIFTIN(3,MXMR_G0CL) 841 #define MXMR_G0CL_A8 __SHIFTIN(4,MXMR_G0CL) 842 #define MXMR_G0CL_A7 __SHIFTIN(5,MXMR_G0CL) 843 #define MXMR_G0CL_A6 __SHIFTIN(6,MXMR_G0CL) 844 #define MXMR_G0CL_A5 __SHIFTIN(7,MXMR_G0CL) 845 #define MXMR_GPL4 __PPCBIT(13) /* LGPL4 output line disable */ 846 #define MXMR_RLF __PPCBITS(14,17) /* Read loop field */ 847 #define MXMR_WLF __PPCBITS(18,21) /* Write loop field */ 848 #define MXMR_TLF __PPCBITS(22,25) /* Refresh loop field */ 849 #define MXMR_MAS __PPCBITS(26,31) /* Machine Address */ 850 851 #define MRTPR_PTP __PPCBITS(0,7) /* Refresh timers prescaler */ 852 853 #endif /* LBC_PRIVATE */ 854
Indexes created Sat Sep 20 22:09:52 GMT 2025