Home | History | Annotate | Line # | Download | only in inc 
      1 /*	$NetBSD: power_state.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2015 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #ifndef PP_POWERSTATE_H
     26 #define PP_POWERSTATE_H
     27 
     28 struct pp_hw_power_state {
     29 	unsigned int magic;
     30 };
     31 
     32 struct pp_power_state;
     33 
     34 
     35 #define PP_INVALID_POWER_STATE_ID (0)
     36 
     37 
     38 /*
     39  * An item of a list containing Power States.
     40  */
     41 
     42 struct PP_StateLinkedList {
     43 	struct pp_power_state *next;
     44 	struct pp_power_state *prev;
     45 };
     46 
     47 
     48 enum PP_StateUILabel {
     49 	PP_StateUILabel_None,
     50 	PP_StateUILabel_Battery,
     51 	PP_StateUILabel_MiddleLow,
     52 	PP_StateUILabel_Balanced,
     53 	PP_StateUILabel_MiddleHigh,
     54 	PP_StateUILabel_Performance,
     55 	PP_StateUILabel_BACO
     56 };
     57 
     58 enum PP_StateClassificationFlag {
     59 	PP_StateClassificationFlag_Boot                = 0x0001,
     60 	PP_StateClassificationFlag_Thermal             = 0x0002,
     61 	PP_StateClassificationFlag_LimitedPowerSource  = 0x0004,
     62 	PP_StateClassificationFlag_Rest                = 0x0008,
     63 	PP_StateClassificationFlag_Forced              = 0x0010,
     64 	PP_StateClassificationFlag_User3DPerformance   = 0x0020,
     65 	PP_StateClassificationFlag_User2DPerformance   = 0x0040,
     66 	PP_StateClassificationFlag_3DPerformance       = 0x0080,
     67 	PP_StateClassificationFlag_ACOverdriveTemplate   = 0x0100,
     68 	PP_StateClassificationFlag_Uvd                 = 0x0200,
     69 	PP_StateClassificationFlag_3DPerformanceLow    = 0x0400,
     70 	PP_StateClassificationFlag_ACPI                = 0x0800,
     71 	PP_StateClassificationFlag_HD2                 = 0x1000,
     72 	PP_StateClassificationFlag_UvdHD               = 0x2000,
     73 	PP_StateClassificationFlag_UvdSD               = 0x4000,
     74 	PP_StateClassificationFlag_UserDCPerformance    = 0x8000,
     75 	PP_StateClassificationFlag_DCOverdriveTemplate   = 0x10000,
     76 	PP_StateClassificationFlag_BACO                  = 0x20000,
     77 	PP_StateClassificationFlag_LimitedPowerSource_2  = 0x40000,
     78 	PP_StateClassificationFlag_ULV                   = 0x80000,
     79 	PP_StateClassificationFlag_UvdMVC               = 0x100000,
     80 };
     81 
     82 typedef unsigned int PP_StateClassificationFlags;
     83 
     84 struct PP_StateClassificationBlock {
     85 	enum PP_StateUILabel         ui_label;
     86 	enum PP_StateClassificationFlag  flags;
     87 	int                          bios_index;
     88 	bool                      temporary_state;
     89 	bool                      to_be_deleted;
     90 };
     91 
     92 struct PP_StatePcieBlock {
     93 	unsigned int lanes;
     94 };
     95 
     96 enum PP_RefreshrateSource {
     97 	PP_RefreshrateSource_EDID,
     98 	PP_RefreshrateSource_Explicit
     99 };
    100 
    101 struct PP_StateDisplayBlock {
    102 	bool              disableFrameModulation;
    103 	bool              limitRefreshrate;
    104 	enum PP_RefreshrateSource refreshrateSource;
    105 	int                  explicitRefreshrate;
    106 	int                  edidRefreshrateIndex;
    107 	bool              enableVariBright;
    108 };
    109 
    110 struct PP_StateMemroyBlock {
    111 	bool              dllOff;
    112 	uint8_t                 m3arb;
    113 	uint8_t                 unused[3];
    114 };
    115 
    116 struct PP_StateSoftwareAlgorithmBlock {
    117 	bool disableLoadBalancing;
    118 	bool enableSleepForTimestamps;
    119 };
    120 
    121 #define PP_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
    122 
    123 /**
    124  * Type to hold a temperature range.
    125  */
    126 struct PP_TemperatureRange {
    127 	int min;
    128 	int max;
    129 	int edge_emergency_max;
    130 	int hotspot_min;
    131 	int hotspot_crit_max;
    132 	int hotspot_emergency_max;
    133 	int mem_min;
    134 	int mem_crit_max;
    135 	int mem_emergency_max;
    136 };
    137 
    138 struct PP_StateValidationBlock {
    139 	bool singleDisplayOnly;
    140 	bool disallowOnDC;
    141 	uint8_t supportedPowerLevels;
    142 };
    143 
    144 struct PP_UVD_CLOCKS {
    145 	uint32_t VCLK;
    146 	uint32_t DCLK;
    147 };
    148 
    149 /**
    150 * Structure to hold a PowerPlay Power State.
    151 */
    152 struct pp_power_state {
    153 	uint32_t                            id;
    154 	struct PP_StateLinkedList                  orderedList;
    155 	struct PP_StateLinkedList                  allStatesList;
    156 
    157 	struct PP_StateClassificationBlock         classification;
    158 	struct PP_StateValidationBlock             validation;
    159 	struct PP_StatePcieBlock                   pcie;
    160 	struct PP_StateDisplayBlock                display;
    161 	struct PP_StateMemroyBlock                 memory;
    162 	struct PP_TemperatureRange                 temperatures;
    163 	struct PP_StateSoftwareAlgorithmBlock      software;
    164 	struct PP_UVD_CLOCKS                       uvd_clocks;
    165 	struct pp_hw_power_state  hardware;
    166 };
    167 
    168 enum PP_MMProfilingState {
    169 	PP_MMProfilingState_NA = 0,
    170 	PP_MMProfilingState_Started,
    171 	PP_MMProfilingState_Stopped
    172 };
    173 
    174 struct pp_clock_engine_request {
    175 	unsigned long client_type;
    176 	unsigned long ctx_id;
    177 	uint64_t  context_handle;
    178 	unsigned long sclk;
    179 	unsigned long sclk_hard_min;
    180 	unsigned long mclk;
    181 	unsigned long iclk;
    182 	unsigned long evclk;
    183 	unsigned long ecclk;
    184 	unsigned long ecclk_hard_min;
    185 	unsigned long vclk;
    186 	unsigned long dclk;
    187 	unsigned long sclk_over_drive;
    188 	unsigned long mclk_over_drive;
    189 	unsigned long sclk_threshold;
    190 	unsigned long flag;
    191 	unsigned long vclk_ceiling;
    192 	unsigned long dclk_ceiling;
    193 	unsigned long num_cus;
    194 	unsigned long pm_flag;
    195 	enum PP_MMProfilingState mm_profiling_state;
    196 };
    197 
    198 #endif
    199