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      1 /*	$NetBSD: cik_regs.h,v 1.3 2021/12/18 23:44:59 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2014 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  */
     24 
     25 #ifndef CIK_REGS_H
     26 #define CIK_REGS_H
     27 
     28 /* if PTR32, these are the bases for scratch and lds */
     29 #define	PRIVATE_BASE(x)					((x) << 0) /* scratch */
     30 #define	SHARED_BASE(x)					((x) << 16) /* LDS */
     31 #define	PTR32						(1 << 0)
     32 #define	ALIGNMENT_MODE(x)				((x) << 2)
     33 #define	SH_MEM_ALIGNMENT_MODE_UNALIGNED			3
     34 #define	DEFAULT_MTYPE(x)				((x) << 4)
     35 #define	APE1_MTYPE(x)					((x) << 7)
     36 
     37 /* valid for both DEFAULT_MTYPE and APE1_MTYPE */
     38 #define	MTYPE_CACHED_NV					0
     39 #define	MTYPE_CACHED					1
     40 #define	MTYPE_NONCACHED					3
     41 
     42 #define	DEFAULT_CP_HQD_PERSISTENT_STATE			(0x33U << 8)
     43 #define	PRELOAD_REQ					(1 << 0)
     44 
     45 #define	MQD_CONTROL_PRIV_STATE_EN			(1U << 8)
     46 
     47 #define	DEFAULT_MIN_IB_AVAIL_SIZE			(3U << 20)
     48 
     49 #define	IB_ATC_EN					(1U << 23)
     50 
     51 #define	QUANTUM_EN					1U
     52 #define	QUANTUM_SCALE_1MS				(1U << 4)
     53 #define	QUANTUM_DURATION(x)				((x) << 8)
     54 
     55 #define	RPTR_BLOCK_SIZE(x)				((x) << 8)
     56 #define	MIN_AVAIL_SIZE(x)				((x) << 20)
     57 #define	DEFAULT_RPTR_BLOCK_SIZE				RPTR_BLOCK_SIZE(5)
     58 #define	DEFAULT_MIN_AVAIL_SIZE				MIN_AVAIL_SIZE(3)
     59 
     60 #define	PQ_ATC_EN					(1 << 23)
     61 #define	NO_UPDATE_RPTR					(1 << 27)
     62 
     63 #define	DOORBELL_OFFSET(x)				((x) << 2)
     64 #define	DOORBELL_EN					(1 << 30)
     65 
     66 #define	PRIV_STATE					(1 << 30)
     67 #define	KMD_QUEUE					(1 << 31)
     68 
     69 #define	AQL_ENABLE					1
     70 
     71 #define GRBM_GFX_INDEX					0x30800
     72 
     73 #endif
     74