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      1 /*	$NetBSD: pscreg.h,v 1.1 2026/06/27 13:28:35 rkujawa Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2026 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Radoslaw Kujawa and Robert Swindells.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _POWERPC_MPC5200_PSCREG_H_
     33 #define _POWERPC_MPC5200_PSCREG_H_
     34 
     35 /*
     36  * Programmable Serial Controller (PSC) registers
     37  */
     38 
     39 #define PSC_MR1		0x00	/* Mode Register 1 (8-bit, indexed) */
     40 #define PSC_MR2		0x00	/* Mode Register 2 (8-bit, indexed) */
     41 
     42 /*
     43  * Mode Register 1 (PSC_MR1) bits
     44  */
     45 #define MR1_RRTS	(1 << 7)	/* receiver request-to-send control */
     46 #define MR1_FFULL	(1 << 6)	/* RxRDY on FIFO full (vs not empty) */
     47 #define PSC_SR		0x04	/* Status Register (ro, 16-bit) */
     48 #define PSC_CSR		0x04	/* Clock Select Register (wo, 16-bit) */
     49 #define PSC_CR		0x08	/* Command Register (wo, 8-bit) */
     50 #define PSC_RB		0x0c	/* Rx Buffer (ro) */
     51 #define PSC_TB		0x0c	/* Tx Buffer (wo) */
     52 #define PSC_IPCR	0x10	/* Input Port Change Register (ro) */
     53 #define PSC_ACR		0x10	/* Auxiliary Control Register (wo) */
     54 #define PSC_ISR		0x14	/* Interrupt Status Register (ro, 16-bit) */
     55 #define PSC_IMR		0x14	/* Interrupt Mask Register (wo, 16-bit) */
     56 #define PSC_CTUR	0x18	/* Counter Timer Upper Register */
     57 #define PSC_CTLR	0x1c	/* Counter Timer Lower Register */
     58 #define PSC_SICR	0x40	/* Serial Interface Control Register */
     59 #define PSC_TFNUM	0x5c	/* Tx FIFO byte count */
     60 #define PSC_RFNUM	0x58	/* Rx FIFO byte count */
     61 #define PSC_TFSTAT	0x84	/* Tx FIFO Status */
     62 #define PSC_RFSTAT	0x64	/* Rx FIFO Status */
     63 
     64 #define PSC_NPORTS	0x100	/* size of one PSC register window */
     65 
     66 /*
     67  * Clock Select Register (PSC_CSR)
     68  */
     69 #define CSR_UART_CT	0xdd00	/* Rx/Tx clock = counter/timer (/32 prescale) */
     70 #define PSC_BAUD_PRESCALE	32
     71 
     72 /* Status Register (PSC_SR) bits. */
     73 #define SR_RB		__BIT(15)	/* received break */
     74 #define SR_FE		__BIT(14)	/* framing error */
     75 #define SR_PE		__BIT(13)	/* parity error */
     76 #define SR_ORERR	__BIT(12)	/* overrun error */
     77 #define SR_TXEMP	__BIT(11)	/* transmitter empty */
     78 #define SR_TXRDY	__BIT(10)	/* transmitter ready */
     79 #define SR_FFULL	__BIT(9)	/* receive FIFO full */
     80 #define SR_RXRDY	__BIT(8)	/* receiver ready */
     81 
     82 #define SR_RCV_MASK	(SR_RB | SR_FE | SR_PE | SR_ORERR | SR_RXRDY)
     83 
     84 /* Command Register (PSC_CR) bits. */
     85 #define CMD_RESET_MR	(1 << 4)
     86 #define CMD_RESET_RX	(2 << 4)
     87 #define CMD_RESET_TX	(3 << 4)
     88 #define CMD_RESET_ERR	(4 << 4)
     89 #define CMD_RESET_BRK	(5 << 4)
     90 #define CMD_START_BRK	(6 << 4)
     91 #define CMD_STOP_BRK	(7 << 4)
     92 #define CMD_TX_ENABLE	(1 << 2)
     93 #define CMD_TX_DISABLE	(2 << 2)
     94 #define CMD_RX_ENABLE	(1 << 0)
     95 #define CMD_RX_DISABLE	(2 << 0)
     96 
     97 /* Interrupt Status/Mask Register bits. */
     98 #define INT_IPC		__BIT(15)
     99 #define INT_ORERR	__BIT(12)
    100 #define INT_TXEMP	__BIT(11)
    101 #define INT_DB		__BIT(10)
    102 #define INT_RXRDY	__BIT(9)
    103 #define INT_TXRDY	__BIT(8)
    104 #define INT_ERROR	__BIT(6)
    105 
    106 #endif /* _POWERPC_MPC5200_PSCREG_H_ */
    107