1 /* $NetBSD: bcm2835_pwm.h,v 1.2 2017/10/19 05:45:37 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef BCM2835_PWMREG_H 30 #define BCM2835_PWMREG_H 31 32 #define PWM_CTL 0x00 33 #define PWM_CTL_MSEN2 __BIT(15) 34 #define PWM_CTL_USEF2 __BIT(13) 35 #define PWM_CTL_POLA2 __BIT(12) 36 #define PWM_CTL_SBIT2 __BIT(11) 37 #define PWM_CTL_RPTL2 __BIT(10) 38 #define PWM_CTL_MODE2 __BIT(9) 39 #define PWM_CTL_PWEN2 __BIT(8) 40 #define PWM_CTL_MSEN1 __BIT(7) 41 #define PWM_CTL_CLRF1 __BIT(6) 42 #define PWM_CTL_USEF1 __BIT(5) 43 #define PWM_CTL_POLA1 __BIT(4) 44 #define PWM_CTL_SBIT1 __BIT(3) 45 #define PWM_CTL_RPTL1 __BIT(2) 46 #define PWM_CTL_MODE1 __BIT(1) 47 #define PWM_CTL_PWEN1 __BIT(0) 48 #define PWM_CTL_WRITEZERO (__BITS(16,31)|__BIT(14)) 49 #define PWM_STA 0x04 50 #define PWM_STA_STA4 __BIT(12) 51 #define PWM_STA_STA3 __BIT(11) 52 #define PWM_STA_STA2 __BIT(10) 53 #define PWM_STA_STA1 __BIT(9) 54 #define PWM_STA_BERR __BIT(8) 55 #define PWM_STA_GAPO4 __BIT(7) 56 #define PWM_STA_GAPO3 __BIT(6) 57 #define PWM_STA_GAPO2 __BIT(5) 58 #define PWM_STA_GAPO1 __BIT(4) 59 #define PWM_STA_RERR1 __BIT(3) 60 #define PWM_STA_WERR1 __BIT(2) 61 #define PWM_STA_EMPT1 __BIT(1) 62 #define PWM_STA_FULL1 __BIT(0) 63 #define PWM_STA_WRITEZERO __BITS(13,31) 64 #define PWM_DMAC 0x08 65 #define PWM_DMAC_ENAB __BIT(31) 66 #define PWM_DMAC_PANIC __BITS(8,15) 67 #define PWM_DMAC_DREQ __BITS(0,7) 68 #define PWM_DMAC_WRITEZERO __BITS(16,30) 69 #define PWM_RNG1 0x10 70 #define PWM_DAT1 0x14 71 #define PWM_FIFO 0x18 72 #define PWM_RNG2 0x20 73 #define PWM_DAT2 0x24 74 75 struct bcm_pwm_channel; 76 77 struct bcm_pwm_channel *bcm_pwm_alloc(int num); 78 void bcm_pwm_free(struct bcm_pwm_channel *); 79 void bcm_pwm_control(struct bcm_pwm_channel *, uint32_t, uint32_t); 80 uint32_t bcm_pwm_status(struct bcm_pwm_channel *); 81 int bcm_pwm_write(struct bcm_pwm_channel *, uint32_t *, uint32_t *, int); 82 void bcm_pwm_set(struct bcm_pwm_channel *, uint32_t); 83 int bcm_pwm_flush(struct bcm_pwm_channel *); 84 void bcm_pwm_dma_enable(struct bcm_pwm_channel *, bool); 85 uint32_t bcm_pwm_dma_address(struct bcm_pwm_channel *); 86 87 #define PWM_CTL_MSEN PWM_CTL_MSEN1 88 #define PWM_CTL_USEF PWM_CTL_USEF1 89 #define PWM_CTL_RPTL PWM_CTL_RPTL1 90 #define PWM_CTL_MODE PWM_CTL_MODE1 91 #define PWM_CTL_PWEN PWM_CTL_PWEN1 92 93 #define PWM_STA_STA PWM_STA_STA1 94 #define PWM_STA_GAPO PWM_STA_GAPO1 95 #define PWM_STA_RERR PWM_STA_RERR1 96 #define PWM_STA_WERR PWM_STA_WERR1 97 #define PWM_STA_EMPT PWM_STA_EMPT1 98 #define PWM_STA_FULL PWM_STA_FULL1 99 100 101 #endif /* !BCM2835_PWMREG_H */ 102
Indexes created Tue Sep 23 14:10:03 GMT 2025