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      1 /*-
      2  * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
      3  * All rights reserved.
      4  *
      5  * This code is derived from software contributed to The NetBSD Foundation
      6  * by Matt Thomas of 3am Software Foundry.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     19  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     27  * POSSIBILITY OF SUCH DAMAGE.
     28  */
     29 
     30 #ifndef _MPC85XX_PIXISREG_H_
     31 #define _MPC85XX_PIXISREG_H_
     32 
     33 #define	PX_BASE		0xffdf0000
     34 
     35 #define	PX_ID		0x00	/* System ID register */
     36 #define	PX_VER		0x01	/* System version register */
     37 #define	PX_VER_ID	__BITS(4,7)
     38 #define	PX_VER_ID_GET(n) __SHIFTOUT((n), PX_VER_ID)
     39 #define	PX_VER_REV	__BITS(0,3)
     40 #define	PX_VER_REV_GET(n) __SHIFTOUT((n), PX_VER_ID)
     41 #define	PX_PVER		0x02	/* System version register */
     42 #define	PX_CSR		0x03	/* General control/status register */
     43 #define	PX_CSR_ASLEEP	__BIT(6)
     44 #define	PX_CSR_EVES	__BITS(2,3)
     45 #define	PX_CSR_EVES_GET(n)	__SHIFTOUT((n), PX_CSR_EVES)
     46 #define	PX_CSR_PASS	__BIT(1)
     47 #define	PX_CSR_FAIL	__BIT(0)
     48 #define	PX_RST		0x04	/* Reset control register */
     49 #define	PX_RST_ALL	__BIT(7) /* if set to 0 a full system reset is initiated */
     50 #define	PX_RST_PCIE1	__BIT(6) /* If 1: RST_PCIE1* is deasserted and the slot is out of reset. */
     51 #define	PX_RST_PCIE2	__BIT(5) /* If 1: RST_PCIE2* is deasserted and the slot is out of reset. */
     52 #define	PX_RST_PCIE3	__BIT(4) /* If 1: RST_PCIE3* is deasserted and the slot is out of reset. */
     53 #define	PX_RST_USB	__BIT(3) /* If 0: RST_USB3300 is deasserted and the devices are out of reset. */
     54 #define	PX_RST_PHY	__BIT(2) /* If 1: PHY_RST* is deasserted and the device is out of reset. */
     55 #define	PX_RST_LB	__BIT(1) /* If 1: LB_RST* is deasserted and the device is out of reset. */
     56 #define	PX_RST_GEN	__BIT(0) /* If 1: GEN_RST* is deasserted and the devices are out of reset. */
     57 #define	PX_RST2		0x05	/* Reset control register 2 */
     58 #define	PX_RST2_SGMII	__BIT(1) /* If 1: RST_SGMII_SLOT* is deasserted and the device is out of reset. */
     59 #define	PX_RST2_PCI	__BIT(0) /* If 1: RST_PCI_SLOT* is deasserted and the devices are out of reset. */
     60 #define	PX_AUX1		0x06	/* Auxiliary 1 register */
     61 #define	PX_SPD		0x07	/* Speed register */
     62 #define	PX_SPD_SYSCLK	__BITS(0,2)
     63 #define	PX_SPD_SYSCLK_GET(n)	__SHIFTOUT((n), PX_SPD_SYSCLK)
     64 #define	PX_SPD_33MHZ	0
     65 #define	PX_SPD_40MHZ	1
     66 #define	PX_SPD_50MHZ	2
     67 #define	PX_SPD_66MHZ	3
     68 #define	PX_SPD_83MHZ	4
     69 #define	PX_SPD_100MHZ	5
     70 #define	PX_SPD_133MHZ	6
     71 #define	PX_SPD_166MHZ	7
     72 #define	PX_SPD_DDRCLK	__BITS(3,5)
     73 #define	PX_SPD_DDRCLK_GET(n)	__SHIFTOUT((n), PX_SPD_DDRCLK)
     74 #define	PX_AUX2		0x08	/* Auxiliary 2 register */
     75 #define	PX_CSR2		0x09	/* General control/status register 2 */
     76 #define PX_CSR2_MMC_8BITEN	__BIT(7)
     77 #define PX_CSR2_SDSEL_EN	__BIT(6)
     78 #define PX_CSR2_MMC_8BIT	__BIT(4)
     79 #define PX_CSR2_SDSEK		__BIT(3)
     80 #define	PX_VWATCH	0x0a	/* VELA watchdog register */
     81 #define	PX_LED		0x0b	/* LED data register */
     82 #define	PX_PWR		0x0c	/* Power status register */
     83 #define	PX_VCTRL	0x10	/* VELA control register */
     84 
     85 #endif /* !_MPC85XX_PIXISREG_H_ */
     86