| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LiveRegMatrix.cpp | 81 LiveInterval &VRegInterval, MCRegister PhysReg,
84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) {
106 << printReg(PhysReg, TRI) << ':');
108 VRM->assignVirt2Phys(VirtReg.reg(), PhysReg);
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) {
122 Register PhysReg = VRM->getPhys(VirtReg.reg());
124 << " from " << printReg(PhysReg, TRI) << ':');
127 foreachUnit(TRI, VirtReg, PhysReg,
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| RegisterClassInfo.cpp | 113 unsigned PhysReg = RawOrder[i];
115 if (Reserved.test(PhysReg))
117 uint8_t Cost = RegCosts[PhysReg];
120 if (CalleeSavedAliases[PhysReg] &&
121 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
122 // PhysReg aliases a CSR, save it for later.
123 CSRAlias.push_back(PhysReg);
127 RCI.Order[N++] = PhysReg;
136 unsigned PhysReg = CSRAlias[i];
137 uint8_t Cost = RegCosts[PhysReg];
[all...] |
| InterferenceCache.h | 44 /// of PhysReg in all basic blocks.
46 /// PhysReg - The register currently represented.
47 MCRegister PhysReg = 0;
68 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
90 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
105 PhysReg = MCRegister::NoRegister;
111 MCRegister getPhysReg() const { return PhysReg; }
119 /// valid - Return true if this is a valid entry for physReg.
122 /// reset - Initialize entry to represent physReg's aliases
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| ShrinkWrap.cpp | 282 Register PhysReg = MO.getReg();
283 if (!PhysReg)
285 assert(Register::isPhysicalRegister(PhysReg) && "Unallocated register?!");
291 UseOrDefCSR = (!MI.isCall() && PhysReg == SP) ||
292 RCI.getLastCalleeSavedAlias(PhysReg);
|
| VirtRegMap.cpp | 84 void VirtRegMap::assignVirt2Phys(Register virtReg, MCPhysReg physReg) {
85 assert(virtReg.isVirtual() && Register::isPhysicalRegister(physReg));
89 assert(!getRegInfo().isReserved(physReg) &&
90 "Attempt to map virtReg to a reserved physReg");
91 Virt2PhysMap[virtReg.id()] = physReg;
190 void addLiveInsForSubRanges(const LiveInterval &LI, MCRegister PhysReg) const;
279 MCRegister PhysReg) const {
318 MBB->addLiveIn(PhysReg, LaneMask);
333 // assigned PhysReg must be marked as live-in to those blocks.
334 Register PhysReg = VRM->getPhys(VirtReg)
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| RegAllocFast.cpp | 91 MCPhysReg PhysReg = 0; ///< Currently held here.
153 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
154 bool isPhysRegFree(MCPhysReg PhysReg) const;
156 /// Mark a physreg as used in this instruction.
157 void markRegUsedInInstr(MCPhysReg PhysReg) {
158 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
162 // Check if physreg is clobbered by instruction's regmask(s).
163 bool isClobberedByRegMasks(MCPhysReg PhysReg) const {
164 return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) {
165 return MachineOperand::clobbersPhysReg(Mask, PhysReg);
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| RegAllocGreedy.cpp | 295 std::pair<Register /* evictor */, MCRegister /* physreg */>;
300 /// be mapped to the evictor Vreg and the PhysReg it was evicted from.
315 /// The Evictor vreg has evicted the Evictee vreg from Physreg.
316 /// \param PhysReg The physical register Evictee was evicted from.
319 void addEviction(MCRegister PhysReg, Register Evictor, Register Evictee) {
321 Evictees[Evictee].second = PhysReg;
324 /// Return the Evictor Vreg which evicted Evictee Vreg from PhysReg.
326 /// \return The Evictor vreg which evicted Evictee vreg from PhysReg. 0 if
327 /// nobody has evicted Evictee from PhysReg.
353 MCRegister PhysReg;
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIPreAllocateWWMRegs.cpp | 103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
104 if (!MRI->isPhysRegUsed(PhysReg) &&
105 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) {
106 Matrix->assign(LI, PhysReg);
107 assert(PhysReg != 0);
113 llvm_unreachable("physreg not found for WWM expression");
131 Register PhysReg = VRM->getPhys(VirtReg);
134 PhysReg = TRI->getSubReg(PhysReg, SubReg);
138 MO.setReg(PhysReg);
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| AMDGPUCallLowering.cpp | 62 void assignValueToReg(Register ValVReg, Register PhysReg,
71 if (TRI->isSGPRReg(MRI, PhysReg)) {
78 MIRBuilder.buildCopy(PhysReg, ExtReg);
79 MIB.addUse(PhysReg, RegState::Implicit);
105 void assignValueToReg(Register ValVReg, Register PhysReg,
107 markPhysRegUsed(PhysReg);
112 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
122 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
143 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
150 void markPhysRegUsed(unsigned PhysReg) override
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| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMCallLowering.cpp | 111 void assignValueToReg(Register ValVReg, Register PhysReg,
114 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
120 MIRBuilder.buildCopy(PhysReg, ExtReg);
121 MIB.addUse(PhysReg, RegState::Implicit);
282 void assignValueToReg(Register ValVReg, Register PhysReg,
285 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
293 markPhysRegUsed(PhysReg);
295 MIRBuilder.buildCopy(ValVReg, PhysReg);
302 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg);
346 virtual void markPhysRegUsed(unsigned PhysReg) = 0
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| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 42 Register PhysReg = VRM->getPhys(MO.getReg());
43 if (SystemZ::GR32BitRegClass.contains(PhysReg))
45 assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
110 Register PhysReg = Register::isPhysicalRegister(Reg)
113 if (PhysReg) {
115 PhysReg = getSubReg(PhysReg, MO->getSubReg());
117 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
119 if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg)
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| SystemZInstrInfo.cpp | 1201 Register PhysReg = Register::isVirtualRegister(Reg)
1204 if (!PhysReg ||
1205 !(SystemZ::FP32BitRegClass.contains(PhysReg) ||
1206 SystemZ::FP64BitRegClass.contains(PhysReg) ||
1207 SystemZ::VF128BitRegClass.contains(PhysReg)))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86CallLowering.cpp | 107 void assignValueToReg(Register ValVReg, Register PhysReg,
109 MIB.addUse(PhysReg, RegState::Implicit);
111 MIRBuilder.buildCopy(PhysReg, ExtReg);
198 void assignValueToReg(Register ValVReg, Register PhysReg,
200 markPhysRegUsed(PhysReg);
201 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
207 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
217 void markPhysRegUsed(unsigned PhysReg) override {
218 MIRBuilder.getMRI()->addLiveIn(PhysReg);
219 MIRBuilder.getMBB().addLiveIn(PhysReg);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 207 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
210 if (PhysReg.first == SP)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64CallLowering.cpp | 154 void assignValueToReg(Register ValVReg, Register PhysReg,
156 markPhysRegUsed(PhysReg);
157 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
192 virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
199 void markPhysRegUsed(MCRegister PhysReg) override {
200 MIRBuilder.getMRI()->addLiveIn(PhysReg);
201 MIRBuilder.getMBB().addLiveIn(PhysReg);
210 void markPhysRegUsed(MCRegister PhysReg) override {
211 MIB.addDef(PhysReg, RegState::Implicit);
224 void markPhysRegUsed(MCRegister PhysReg) override {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsCallLowering.cpp | 109 virtual void markPhysRegUsed(unsigned PhysReg) {
110 MIRBuilder.getMRI()->addLiveIn(PhysReg);
111 MIRBuilder.getMBB().addLiveIn(PhysReg);
128 void markPhysRegUsed(unsigned PhysReg) override {
129 MIB.addDef(PhysReg, RegState::Implicit);
140 Register PhysReg = VA.getLocReg();
141 if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
146 auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1)));
147 auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 1 : 0)))
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 103 MCPhysReg PhysReg;
106 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
107 : PhysReg(PhysReg), LaneMask(LaneMask) {}
367 void addLiveIn(MCRegister PhysReg,
369 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
383 /// Add PhysReg as live in to this block, and ensure that there is a copy of
384 /// PhysReg to a virtual register of class RC. Return the virtual register
385 /// that is a copy of the live in PhysReg.
386 Register addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC)
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