1 /* $NetBSD: mpt_mpilib.h,v 1.6 2024/02/10 18:43:52 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 by LSI Logic Corporation 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice immediately at the beginning of the file, without modification, 11 * this list of conditions, and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * 28 * Name: MPI_TYPE.H 29 * Title: MPI Basic type definitions 30 * Creation Date: June 6, 2000 31 * 32 * MPI Version: 01.02.01 33 * 34 * Version History 35 * --------------- 36 * 37 * Date Version Description 38 * -------- -------- ------------------------------------------------------ 39 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 40 * 06-06-00 01.00.01 Update version number for 1.0 release. 41 * 11-02-00 01.01.01 Original release for post 1.0 work 42 * 02-20-01 01.01.02 Added define and ifdef for MPI_POINTER. 43 * 08-08-01 01.02.01 Original release for v1.2 work. 44 * -------------------------------------------------------------------------- 45 */ 46 47 #ifndef MPI_TYPE_H 48 #define MPI_TYPE_H 49 50 51 /******************************************************************************* 52 * Define MPI_POINTER if it hasn't already been defined. By default MPI_POINTER 53 * is defined to be a near pointer. MPI_POINTER can be defined as a far pointer 54 * by defining MPI_POINTER as "far *" before this header file is included. 55 */ 56 #ifndef MPI_POINTER 57 #define MPI_POINTER * 58 #endif 59 60 61 /***************************************************************************** 62 * 63 * B a s i c T y p e s 64 * 65 *****************************************************************************/ 66 67 #ifdef __NetBSD__ 68 typedef int8_t S8; 69 typedef uint8_t U8; 70 typedef int16_t S16; 71 typedef uint16_t U16; 72 typedef int32_t S32; 73 typedef uint32_t U32; 74 #else /* ! __NetBSD__ */ 75 typedef signed char S8; 76 typedef unsigned char U8; 77 typedef signed short S16; 78 typedef unsigned short U16; 79 80 #if defined(unix) || defined(__arm) || defined(ALPHA) || defined(__GNUC__) 81 82 typedef signed int S32; 83 typedef unsigned int U32; 84 85 #else 86 87 typedef signed long S32; 88 typedef unsigned long U32; 89 90 #endif 91 #endif /* __NetBSD__ */ 92 93 94 typedef struct _S64 95 { 96 U32 Low; 97 S32 High; 98 } S64; 99 100 typedef struct _U64 101 { 102 U32 Low; 103 U32 High; 104 } U64; 105 106 107 /****************************************************************************/ 108 /* Pointers */ 109 /****************************************************************************/ 110 111 typedef S8 *PS8; 112 typedef U8 *PU8; 113 typedef S16 *PS16; 114 typedef U16 *PU16; 115 typedef S32 *PS32; 116 typedef U32 *PU32; 117 typedef S64 *PS64; 118 typedef U64 *PU64; 119 120 121 #endif 122 123 124 /* 125 * Copyright (c) 2000, 2001 by LSI Logic Corporation 126 * 127 * Redistribution and use in source and binary forms, with or without 128 * modification, are permitted provided that the following conditions 129 * are met: 130 * 1. Redistributions of source code must retain the above copyright 131 * notice immediately at the beginning of the file, without modification, 132 * this list of conditions, and the following disclaimer. 133 * 2. The name of the author may not be used to endorse or promote products 134 * derived from this software without specific prior written permission. 135 * 136 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 137 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 138 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 139 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 140 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 141 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 142 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 143 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 144 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 145 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 146 * SUCH DAMAGE. 147 * 148 * 149 * Name: MPI.H 150 * Title: MPI Message independent structures and definitions 151 * Creation Date: July 27, 2000 152 * 153 * MPI Version: 01.02.03 154 * 155 * Version History 156 * --------------- 157 * 158 * Date Version Description 159 * -------- -------- ------------------------------------------------------ 160 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 161 * 05-24-00 00.10.02 Added MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH definition. 162 * 06-06-00 01.00.01 Update MPI_VERSION_MAJOR and MPI_VERSION_MINOR. 163 * 06-22-00 01.00.02 Added MPI_IOCSTATUS_LAN_ definitions. 164 * Removed LAN_SUSPEND function definition. 165 * Added MPI_MSGFLAGS_CONTINUATION_REPLY definition. 166 * 06-30-00 01.00.03 Added MPI_CONTEXT_REPLY_TYPE_LAN definition. 167 * Added MPI_GET/SET_CONTEXT_REPLY_TYPE macros. 168 * 07-27-00 01.00.04 Added MPI_FAULT_ definitions. 169 * Removed MPI_IOCSTATUS_MSG/DATA_XFER_ERROR definitions. 170 * Added MPI_IOCSTATUS_INTERNAL_ERROR definition. 171 * Added MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH. 172 * 11-02-00 01.01.01 Original release for post 1.0 work. 173 * 12-04-00 01.01.02 Added new function codes. 174 * 01-09-01 01.01.03 Added more definitions to the system interface section 175 * Added MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT. 176 * 01-25-01 01.01.04 Changed MPI_VERSION_MINOR from 0x00 to 0x01. 177 * 02-20-01 01.01.05 Started using MPI_POINTER. 178 * Fixed value for MPI_DIAG_RW_ENABLE. 179 * Added defines for MPI_DIAG_PREVENT_IOC_BOOT and 180 * MPI_DIAG_CLEAR_FLASH_BAD_SIG. 181 * Obsoleted MPI_IOCSTATUS_TARGET_FC_ defines. 182 * 02-27-01 01.01.06 Removed MPI_HOST_INDEX_REGISTER define. 183 * Added function codes for RAID. 184 * 04-09-01 01.01.07 Added alternate define for MPI_DOORBELL_ACTIVE, 185 * MPI_DOORBELL_USED, to better match the spec. 186 * 08-08-01 01.02.01 Original release for v1.2 work. 187 * Changed MPI_VERSION_MINOR from 0x01 to 0x02. 188 * Added define MPI_FUNCTION_TOOLBOX. 189 * 09-28-01 01.02.02 New function code MPI_SCSI_ENCLOSURE_PROCESSOR. 190 * 11-01-01 01.02.03 Changed name to MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR. 191 * -------------------------------------------------------------------------- 192 */ 193 194 #ifndef MPI_H 195 #define MPI_H 196 197 198 /***************************************************************************** 199 * 200 * M P I V e r s i o n D e f i n i t i o n s 201 * 202 *****************************************************************************/ 203 204 #define MPI_VERSION_MAJOR (0x01) 205 #define MPI_VERSION_MINOR (0x02) 206 #define MPI_VERSION ((MPI_VERSION_MAJOR << 8) | MPI_VERSION_MINOR) 207 208 /* Note: The major versions of 0xe0 through 0xff are reserved */ 209 210 /***************************************************************************** 211 * 212 * I O C S t a t e D e f i n i t i o n s 213 * 214 *****************************************************************************/ 215 216 #define MPI_IOC_STATE_RESET (0x00000000) 217 #define MPI_IOC_STATE_READY (0x10000000) 218 #define MPI_IOC_STATE_OPERATIONAL (0x20000000) 219 #define MPI_IOC_STATE_FAULT (0x40000000) 220 221 #define MPI_IOC_STATE_MASK (0xF0000000) 222 #define MPI_IOC_STATE_SHIFT (28) 223 224 /* Fault state codes (product independent range 0x8000-0xFFFF) */ 225 226 #define MPI_FAULT_REQUEST_MESSAGE_PCI_PARITY_ERROR (0x8111) 227 #define MPI_FAULT_REQUEST_MESSAGE_PCI_BUS_FAULT (0x8112) 228 #define MPI_FAULT_REPLY_MESSAGE_PCI_PARITY_ERROR (0x8113) 229 #define MPI_FAULT_REPLY_MESSAGE_PCI_BUS_FAULT (0x8114) 230 #define MPI_FAULT_DATA_SEND_PCI_PARITY_ERROR (0x8115) 231 #define MPI_FAULT_DATA_SEND_PCI_BUS_FAULT (0x8116) 232 #define MPI_FAULT_DATA_RECEIVE_PCI_PARITY_ERROR (0x8117) 233 #define MPI_FAULT_DATA_RECEIVE_PCI_BUS_FAULT (0x8118) 234 235 236 /***************************************************************************** 237 * 238 * P C I S y s t e m I n t e r f a c e R e g i s t e r s 239 * 240 *****************************************************************************/ 241 242 /* S y s t e m D o o r b e l l */ 243 #define MPI_DOORBELL_OFFSET (0x00000000) 244 #define MPI_DOORBELL_ACTIVE (0x08000000) /* DoorbellUsed */ 245 #define MPI_DOORBELL_USED (MPI_DOORBELL_ACTIVE) 246 #define MPI_DOORBELL_ACTIVE_SHIFT (27) 247 #define MPI_DOORBELL_WHO_INIT_MASK (0x07000000) 248 #define MPI_DOORBELL_WHO_INIT_SHIFT (24) 249 #define MPI_DOORBELL_FUNCTION_MASK (0xFF000000) 250 #define MPI_DOORBELL_FUNCTION_SHIFT (24) 251 #define MPI_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 252 #define MPI_DOORBELL_ADD_DWORDS_SHIFT (16) 253 #define MPI_DOORBELL_DATA_MASK (0x0000FFFF) 254 255 256 #define MPI_WRITE_SEQUENCE_OFFSET (0x00000004) 257 #define MPI_WRSEQ_KEY_VALUE_MASK (0x0000000F) 258 #define MPI_WRSEQ_1ST_KEY_VALUE (0x04) 259 #define MPI_WRSEQ_2ND_KEY_VALUE (0x0B) 260 #define MPI_WRSEQ_3RD_KEY_VALUE (0x02) 261 #define MPI_WRSEQ_4TH_KEY_VALUE (0x07) 262 #define MPI_WRSEQ_5TH_KEY_VALUE (0x0D) 263 264 #define MPI_DIAGNOSTIC_OFFSET (0x00000008) 265 #define MPI_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 266 #define MPI_DIAG_PREVENT_IOC_BOOT (0x00000200) 267 #define MPI_DIAG_DRWE (0x00000080) 268 #define MPI_DIAG_FLASH_BAD_SIG (0x00000040) 269 #define MPI_DIAG_RESET_HISTORY (0x00000020) 270 #define MPI_DIAG_RW_ENABLE (0x00000010) 271 #define MPI_DIAG_RESET_ADAPTER (0x00000004) 272 #define MPI_DIAG_DISABLE_ARM (0x00000002) 273 #define MPI_DIAG_MEM_ENABLE (0x00000001) 274 275 #define MPI_TEST_BASE_ADDRESS_OFFSET (0x0000000C) 276 277 #define MPI_DIAG_RW_DATA_OFFSET (0x00000010) 278 279 #define MPI_DIAG_RW_ADDRESS_OFFSET (0x00000014) 280 281 #define MPI_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 282 #define MPI_HIS_IOP_DOORBELL_STATUS (0x80000000) 283 #define MPI_HIS_REPLY_MESSAGE_INTERRUPT (0x00000008) 284 #define MPI_HIS_DOORBELL_INTERRUPT (0x00000001) 285 286 #define MPI_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 287 #define MPI_HIM_RIM (0x00000008) 288 #define MPI_HIM_DIM (0x00000001) 289 290 #define MPI_REQUEST_QUEUE_OFFSET (0x00000040) 291 #define MPI_REQUEST_POST_FIFO_OFFSET (0x00000040) 292 293 #define MPI_REPLY_QUEUE_OFFSET (0x00000044) 294 #define MPI_REPLY_POST_FIFO_OFFSET (0x00000044) 295 #define MPI_REPLY_FREE_FIFO_OFFSET (0x00000044) 296 297 298 299 /***************************************************************************** 300 * 301 * M e s s a g e F r a m e D e s c r i p t o r s 302 * 303 *****************************************************************************/ 304 305 #define MPI_REQ_MF_DESCRIPTOR_NB_MASK (0x00000003) 306 #define MPI_REQ_MF_DESCRIPTOR_F_BIT (0x00000004) 307 #define MPI_REQ_MF_DESCRIPTOR_ADDRESS_MASK (0xFFFFFFF8) 308 309 #define MPI_ADDRESS_REPLY_A_BIT (0x80000000) 310 #define MPI_ADDRESS_REPLY_ADDRESS_MASK (0x7FFFFFFF) 311 312 #define MPI_CONTEXT_REPLY_A_BIT (0x80000000) 313 #define MPI_CONTEXT_REPLY_TYPE_MASK (0x60000000) 314 #define MPI_CONTEXT_REPLY_TYPE_SCSI_INIT (0x00) 315 #define MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET (0x01) 316 #define MPI_CONTEXT_REPLY_TYPE_LAN (0x02) 317 #define MPI_CONTEXT_REPLY_TYPE_SHIFT (29) 318 #define MPI_CONTEXT_REPLY_CONTEXT_MASK (0x1FFFFFFF) 319 320 321 /****************************************************************************/ 322 /* Context Reply macros */ 323 /****************************************************************************/ 324 325 #define MPI_GET_CONTEXT_REPLY_TYPE(x) (((x) & MPI_CONTEXT_REPLY_TYPE_MASK) \ 326 >> MPI_CONTEXT_REPLY_TYPE_SHIFT) 327 328 #define MPI_SET_CONTEXT_REPLY_TYPE(x, typ) \ 329 ((x) = ((x) & ~MPI_CONTEXT_REPLY_TYPE_MASK) | \ 330 (((typ) << MPI_CONTEXT_REPLY_TYPE_SHIFT) & \ 331 MPI_CONTEXT_REPLY_TYPE_MASK)) 332 333 334 /***************************************************************************** 335 * 336 * M e s s a g e F u n c t i o n s 337 * 0x80 -> 0x8F reserved for private message use per product 338 * 339 * 340 *****************************************************************************/ 341 342 #define MPI_FUNCTION_SCSI_IO_REQUEST (0x00) 343 #define MPI_FUNCTION_SCSI_TASK_MGMT (0x01) 344 #define MPI_FUNCTION_IOC_INIT (0x02) 345 #define MPI_FUNCTION_IOC_FACTS (0x03) 346 #define MPI_FUNCTION_CONFIG (0x04) 347 #define MPI_FUNCTION_PORT_FACTS (0x05) 348 #define MPI_FUNCTION_PORT_ENABLE (0x06) 349 #define MPI_FUNCTION_EVENT_NOTIFICATION (0x07) 350 #define MPI_FUNCTION_EVENT_ACK (0x08) 351 #define MPI_FUNCTION_FW_DOWNLOAD (0x09) 352 #define MPI_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A) 353 #define MPI_FUNCTION_TARGET_ASSIST (0x0B) 354 #define MPI_FUNCTION_TARGET_STATUS_SEND (0x0C) 355 #define MPI_FUNCTION_TARGET_MODE_ABORT (0x0D) 356 #define MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC (0x0E) /* obsolete name */ 357 #define MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC (0x0F) /* obsolete name */ 358 #define MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC (0x10) /* obsolete name */ 359 #define MPI_FUNCTION_TARGET_FC_ABORT (0x11) /* obsolete name */ 360 #define MPI_FUNCTION_FC_LINK_SRVC_BUF_POST (0x0E) 361 #define MPI_FUNCTION_FC_LINK_SRVC_RSP (0x0F) 362 #define MPI_FUNCTION_FC_EX_LINK_SRVC_SEND (0x10) 363 #define MPI_FUNCTION_FC_ABORT (0x11) 364 #define MPI_FUNCTION_FW_UPLOAD (0x12) 365 #define MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND (0x13) 366 #define MPI_FUNCTION_FC_PRIMITIVE_SEND (0x14) 367 368 #define MPI_FUNCTION_RAID_ACTION (0x15) 369 #define MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 370 371 #define MPI_FUNCTION_TOOLBOX (0x17) 372 373 #define MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 374 375 #define MPI_FUNCTION_LAN_SEND (0x20) 376 #define MPI_FUNCTION_LAN_RECEIVE (0x21) 377 #define MPI_FUNCTION_LAN_RESET (0x22) 378 379 #define MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 380 #define MPI_FUNCTION_IO_UNIT_RESET (0x41) 381 #define MPI_FUNCTION_HANDSHAKE (0x42) 382 #define MPI_FUNCTION_REPLY_FRAME_REMOVAL (0x43) 383 384 385 386 /***************************************************************************** 387 * 388 * S c a t t e r G a t h e r E l e m e n t s 389 * 390 *****************************************************************************/ 391 392 /****************************************************************************/ 393 /* Simple element structures */ 394 /****************************************************************************/ 395 396 typedef struct _SGE_SIMPLE32 397 { 398 U32 FlagsLength; 399 U32 Address; 400 } SGE_SIMPLE32, MPI_POINTER PTR_SGE_SIMPLE32, 401 SGESimple32_t, MPI_POINTER pSGESimple32_t; 402 403 typedef struct _SGE_SIMPLE64 404 { 405 U32 FlagsLength; 406 U64 Address; 407 } SGE_SIMPLE64, MPI_POINTER PTR_SGE_SIMPLE64, 408 SGESimple64_t, MPI_POINTER pSGESimple64_t; 409 410 typedef struct _SGE_SIMPLE_UNION 411 { 412 U32 FlagsLength; 413 union 414 { 415 U32 Address32; 416 U64 Address64; 417 } _u; 418 } SGESimpleUnion_t, MPI_POINTER pSGESimpleUnion_t, 419 SGE_SIMPLE_UNION, MPI_POINTER PTR_SGE_SIMPLE_UNION; 420 421 /****************************************************************************/ 422 /* Chain element structures */ 423 /****************************************************************************/ 424 425 typedef struct _SGE_CHAIN32 426 { 427 U16 Length; 428 U8 NextChainOffset; 429 U8 Flags; 430 U32 Address; 431 } SGE_CHAIN32, MPI_POINTER PTR_SGE_CHAIN32, 432 SGEChain32_t, MPI_POINTER pSGEChain32_t; 433 434 typedef struct _SGE_CHAIN64 435 { 436 U16 Length; 437 U8 NextChainOffset; 438 U8 Flags; 439 U64 Address; 440 } SGE_CHAIN64, MPI_POINTER PTR_SGE_CHAIN64, 441 SGEChain64_t, MPI_POINTER pSGEChain64_t; 442 443 typedef struct _SGE_CHAIN_UNION 444 { 445 U16 Length; 446 U8 NextChainOffset; 447 U8 Flags; 448 union 449 { 450 U32 Address32; 451 U64 Address64; 452 } _u; 453 } SGE_CHAIN_UNION, MPI_POINTER PTR_SGE_CHAIN_UNION, 454 SGEChainUnion_t, MPI_POINTER pSGEChainUnion_t; 455 456 /****************************************************************************/ 457 /* Transaction Context element */ 458 /****************************************************************************/ 459 460 typedef struct _SGE_TRANSACTION32 461 { 462 U8 Reserved; 463 U8 ContextSize; 464 U8 DetailsLength; 465 U8 Flags; 466 U32 TransactionContext[1]; 467 U32 TransactionDetails[1]; 468 } SGE_TRANSACTION32, MPI_POINTER PTR_SGE_TRANSACTION32, 469 SGETransaction32_t, MPI_POINTER pSGETransaction32_t; 470 471 typedef struct _SGE_TRANSACTION64 472 { 473 U8 Reserved; 474 U8 ContextSize; 475 U8 DetailsLength; 476 U8 Flags; 477 U32 TransactionContext[2]; 478 U32 TransactionDetails[1]; 479 } SGE_TRANSACTION64, MPI_POINTER PTR_SGE_TRANSACTION64, 480 SGETransaction64_t, MPI_POINTER pSGETransaction64_t; 481 482 typedef struct _SGE_TRANSACTION96 483 { 484 U8 Reserved; 485 U8 ContextSize; 486 U8 DetailsLength; 487 U8 Flags; 488 U32 TransactionContext[3]; 489 U32 TransactionDetails[1]; 490 } SGE_TRANSACTION96, MPI_POINTER PTR_SGE_TRANSACTION96, 491 SGETransaction96_t, MPI_POINTER pSGETransaction96_t; 492 493 typedef struct _SGE_TRANSACTION128 494 { 495 U8 Reserved; 496 U8 ContextSize; 497 U8 DetailsLength; 498 U8 Flags; 499 U32 TransactionContext[4]; 500 U32 TransactionDetails[1]; 501 } SGE_TRANSACTION128, MPI_POINTER PTR_SGE_TRANSACTION128, 502 SGETransaction_t128, MPI_POINTER pSGETransaction_t128; 503 504 typedef struct _SGE_TRANSACTION_UNION 505 { 506 U8 Reserved; 507 U8 ContextSize; 508 U8 DetailsLength; 509 U8 Flags; 510 union 511 { 512 U32 TransactionContext32[1]; 513 U32 TransactionContext64[2]; 514 U32 TransactionContext96[3]; 515 U32 TransactionContext128[4]; 516 } _u; 517 U32 TransactionDetails[1]; 518 } SGE_TRANSACTION_UNION, MPI_POINTER PTR_SGE_TRANSACTION_UNION, 519 SGETransactionUnion_t, MPI_POINTER pSGETransactionUnion_t; 520 521 522 /****************************************************************************/ 523 /* SGE IO types union for IO SGL's */ 524 /****************************************************************************/ 525 526 typedef struct _SGE_IO_UNION 527 { 528 union 529 { 530 SGE_SIMPLE_UNION Simple; 531 SGE_CHAIN_UNION Chain; 532 } _u; 533 } SGE_IO_UNION, MPI_POINTER PTR_SGE_IO_UNION, 534 SGEIOUnion_t, MPI_POINTER pSGEIOUnion_t; 535 536 /****************************************************************************/ 537 /* SGE union for SGL's with Simple and Transaction elements */ 538 /****************************************************************************/ 539 540 typedef struct _SGE_TRANS_SIMPLE_UNION 541 { 542 union 543 { 544 SGE_SIMPLE_UNION Simple; 545 SGE_TRANSACTION_UNION Transaction; 546 } _u; 547 } SGE_TRANS_SIMPLE_UNION, MPI_POINTER PTR_SGE_TRANS_SIMPLE_UNION, 548 SGETransSimpleUnion_t, MPI_POINTER pSGETransSimpleUnion_t; 549 550 /****************************************************************************/ 551 /* All SGE types union */ 552 /****************************************************************************/ 553 554 typedef struct _SGE_MPI_UNION 555 { 556 union 557 { 558 SGE_SIMPLE_UNION Simple; 559 SGE_CHAIN_UNION Chain; 560 SGE_TRANSACTION_UNION Transaction; 561 } _u; 562 } SGE_MPI_UNION, MPI_POINTER PTR_SGE_MPI_UNION, 563 MPI_SGE_UNION_t, MPI_POINTER pMPI_SGE_UNION_t, 564 SGEAllUnion_t, MPI_POINTER pSGEAllUnion_t; 565 566 567 /****************************************************************************/ 568 /* SGE field definition and masks */ 569 /****************************************************************************/ 570 571 /* Flags field bit definitions */ 572 573 #define MPI_SGE_FLAGS_LAST_ELEMENT (0x80) 574 #define MPI_SGE_FLAGS_END_OF_BUFFER (0x40) 575 #define MPI_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 576 #define MPI_SGE_FLAGS_LOCAL_ADDRESS (0x08) 577 #define MPI_SGE_FLAGS_DIRECTION (0x04) 578 #define MPI_SGE_FLAGS_ADDRESS_SIZE (0x02) 579 #define MPI_SGE_FLAGS_END_OF_LIST (0x01) 580 581 #define MPI_SGE_FLAGS_SHIFT (24) 582 583 #define MPI_SGE_LENGTH_MASK (0x00FFFFFF) 584 #define MPI_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 585 586 /* Element Type */ 587 588 #define MPI_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 589 #define MPI_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 590 #define MPI_SGE_FLAGS_CHAIN_ELEMENT (0x30) 591 #define MPI_SGE_FLAGS_ELEMENT_MASK (0x30) 592 593 /* Address location */ 594 595 #define MPI_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 596 597 /* Direction */ 598 599 #define MPI_SGE_FLAGS_IOC_TO_HOST (0x00) 600 #define MPI_SGE_FLAGS_HOST_TO_IOC (0x04) 601 602 /* Address Size */ 603 604 #define MPI_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 605 #define MPI_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 606 607 /* Context Size */ 608 609 #define MPI_SGE_FLAGS_32_BIT_CONTEXT (0x00) 610 #define MPI_SGE_FLAGS_64_BIT_CONTEXT (0x02) 611 #define MPI_SGE_FLAGS_96_BIT_CONTEXT (0x04) 612 #define MPI_SGE_FLAGS_128_BIT_CONTEXT (0x06) 613 614 #define MPI_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 615 #define MPI_SGE_CHAIN_OFFSET_SHIFT (16) 616 617 618 /****************************************************************************/ 619 /* SGE operation Macros */ 620 /****************************************************************************/ 621 622 /* SIMPLE FlagsLength manipulations... */ 623 #define MPI_SGE_SET_FLAGS(f) ((U32)(f) << MPI_SGE_FLAGS_SHIFT) 624 #define MPI_SGE_GET_FLAGS(fl) (((fl) & ~MPI_SGE_LENGTH_MASK) >> MPI_SGE_FLAGS_SHIFT) 625 #define MPI_SGE_LENGTH(fl) ((fl) & MPI_SGE_LENGTH_MASK) 626 #define MPI_SGE_CHAIN_LENGTH(fl) ((fl) & MPI_SGE_CHAIN_LENGTH_MASK) 627 628 #define MPI_SGE_SET_FLAGS_LENGTH(f,l) (MPI_SGE_SET_FLAGS(f) | MPI_SGE_LENGTH(l)) 629 630 #define MPI_pSGE_GET_FLAGS(psg) MPI_SGE_GET_FLAGS((psg)->FlagsLength) 631 #define MPI_pSGE_GET_LENGTH(psg) MPI_SGE_LENGTH((psg)->FlagsLength) 632 #define MPI_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI_SGE_SET_FLAGS_LENGTH(f,l) 633 /* CAUTION - The following are READ-MODIFY-WRITE! */ 634 #define MPI_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI_SGE_SET_FLAGS(f) 635 #define MPI_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI_SGE_LENGTH(l) 636 637 #define MPI_GET_CHAIN_OFFSET(x) ((x&MPI_SGE_CHAIN_OFFSET_MASK)>>MPI_SGE_CHAIN_OFFSET_SHIFT) 638 639 640 641 /***************************************************************************** 642 * 643 * S t a n d a r d M e s s a g e S t r u c t u r e s 644 * 645 *****************************************************************************/ 646 647 /****************************************************************************/ 648 /* Standard message request header for all request messages */ 649 /****************************************************************************/ 650 651 typedef struct _MSG_REQUEST_HEADER 652 { 653 U8 Reserved[2]; /* function specific */ 654 U8 ChainOffset; 655 U8 Function; 656 U8 Reserved1[3]; /* function specific */ 657 U8 MsgFlags; 658 U32 MsgContext; 659 } MSG_REQUEST_HEADER, MPI_POINTER PTR_MSG_REQUEST_HEADER, 660 MPIHeader_t, MPI_POINTER pMPIHeader_t; 661 662 663 /****************************************************************************/ 664 /* Default Reply */ 665 /****************************************************************************/ 666 667 typedef struct _MSG_DEFAULT_REPLY 668 { 669 U8 Reserved[2]; /* function specific */ 670 U8 MsgLength; 671 U8 Function; 672 U8 Reserved1[3]; /* function specific */ 673 U8 MsgFlags; 674 U32 MsgContext; 675 U8 Reserved2[2]; /* function specific */ 676 U16 IOCStatus; 677 U32 IOCLogInfo; 678 } MSG_DEFAULT_REPLY, MPI_POINTER PTR_MSG_DEFAULT_REPLY, 679 MPIDefaultReply_t, MPI_POINTER pMPIDefaultReply_t; 680 681 682 /* MsgFlags definition for all replies */ 683 684 #define MPI_MSGFLAGS_CONTINUATION_REPLY (0x80) 685 686 687 /***************************************************************************** 688 * 689 * I O C S t a t u s V a l u e s 690 * 691 *****************************************************************************/ 692 693 /****************************************************************************/ 694 /* Common IOCStatus values for all replies */ 695 /****************************************************************************/ 696 697 #define MPI_IOCSTATUS_SUCCESS (0x0000) 698 #define MPI_IOCSTATUS_INVALID_FUNCTION (0x0001) 699 #define MPI_IOCSTATUS_BUSY (0x0002) 700 #define MPI_IOCSTATUS_INVALID_SGL (0x0003) 701 #define MPI_IOCSTATUS_INTERNAL_ERROR (0x0004) 702 #define MPI_IOCSTATUS_RESERVED (0x0005) 703 #define MPI_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 704 #define MPI_IOCSTATUS_INVALID_FIELD (0x0007) 705 #define MPI_IOCSTATUS_INVALID_STATE (0x0008) 706 707 /****************************************************************************/ 708 /* Config IOCStatus values */ 709 /****************************************************************************/ 710 711 #define MPI_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 712 #define MPI_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 713 #define MPI_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 714 #define MPI_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 715 #define MPI_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 716 #define MPI_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 717 718 /****************************************************************************/ 719 /* SCSIIO Reply (SPI & FCP) initiator values */ 720 /****************************************************************************/ 721 722 #define MPI_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 723 #define MPI_IOCSTATUS_SCSI_INVALID_BUS (0x0041) 724 #define MPI_IOCSTATUS_SCSI_INVALID_TARGETID (0x0042) 725 #define MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 726 #define MPI_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 727 #define MPI_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 728 #define MPI_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 729 #define MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 730 #define MPI_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 731 #define MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 732 #define MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 733 #define MPI_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 734 #define MPI_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 735 736 /****************************************************************************/ 737 /* SCSI (SPI & FCP) target values */ 738 /****************************************************************************/ 739 740 #define MPI_IOCSTATUS_TARGET_PRIORITY_IO (0x0060) 741 #define MPI_IOCSTATUS_TARGET_INVALID_PORT (0x0061) 742 #define MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX (0x0062) 743 #define MPI_IOCSTATUS_TARGET_ABORTED (0x0063) 744 #define MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 745 #define MPI_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 746 #define MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 747 #define MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT (0x006B) 748 749 /****************************************************************************/ 750 /* Additional FCP target values */ 751 /****************************************************************************/ 752 753 #define MPI_IOCSTATUS_TARGET_FC_ABORTED (0x0066) /* obsolete */ 754 #define MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID (0x0067) /* obsolete */ 755 #define MPI_IOCSTATUS_TARGET_FC_DID_INVALID (0x0068) /* obsolete */ 756 #define MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT (0x0069) /* obsolete */ 757 758 /****************************************************************************/ 759 /* Fibre Channel Direct Access values */ 760 /****************************************************************************/ 761 762 #define MPI_IOCSTATUS_FC_ABORTED (0x0066) 763 #define MPI_IOCSTATUS_FC_RX_ID_INVALID (0x0067) 764 #define MPI_IOCSTATUS_FC_DID_INVALID (0x0068) 765 #define MPI_IOCSTATUS_FC_NODE_LOGGED_OUT (0x0069) 766 767 /****************************************************************************/ 768 /* LAN values */ 769 /****************************************************************************/ 770 771 #define MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND (0x0080) 772 #define MPI_IOCSTATUS_LAN_DEVICE_FAILURE (0x0081) 773 #define MPI_IOCSTATUS_LAN_TRANSMIT_ERROR (0x0082) 774 #define MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED (0x0083) 775 #define MPI_IOCSTATUS_LAN_RECEIVE_ERROR (0x0084) 776 #define MPI_IOCSTATUS_LAN_RECEIVE_ABORTED (0x0085) 777 #define MPI_IOCSTATUS_LAN_PARTIAL_PACKET (0x0086) 778 #define MPI_IOCSTATUS_LAN_CANCELED (0x0087) 779 780 781 /****************************************************************************/ 782 /* IOCStatus flag to indicate that log info is available */ 783 /****************************************************************************/ 784 785 #define MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 786 #define MPI_IOCSTATUS_MASK (0x7FFF) 787 788 /****************************************************************************/ 789 /* LogInfo Types */ 790 /****************************************************************************/ 791 792 #define MPI_IOCLOGINFO_TYPE_MASK (0xF0000000) 793 #define MPI_IOCLOGINFO_TYPE_NONE (0x0) 794 #define MPI_IOCLOGINFO_TYPE_SCSI (0x1) 795 #define MPI_IOCLOGINFO_TYPE_FC (0x2) 796 #define MPI_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 797 798 799 #endif 800 801 /* 802 * Copyright (c) 2000, 2001 by LSI Logic Corporation 803 * 804 * Redistribution and use in source and binary forms, with or without 805 * modification, are permitted provided that the following conditions 806 * are met: 807 * 1. Redistributions of source code must retain the above copyright 808 * notice immediately at the beginning of the file, without modification, 809 * this list of conditions, and the following disclaimer. 810 * 2. The name of the author may not be used to endorse or promote products 811 * derived from this software without specific prior written permission. 812 * 813 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 814 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 815 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 816 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 817 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 818 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 819 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 820 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 821 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 822 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 823 * SUCH DAMAGE. 824 * 825 * 826 * Name: MPI_CNFG.H 827 * Title: MPI Config message, structures, and Pages 828 * Creation Date: July 27, 2000 829 * 830 * MPI Version: 01.02.05 831 * 832 * Version History 833 * --------------- 834 * 835 * Date Version Description 836 * -------- -------- ------------------------------------------------------ 837 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 838 * 06-06-00 01.00.01 Update version number for 1.0 release. 839 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 840 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 841 * fields to FC_DEVICE_0 page, updated the page version. 842 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 843 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 844 * and updated the page versions. 845 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 846 * page and updated the page version. 847 * Added Information field and _INFO_PARAMS_NEGOTIATED 848 * definitionto SCSI_DEVICE_0 page. 849 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 850 * page version. 851 * Added BucketsRemaining to LAN_1 page, redefined the 852 * state values, and updated the page version. 853 * Revised bus width definitions in SCSI_PORT_0, 854 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 855 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 856 * version. 857 * Moved FC_DEVICE_0 PageAddress description to spec. 858 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 859 * widths in IOC_0 page and updated the page version. 860 * 11-02-00 01.01.01 Original release for post 1.0 work 861 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 862 * Port Page 2, FC Port Page 4, FC Port Page 5 863 * 11-15-00 01.01.02 Interim changes to match proposals 864 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 865 * 12-05-00 01.01.04 Modified config page actions. 866 * 01-09-01 01.01.05 Added defines for page address formats. 867 * Data size for Manufacturing pages 2 and 3 no longer 868 * defined here. 869 * Io Unit Page 2 size is fixed at 4 adapters and some 870 * flags were changed. 871 * SCSI Port Page 2 Device Settings modified. 872 * New fields added to FC Port Page 0 and some flags 873 * cleaned up. 874 * Removed impedance flash from FC Port Page 1. 875 * Added FC Port pages 6 and 7. 876 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 877 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 878 * Added some LinkType defines for FcPortPage0. 879 * 02-20-01 01.01.08 Started using MPI_POINTER. 880 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 881 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 882 * Added definitions and structures for IOC Page 2 and 883 * RAID Volume Page 2. 884 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 885 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 886 * Added VendorId and ProductRevLevel fields to 887 * RAIDVOL2_IM_PHYS_ID struct. 888 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 889 * defines to make them compatible to MPI version 1.0. 890 * Added structure offset comments. 891 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 892 * removed some obsolete ones. 893 * Added IO Unit Page 3. 894 * Modified defines for Scsi Port Page 2. 895 * Modified RAID Volume Pages. 896 * 08-08-01 01.02.01 Original release for v1.2 work. 897 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 898 * Added defines for the SEP bits in RVP2 VolumeSettings. 899 * Modified the DeviceSettings field in RVP2 to use the 900 * proper structure. 901 * Added defines for SES, SAF-TE, and cross channel for 902 * IOCPage2 CapabilitiesFlags. 903 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 904 * Removed define for 905 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 906 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 907 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 908 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 909 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 910 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 911 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 912 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 913 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 914 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 915 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 916 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 917 * Added rejected bits to SCSI Device Page 0 Information. 918 * Increased size of ALPA array in FC Port Page 2 by one 919 * and removed a one byte reserved field. 920 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 921 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 922 * Added structures for Manufacturing Page 4, IO Unit 923 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 924 * RAID PhysDisk Page 0. 925 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 926 * Modified some of the new defines to make them 32 927 * character unique. 928 * Modified how variable length pages (arrays) are defined. 929 * Added generic defines for hot spare pools and RAID 930 * volume types. 931 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 932 * -------------------------------------------------------------------------- 933 */ 934 935 #ifndef MPI_CNFG_H 936 #define MPI_CNFG_H 937 938 939 /***************************************************************************** 940 * 941 * C o n f i g M e s s a g e a n d S t r u c t u r e s 942 * 943 *****************************************************************************/ 944 945 typedef struct _CONFIG_PAGE_HEADER 946 { 947 U8 PageVersion; /* 00h */ 948 U8 PageLength; /* 01h */ 949 U8 PageNumber; /* 02h */ 950 U8 PageType; /* 03h */ 951 } fCONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 952 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 953 954 typedef union _CONFIG_PAGE_HEADER_UNION 955 { 956 ConfigPageHeader_t Struct; 957 U8 Bytes[4]; 958 U16 Word16[2]; 959 U32 Word32; 960 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 961 fCONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 962 963 964 /**************************************************************************** 965 * PageType field values 966 ****************************************************************************/ 967 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 968 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 969 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 970 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 971 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 972 973 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 974 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 975 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 976 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 977 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 978 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 979 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 980 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 981 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 982 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 983 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 984 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 985 986 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 987 988 989 /**************************************************************************** 990 * PageAddress field values 991 ****************************************************************************/ 992 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 993 994 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 995 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 996 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 997 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 998 999 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 1000 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 1001 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 1002 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 1003 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 1004 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 1005 1006 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 1007 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 1008 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 1009 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 1010 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 1011 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 1012 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 1013 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 1014 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 1015 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 1016 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 1017 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 1018 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 1019 1020 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 1021 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 1022 1023 1024 1025 /**************************************************************************** 1026 * Config Request Message 1027 ****************************************************************************/ 1028 typedef struct _MSG_CONFIG 1029 { 1030 U8 Action; /* 00h */ 1031 U8 Reserved; /* 01h */ 1032 U8 ChainOffset; /* 02h */ 1033 U8 Function; /* 03h */ 1034 U8 Reserved1[3]; /* 04h */ 1035 U8 MsgFlags; /* 07h */ 1036 U32 MsgContext; /* 08h */ 1037 U8 Reserved2[8]; /* 0Ch */ 1038 fCONFIG_PAGE_HEADER Header; /* 14h */ 1039 U32 PageAddress; /* 18h */ 1040 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 1041 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 1042 Config_t, MPI_POINTER pConfig_t; 1043 1044 1045 /**************************************************************************** 1046 * Action field values 1047 ****************************************************************************/ 1048 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 1049 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 1050 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 1051 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 1052 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 1053 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 1054 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 1055 1056 1057 /* Config Reply Message */ 1058 typedef struct _MSG_CONFIG_REPLY 1059 { 1060 U8 Action; /* 00h */ 1061 U8 Reserved; /* 01h */ 1062 U8 MsgLength; /* 02h */ 1063 U8 Function; /* 03h */ 1064 U8 Reserved1[3]; /* 04h */ 1065 U8 MsgFlags; /* 07h */ 1066 U32 MsgContext; /* 08h */ 1067 U8 Reserved2[2]; /* 0Ch */ 1068 U16 IOCStatus; /* 0Eh */ 1069 U32 IOCLogInfo; /* 10h */ 1070 fCONFIG_PAGE_HEADER Header; /* 14h */ 1071 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 1072 ConfigReply_t, MPI_POINTER pConfigReply_t; 1073 1074 1075 1076 /***************************************************************************** 1077 * 1078 * C o n f i g u r a t i o n P a g e s 1079 * 1080 *****************************************************************************/ 1081 1082 /**************************************************************************** 1083 * Manufacturing Config pages 1084 ****************************************************************************/ 1085 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 1086 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 1087 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 1088 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 1089 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 1090 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 1091 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 1092 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 1093 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 1094 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 1095 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 1096 1097 typedef struct _CONFIG_PAGE_MANUFACTURING_0 1098 { 1099 fCONFIG_PAGE_HEADER Header; /* 00h */ 1100 U8 ChipName[16]; /* 04h */ 1101 U8 ChipRevision[8]; /* 14h */ 1102 U8 BoardName[16]; /* 1Ch */ 1103 U8 BoardAssembly[16]; /* 2Ch */ 1104 U8 BoardTracerNumber[16]; /* 3Ch */ 1105 1106 } fCONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 1107 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 1108 1109 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 1110 1111 1112 typedef struct _CONFIG_PAGE_MANUFACTURING_1 1113 { 1114 fCONFIG_PAGE_HEADER Header; /* 00h */ 1115 U8 VPD[256]; /* 04h */ 1116 } fCONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 1117 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 1118 1119 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 1120 1121 1122 typedef struct _MPI_CHIP_REVISION_ID 1123 { 1124 U16 DeviceID; /* 00h */ 1125 U8 PCIRevisionID; /* 02h */ 1126 U8 Reserved; /* 03h */ 1127 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 1128 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 1129 1130 1131 /* 1132 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1133 * one and check Header.PageLength at runtime. 1134 */ 1135 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 1136 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 1137 #endif 1138 1139 typedef struct _CONFIG_PAGE_MANUFACTURING_2 1140 { 1141 fCONFIG_PAGE_HEADER Header; /* 00h */ 1142 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 1143 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 1144 } fCONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 1145 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 1146 1147 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 1148 1149 1150 /* 1151 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1152 * one and check Header.PageLength at runtime. 1153 */ 1154 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 1155 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 1156 #endif 1157 1158 typedef struct _CONFIG_PAGE_MANUFACTURING_3 1159 { 1160 fCONFIG_PAGE_HEADER Header; /* 00h */ 1161 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 1162 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 1163 } fCONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 1164 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 1165 1166 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 1167 1168 1169 typedef struct _CONFIG_PAGE_MANUFACTURING_4 1170 { 1171 fCONFIG_PAGE_HEADER Header; /* 00h */ 1172 U32 Reserved1; /* 04h */ 1173 U8 InfoOffset0; /* 08h */ 1174 U8 InfoSize0; /* 09h */ 1175 U8 InfoOffset1; /* 0Ah */ 1176 U8 InfoSize1; /* 0Bh */ 1177 U8 InquirySize; /* 0Ch */ 1178 U8 Reserved2; /* 0Dh */ 1179 U16 Reserved3; /* 0Eh */ 1180 U8 InquiryData[56]; /* 10h */ 1181 U32 ISVolumeSettings; /* 48h */ 1182 U32 IMEVolumeSettings; /* 4Ch */ 1183 U32 IMVolumeSettings; /* 50h */ 1184 } fCONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 1185 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 1186 1187 #define MPI_MANUFACTURING4_PAGEVERSION (0x00) 1188 1189 1190 /**************************************************************************** 1191 * IO Unit Config Pages 1192 ****************************************************************************/ 1193 1194 typedef struct _CONFIG_PAGE_IO_UNIT_0 1195 { 1196 fCONFIG_PAGE_HEADER Header; /* 00h */ 1197 U64 UniqueValue; /* 04h */ 1198 } fCONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 1199 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 1200 1201 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 1202 1203 1204 typedef struct _CONFIG_PAGE_IO_UNIT_1 1205 { 1206 fCONFIG_PAGE_HEADER Header; /* 00h */ 1207 U32 Flags; /* 04h */ 1208 } fCONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 1209 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 1210 1211 #define MPI_IOUNITPAGE1_PAGEVERSION (0x00) 1212 1213 /* IO Unit Page 1 Flags defines */ 1214 1215 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 1216 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 1217 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 1218 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 1219 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 1220 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 1221 1222 1223 typedef struct _MPI_ADAPTER_INFO 1224 { 1225 U8 PciBusNumber; /* 00h */ 1226 U8 PciDeviceAndFunctionNumber; /* 01h */ 1227 U16 AdapterFlags; /* 02h */ 1228 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 1229 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 1230 1231 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1232 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1233 1234 typedef struct _CONFIG_PAGE_IO_UNIT_2 1235 { 1236 fCONFIG_PAGE_HEADER Header; /* 00h */ 1237 U32 Flags; /* 04h */ 1238 U32 BiosVersion; /* 08h */ 1239 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 1240 } fCONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 1241 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 1242 1243 #define MPI_IOUNITPAGE2_PAGEVERSION (0x00) 1244 1245 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 1246 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 1247 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 1248 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 1249 1250 1251 /* 1252 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1253 * one and check Header.PageLength at runtime. 1254 */ 1255 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 1256 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 1257 #endif 1258 1259 typedef struct _CONFIG_PAGE_IO_UNIT_3 1260 { 1261 fCONFIG_PAGE_HEADER Header; /* 00h */ 1262 U8 GPIOCount; /* 04h */ 1263 U8 Reserved1; /* 05h */ 1264 U16 Reserved2; /* 06h */ 1265 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 1266 } fCONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 1267 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 1268 1269 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 1270 1271 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 1272 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 1273 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 1274 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 1275 1276 1277 /**************************************************************************** 1278 * IOC Config Pages 1279 ****************************************************************************/ 1280 1281 typedef struct _CONFIG_PAGE_IOC_0 1282 { 1283 fCONFIG_PAGE_HEADER Header; /* 00h */ 1284 U32 TotalNVStore; /* 04h */ 1285 U32 FreeNVStore; /* 08h */ 1286 U16 VendorID; /* 0Ch */ 1287 U16 DeviceID; /* 0Eh */ 1288 U8 RevisionID; /* 10h */ 1289 U8 Reserved[3]; /* 11h */ 1290 U32 ClassCode; /* 14h */ 1291 U16 SubsystemVendorID; /* 18h */ 1292 U16 SubsystemID; /* 1Ah */ 1293 } fCONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 1294 IOCPage0_t, MPI_POINTER pIOCPage0_t; 1295 1296 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 1297 1298 1299 typedef struct _CONFIG_PAGE_IOC_1 1300 { 1301 fCONFIG_PAGE_HEADER Header; /* 00h */ 1302 U32 Flags; /* 04h */ 1303 U32 CoalescingTimeout; /* 08h */ 1304 U8 CoalescingDepth; /* 0Ch */ 1305 U8 Reserved[3]; /* 0Dh */ 1306 } fCONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 1307 IOCPage1_t, MPI_POINTER pIOCPage1_t; 1308 1309 #define MPI_IOCPAGE1_PAGEVERSION (0x00) 1310 1311 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 1312 1313 1314 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 1315 { 1316 U8 VolumeID; /* 00h */ 1317 U8 VolumeBus; /* 01h */ 1318 U8 VolumeIOC; /* 02h */ 1319 U8 VolumePageNumber; /* 03h */ 1320 U8 VolumeType; /* 04h */ 1321 U8 Reserved2; /* 05h */ 1322 U16 Reserved3; /* 06h */ 1323 } fCONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 1324 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 1325 1326 /* 1327 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1328 * one and check Header.PageLength at runtime. 1329 */ 1330 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 1331 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 1332 #endif 1333 1334 typedef struct _CONFIG_PAGE_IOC_2 1335 { 1336 fCONFIG_PAGE_HEADER Header; /* 00h */ 1337 U32 CapabilitiesFlags; /* 04h */ 1338 U8 NumActiveVolumes; /* 08h */ 1339 U8 MaxVolumes; /* 09h */ 1340 U8 NumActivePhysDisks; /* 0Ah */ 1341 U8 MaxPhysDisks; /* 0Bh */ 1342 fCONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 1343 } fCONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 1344 IOCPage2_t, MPI_POINTER pIOCPage2_t; 1345 1346 #define MPI_IOCPAGE2_PAGEVERSION (0x01) 1347 1348 /* IOC Page 2 Capabilities flags */ 1349 1350 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 1351 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 1352 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 1353 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 1354 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 1355 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 1356 1357 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 1358 1359 #define MPI_RAID_VOL_TYPE_IS (0x00) 1360 #define MPI_RAID_VOL_TYPE_IME (0x01) 1361 #define MPI_RAID_VOL_TYPE_IM (0x02) 1362 1363 1364 typedef struct _IOC_3_PHYS_DISK 1365 { 1366 U8 PhysDiskID; /* 00h */ 1367 U8 PhysDiskBus; /* 01h */ 1368 U8 PhysDiskIOC; /* 02h */ 1369 U8 PhysDiskNum; /* 03h */ 1370 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 1371 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 1372 1373 /* 1374 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1375 * one and check Header.PageLength at runtime. 1376 */ 1377 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 1378 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 1379 #endif 1380 1381 typedef struct _CONFIG_PAGE_IOC_3 1382 { 1383 fCONFIG_PAGE_HEADER Header; /* 00h */ 1384 U8 NumPhysDisks; /* 04h */ 1385 U8 Reserved1; /* 05h */ 1386 U16 Reserved2; /* 06h */ 1387 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 1388 } fCONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 1389 IOCPage3_t, MPI_POINTER pIOCPage3_t; 1390 1391 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 1392 1393 1394 typedef struct _IOC_4_SEP 1395 { 1396 U8 SEPTargetID; /* 00h */ 1397 U8 SEPBus; /* 01h */ 1398 U16 Reserved; /* 02h */ 1399 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 1400 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 1401 1402 /* 1403 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1404 * one and check Header.PageLength at runtime. 1405 */ 1406 #ifndef MPI_IOC_PAGE_4_SEP_MAX 1407 #define MPI_IOC_PAGE_4_SEP_MAX (1) 1408 #endif 1409 1410 typedef struct _CONFIG_PAGE_IOC_4 1411 { 1412 fCONFIG_PAGE_HEADER Header; /* 00h */ 1413 U8 ActiveSEP; /* 04h */ 1414 U8 MaxSEP; /* 05h */ 1415 U16 Reserved1; /* 06h */ 1416 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 1417 } fCONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 1418 IOCPage4_t, MPI_POINTER pIOCPage4_t; 1419 1420 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 1421 1422 1423 /**************************************************************************** 1424 * SCSI Port Config Pages 1425 ****************************************************************************/ 1426 1427 typedef struct _CONFIG_PAGE_SCSI_PORT_0 1428 { 1429 fCONFIG_PAGE_HEADER Header; /* 00h */ 1430 U32 Capabilities; /* 04h */ 1431 U32 PhysicalInterface; /* 08h */ 1432 } fCONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 1433 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 1434 1435 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01) 1436 1437 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 1438 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 1439 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 1440 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1441 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1442 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 1443 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 1444 1445 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 1446 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 1447 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 1448 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 1449 1450 1451 typedef struct _CONFIG_PAGE_SCSI_PORT_1 1452 { 1453 fCONFIG_PAGE_HEADER Header; /* 00h */ 1454 U32 Configuration; /* 04h */ 1455 U32 OnBusTimerValue; /* 08h */ 1456 } fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 1457 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 1458 1459 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02) 1460 1461 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 1462 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 1463 1464 1465 typedef struct _MPI_DEVICE_INFO 1466 { 1467 U8 Timeout; /* 00h */ 1468 U8 SyncFactor; /* 01h */ 1469 U16 DeviceFlags; /* 02h */ 1470 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 1471 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 1472 1473 typedef struct _CONFIG_PAGE_SCSI_PORT_2 1474 { 1475 fCONFIG_PAGE_HEADER Header; /* 00h */ 1476 U32 PortFlags; /* 04h */ 1477 U32 PortSettings; /* 08h */ 1478 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1479 } fCONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 1480 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 1481 1482 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01) 1483 1484 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 1485 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 1486 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1487 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 1488 1489 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 1490 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 1491 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 1492 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 1493 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 1494 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 1495 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 1496 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 1497 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 1498 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 1499 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 1500 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 1501 1502 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 1503 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 1504 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 1505 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 1506 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 1507 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 1508 1509 1510 /**************************************************************************** 1511 * SCSI Target Device Config Pages 1512 ****************************************************************************/ 1513 1514 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 1515 { 1516 fCONFIG_PAGE_HEADER Header; /* 00h */ 1517 U32 NegotiatedParameters; /* 04h */ 1518 U32 Information; /* 08h */ 1519 } fCONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 1520 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 1521 1522 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x02) 1523 1524 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 1525 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 1526 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 1527 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 1528 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 1529 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 1530 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 1531 1532 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 1533 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 1534 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 1535 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 1536 1537 1538 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 1539 { 1540 fCONFIG_PAGE_HEADER Header; /* 00h */ 1541 U32 RequestedParameters; /* 04h */ 1542 U32 Reserved; /* 08h */ 1543 U32 Configuration; /* 0Ch */ 1544 } fCONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 1545 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 1546 1547 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x03) 1548 1549 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 1550 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 1551 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 1552 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1553 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1554 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 1555 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 1556 1557 #define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK (0x00000003) 1558 #define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK (0x00000300) 1559 1560 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 1561 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 1562 1563 1564 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 1565 { 1566 fCONFIG_PAGE_HEADER Header; /* 00h */ 1567 U32 DomainValidation; /* 04h */ 1568 U32 ParityPipeSelect; /* 08h */ 1569 U32 DataPipeSelect; /* 0Ch */ 1570 } fCONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 1571 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 1572 1573 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x00) 1574 1575 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 1576 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 1577 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 1578 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 1579 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 1580 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 1581 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 1582 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 1583 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 1584 1585 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 1586 1587 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 1588 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 1589 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 1590 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 1591 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 1592 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 1593 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 1594 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 1595 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 1596 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 1597 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 1598 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 1599 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 1600 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 1601 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 1602 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 1603 1604 1605 /**************************************************************************** 1606 * FC Port Config Pages 1607 ****************************************************************************/ 1608 1609 typedef struct _CONFIG_PAGE_FC_PORT_0 1610 { 1611 fCONFIG_PAGE_HEADER Header; /* 00h */ 1612 U32 Flags; /* 04h */ 1613 U8 MPIPortNumber; /* 08h */ 1614 U8 LinkType; /* 09h */ 1615 U8 PortState; /* 0Ah */ 1616 U8 Reserved; /* 0Bh */ 1617 U32 PortIdentifier; /* 0Ch */ 1618 U64 WWNN; /* 10h */ 1619 U64 WWPN; /* 18h */ 1620 U32 SupportedServiceClass; /* 20h */ 1621 U32 SupportedSpeeds; /* 24h */ 1622 U32 CurrentSpeed; /* 28h */ 1623 U32 MaxFrameSize; /* 2Ch */ 1624 U64 FabricWWNN; /* 30h */ 1625 U64 FabricWWPN; /* 38h */ 1626 U32 DiscoveredPortsCount; /* 40h */ 1627 U32 MaxInitiators; /* 44h */ 1628 } fCONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 1629 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 1630 1631 #define MPI_FCPORTPAGE0_PAGEVERSION (0x01) 1632 1633 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 1634 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 1635 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 1636 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 1637 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 1638 1639 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 1640 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 1641 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000030) 1642 1643 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 1644 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1645 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1646 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1647 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1648 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1649 1650 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1651 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1652 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1653 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1654 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1655 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1656 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1657 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1658 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1659 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1660 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1661 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1662 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1663 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1664 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1665 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1666 1667 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1668 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1669 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1670 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1671 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1672 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1673 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1674 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1675 1676 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1677 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1678 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1679 1680 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1681 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1682 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1683 1684 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1685 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1686 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1687 1688 1689 typedef struct _CONFIG_PAGE_FC_PORT_1 1690 { 1691 fCONFIG_PAGE_HEADER Header; /* 00h */ 1692 U32 Flags; /* 04h */ 1693 U64 NoSEEPROMWWNN; /* 08h */ 1694 U64 NoSEEPROMWWPN; /* 10h */ 1695 U8 HardALPA; /* 18h */ 1696 U8 LinkConfig; /* 19h */ 1697 U8 TopologyConfig; /* 1Ah */ 1698 U8 Reserved; /* 1Bh */ 1699 } fCONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1700 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1701 1702 #define MPI_FCPORTPAGE1_PAGEVERSION (0x02) 1703 1704 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1705 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1706 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1707 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1708 1709 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1710 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1711 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1712 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1713 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1714 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1715 1716 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1717 1718 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1719 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1720 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1721 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1722 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1723 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1724 1725 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1726 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1727 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1728 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1729 1730 1731 typedef struct _CONFIG_PAGE_FC_PORT_2 1732 { 1733 fCONFIG_PAGE_HEADER Header; /* 00h */ 1734 U8 NumberActive; /* 04h */ 1735 U8 ALPA[127]; /* 05h */ 1736 } fCONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1737 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1738 1739 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1740 1741 1742 typedef struct _WWN_FORMAT 1743 { 1744 U64 WWNN; /* 00h */ 1745 U64 WWPN; /* 08h */ 1746 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1747 WWNFormat, MPI_POINTER pWWNFormat; 1748 1749 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1750 { 1751 WWN_FORMAT WWN; 1752 U32 Did; 1753 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1754 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1755 1756 typedef struct _FC_PORT_PERSISTENT 1757 { 1758 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1759 U8 TargetID; /* 10h */ 1760 U8 Bus; /* 11h */ 1761 U16 Flags; /* 12h */ 1762 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1763 PersistentData_t, MPI_POINTER pPersistentData_t; 1764 1765 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1766 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1767 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1768 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1769 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1770 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1771 1772 /* 1773 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1774 * one and check Header.PageLength at runtime. 1775 */ 1776 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1777 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1778 #endif 1779 1780 typedef struct _CONFIG_PAGE_FC_PORT_3 1781 { 1782 fCONFIG_PAGE_HEADER Header; /* 00h */ 1783 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1784 } fCONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1785 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1786 1787 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1788 1789 1790 typedef struct _CONFIG_PAGE_FC_PORT_4 1791 { 1792 fCONFIG_PAGE_HEADER Header; /* 00h */ 1793 U32 PortFlags; /* 04h */ 1794 U32 PortSettings; /* 08h */ 1795 } fCONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1796 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1797 1798 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1799 1800 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1801 1802 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1803 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1804 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1805 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1806 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1807 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1808 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1809 1810 1811 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1812 { 1813 U8 Flags; /* 00h */ 1814 U8 AliasAlpa; /* 01h */ 1815 U16 Reserved; /* 02h */ 1816 U64 AliasWWNN; /* 04h */ 1817 U64 AliasWWPN; /* 0Ch */ 1818 } fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1819 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1820 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1821 1822 /* 1823 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1824 * one and check Header.PageLength at runtime. 1825 */ 1826 #ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX 1827 #define MPI_FC_PORT_PAGE_5_ALIAS_MAX (1) 1828 #endif 1829 1830 typedef struct _CONFIG_PAGE_FC_PORT_5 1831 { 1832 fCONFIG_PAGE_HEADER Header; /* 00h */ 1833 fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX];/* 04h */ 1834 } fCONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1835 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1836 1837 #define MPI_FCPORTPAGE5_PAGEVERSION (0x00) 1838 1839 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID (0x01) 1840 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID (0x02) 1841 1842 1843 typedef struct _CONFIG_PAGE_FC_PORT_6 1844 { 1845 fCONFIG_PAGE_HEADER Header; /* 00h */ 1846 U32 Reserved; /* 04h */ 1847 U64 TimeSinceReset; /* 08h */ 1848 U64 TxFrames; /* 10h */ 1849 U64 RxFrames; /* 18h */ 1850 U64 TxWords; /* 20h */ 1851 U64 RxWords; /* 28h */ 1852 U64 LipCount; /* 30h */ 1853 U64 NosCount; /* 38h */ 1854 U64 ErrorFrames; /* 40h */ 1855 U64 DumpedFrames; /* 48h */ 1856 U64 LinkFailureCount; /* 50h */ 1857 U64 LossOfSyncCount; /* 58h */ 1858 U64 LossOfSignalCount; /* 60h */ 1859 U64 PrimativeSeqErrCount; /* 68h */ 1860 U64 InvalidTxWordCount; /* 70h */ 1861 U64 InvalidCrcCount; /* 78h */ 1862 U64 FcpInitiatorIoCount; /* 80h */ 1863 } fCONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 1864 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 1865 1866 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 1867 1868 1869 typedef struct _CONFIG_PAGE_FC_PORT_7 1870 { 1871 fCONFIG_PAGE_HEADER Header; /* 00h */ 1872 U32 Reserved; /* 04h */ 1873 U8 PortSymbolicName[256]; /* 08h */ 1874 } fCONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 1875 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 1876 1877 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 1878 1879 1880 typedef struct _CONFIG_PAGE_FC_PORT_8 1881 { 1882 fCONFIG_PAGE_HEADER Header; /* 00h */ 1883 U32 BitVector[8]; /* 04h */ 1884 } fCONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 1885 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 1886 1887 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 1888 1889 1890 typedef struct _CONFIG_PAGE_FC_PORT_9 1891 { 1892 fCONFIG_PAGE_HEADER Header; /* 00h */ 1893 U32 Reserved; /* 04h */ 1894 U64 GlobalWWPN; /* 08h */ 1895 U64 GlobalWWNN; /* 10h */ 1896 U32 UnitType; /* 18h */ 1897 U32 PhysicalPortNumber; /* 1Ch */ 1898 U32 NumAttachedNodes; /* 20h */ 1899 U16 IPVersion; /* 24h */ 1900 U16 UDPPortNumber; /* 26h */ 1901 U8 IPAddress[16]; /* 28h */ 1902 U16 Reserved1; /* 38h */ 1903 U16 TopologyDiscoveryFlags; /* 3Ah */ 1904 } fCONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 1905 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 1906 1907 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 1908 1909 1910 /**************************************************************************** 1911 * FC Device Config Pages 1912 ****************************************************************************/ 1913 1914 typedef struct _CONFIG_PAGE_FC_DEVICE_0 1915 { 1916 fCONFIG_PAGE_HEADER Header; /* 00h */ 1917 U64 WWNN; /* 04h */ 1918 U64 WWPN; /* 0Ch */ 1919 U32 PortIdentifier; /* 14h */ 1920 U8 Protocol; /* 18h */ 1921 U8 Flags; /* 19h */ 1922 U16 BBCredit; /* 1Ah */ 1923 U16 MaxRxFrameSize; /* 1Ch */ 1924 U8 Reserved1; /* 1Eh */ 1925 U8 PortNumber; /* 1Fh */ 1926 U8 FcPhLowestVersion; /* 20h */ 1927 U8 FcPhHighestVersion; /* 21h */ 1928 U8 CurrentTargetID; /* 22h */ 1929 U8 CurrentBus; /* 23h */ 1930 } fCONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 1931 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 1932 1933 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02) 1934 1935 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 1936 1937 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 1938 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 1939 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 1940 1941 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 1942 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 1943 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 1944 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 1945 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 1946 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 1947 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 1948 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 1949 1950 1951 /**************************************************************************** 1952 * RAID Volume Config Pages 1953 ****************************************************************************/ 1954 1955 typedef struct _RAID_VOL0_PHYS_DISK 1956 { 1957 U16 Reserved; /* 00h */ 1958 U8 PhysDiskMap; /* 02h */ 1959 U8 PhysDiskNum; /* 03h */ 1960 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 1961 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 1962 1963 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1964 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1965 1966 typedef struct _RAID_VOL0_STATUS 1967 { 1968 U8 Flags; /* 00h */ 1969 U8 State; /* 01h */ 1970 U16 Reserved; /* 02h */ 1971 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 1972 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 1973 1974 /* RAID Volume Page 0 VolumeStatus defines */ 1975 1976 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 1977 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 1978 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 1979 1980 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 1981 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 1982 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 1983 1984 typedef struct _RAID_VOL0_SETTINGS 1985 { 1986 U16 Settings; /* 00h */ 1987 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1988 U8 Reserved; /* 02h */ 1989 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 1990 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 1991 1992 /* RAID Volume Page 0 VolumeSettings defines */ 1993 1994 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 1995 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 1996 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 1997 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 1998 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 1999 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 2000 2001 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 2002 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 2003 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 2004 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 2005 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 2006 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 2007 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 2008 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 2009 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 2010 2011 /* 2012 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2013 * one and check Header.PageLength at runtime. 2014 */ 2015 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 2016 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 2017 #endif 2018 2019 typedef struct _CONFIG_PAGE_RAID_VOL_0 2020 { 2021 fCONFIG_PAGE_HEADER Header; /* 00h */ 2022 U8 VolumeID; /* 04h */ 2023 U8 VolumeBus; /* 05h */ 2024 U8 VolumeIOC; /* 06h */ 2025 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 2026 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 2027 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 2028 U32 MaxLBA; /* 10h */ 2029 U32 Reserved1; /* 14h */ 2030 U32 StripeSize; /* 18h */ 2031 U32 Reserved2; /* 1Ch */ 2032 U32 Reserved3; /* 20h */ 2033 U8 NumPhysDisks; /* 24h */ 2034 U8 Reserved4; /* 25h */ 2035 U16 Reserved5; /* 26h */ 2036 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 2037 } fCONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 2038 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 2039 2040 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x00) 2041 2042 2043 /**************************************************************************** 2044 * RAID Physical Disk Config Pages 2045 ****************************************************************************/ 2046 2047 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 2048 { 2049 U8 ErrorCdbByte; /* 00h */ 2050 U8 ErrorSenseKey; /* 01h */ 2051 U16 Reserved; /* 02h */ 2052 U16 ErrorCount; /* 04h */ 2053 U8 ErrorASC; /* 06h */ 2054 U8 ErrorASCQ; /* 07h */ 2055 U16 SmartCount; /* 08h */ 2056 U8 SmartASC; /* 0Ah */ 2057 U8 SmartASCQ; /* 0Bh */ 2058 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 2059 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 2060 2061 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 2062 { 2063 U8 VendorID[8]; /* 00h */ 2064 U8 ProductID[16]; /* 08h */ 2065 U8 ProductRevLevel[4]; /* 18h */ 2066 U8 Info[32]; /* 1Ch */ 2067 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 2068 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 2069 2070 typedef struct _RAID_PHYS_DISK0_SETTINGS 2071 { 2072 U8 SepID; /* 00h */ 2073 U8 SepBus; /* 01h */ 2074 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2075 U8 PhysDiskSettings; /* 03h */ 2076 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 2077 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 2078 2079 typedef struct _RAID_PHYS_DISK0_STATUS 2080 { 2081 U8 Flags; /* 00h */ 2082 U8 State; /* 01h */ 2083 U16 Reserved; /* 02h */ 2084 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 2085 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 2086 2087 /* RAID Volume 2 IM Physical Disk DiskStatus flags */ 2088 2089 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 2090 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2091 2092 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 2093 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 2094 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 2095 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 2096 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 2097 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 2098 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 2099 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 2100 2101 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 2102 { 2103 fCONFIG_PAGE_HEADER Header; /* 00h */ 2104 U8 PhysDiskID; /* 04h */ 2105 U8 PhysDiskBus; /* 05h */ 2106 U8 PhysDiskIOC; /* 06h */ 2107 U8 PhysDiskNum; /* 07h */ 2108 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 2109 U32 Reserved1; /* 0Ch */ 2110 U32 Reserved2; /* 10h */ 2111 U32 Reserved3; /* 14h */ 2112 U8 DiskIdentifier[16]; /* 18h */ 2113 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 2114 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 2115 U32 MaxLBA; /* 68h */ 2116 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2117 } fCONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 2118 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 2119 2120 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00) 2121 2122 2123 /**************************************************************************** 2124 * LAN Config Pages 2125 ****************************************************************************/ 2126 2127 typedef struct _CONFIG_PAGE_LAN_0 2128 { 2129 ConfigPageHeader_t Header; /* 00h */ 2130 U16 TxRxModes; /* 04h */ 2131 U16 Reserved; /* 06h */ 2132 U32 PacketPrePad; /* 08h */ 2133 } fCONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 2134 LANPage0_t, MPI_POINTER pLANPage0_t; 2135 2136 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 2137 2138 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 2139 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 2140 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 2141 2142 typedef struct _CONFIG_PAGE_LAN_1 2143 { 2144 ConfigPageHeader_t Header; /* 00h */ 2145 U16 Reserved; /* 04h */ 2146 U8 CurrentDeviceState; /* 06h */ 2147 U8 Reserved1; /* 07h */ 2148 U32 MinPacketSize; /* 08h */ 2149 U32 MaxPacketSize; /* 0Ch */ 2150 U32 HardwareAddressLow; /* 10h */ 2151 U32 HardwareAddressHigh; /* 14h */ 2152 U32 MaxWireSpeedLow; /* 18h */ 2153 U32 MaxWireSpeedHigh; /* 1Ch */ 2154 U32 BucketsRemaining; /* 20h */ 2155 U32 MaxReplySize; /* 24h */ 2156 U32 NegWireSpeedLow; /* 28h */ 2157 U32 NegWireSpeedHigh; /* 2Ch */ 2158 } fCONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 2159 LANPage1_t, MPI_POINTER pLANPage1_t; 2160 2161 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 2162 2163 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 2164 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 2165 2166 #endif 2167 2168 2169 /* 2170 * Copyright (c) 2000, 2001 by LSI Logic Corporation 2171 * 2172 * Redistribution and use in source and binary forms, with or without 2173 * modification, are permitted provided that the following conditions 2174 * are met: 2175 * 1. Redistributions of source code must retain the above copyright 2176 * notice immediately at the beginning of the file, without modification, 2177 * this list of conditions, and the following disclaimer. 2178 * 2. The name of the author may not be used to endorse or promote products 2179 * derived from this software without specific prior written permission. 2180 * 2181 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2182 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2183 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2184 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2185 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2186 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2187 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2188 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2189 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2190 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2191 * SUCH DAMAGE. 2192 * 2193 * 2194 * Name: MPI_FC.H 2195 * Title: MPI Fibre Channel messages and structures 2196 * Creation Date: June 12, 2000 2197 * 2198 * MPI Version: 01.02.02 2199 * 2200 * Version History 2201 * --------------- 2202 * 2203 * Date Version Description 2204 * -------- -------- ------------------------------------------------------ 2205 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 2206 * 06-06-00 01.00.01 Update version number for 1.0 release. 2207 * 06-12-00 01.00.02 Added _MSG_FC_ABORT_REPLY structure. 2208 * 11-02-00 01.01.01 Original release for post 1.0 work 2209 * 12-04-00 01.01.02 Added messages for Common Transport Send and 2210 * Primitive Send. 2211 * 01-09-01 01.01.03 Modified some of the new flags to have an MPI prefix 2212 * and modified the FcPrimitiveSend flags. 2213 * 01-25-01 01.01.04 Move InitiatorIndex in LinkServiceRsp reply to a larger 2214 * field. 2215 * Added FC_ABORT_TYPE_CT_SEND_REQUEST and 2216 * FC_ABORT_TYPE_EXLINKSEND_REQUEST for FcAbort request. 2217 * Added MPI_FC_PRIM_SEND_FLAGS_STOP_SEND. 2218 * 02-20-01 01.01.05 Started using MPI_POINTER. 2219 * 03-27-01 01.01.06 Added Flags field to MSG_LINK_SERVICE_BUFFER_POST_REPLY 2220 * and defined MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED. 2221 * Added MPI_FC_PRIM_SEND_FLAGS_RESET_LINK define. 2222 * Added structure offset comments. 2223 * 04-09-01 01.01.07 Added RspLength field to MSG_LINK_SERVICE_RSP_REQUEST. 2224 * 08-08-01 01.02.01 Original release for v1.2 work. 2225 * 09-28-01 01.02.02 Change name of reserved field in 2226 * MSG_LINK_SERVICE_RSP_REPLY. 2227 * -------------------------------------------------------------------------- 2228 */ 2229 2230 #ifndef MPI_FC_H 2231 #define MPI_FC_H 2232 2233 2234 /***************************************************************************** 2235 * 2236 * F C T a r g e t M o d e M e s s a g e s 2237 * 2238 *****************************************************************************/ 2239 2240 /****************************************************************************/ 2241 /* Link Service Buffer Post messages */ 2242 /****************************************************************************/ 2243 2244 typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REQUEST 2245 { 2246 U8 BufferPostFlags; /* 00h */ 2247 U8 BufferCount; /* 01h */ 2248 U8 ChainOffset; /* 02h */ 2249 U8 Function; /* 03h */ 2250 U16 Reserved; /* 04h */ 2251 U8 Reserved1; /* 06h */ 2252 U8 MsgFlags; /* 07h */ 2253 U32 MsgContext; /* 08h */ 2254 SGE_TRANS_SIMPLE_UNION SGL; 2255 } MSG_LINK_SERVICE_BUFFER_POST_REQUEST, 2256 MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REQUEST, 2257 LinkServiceBufferPostRequest_t, MPI_POINTER pLinkServiceBufferPostRequest_t; 2258 2259 #define LINK_SERVICE_BUFFER_POST_FLAGS_PORT_MASK (0x01) 2260 2261 typedef struct _WWNFORMAT 2262 { 2263 U32 PortNameHigh; /* 00h */ 2264 U32 PortNameLow; /* 04h */ 2265 U32 NodeNameHigh; /* 08h */ 2266 U32 NodeNameLow; /* 0Ch */ 2267 } WWNFORMAT, 2268 WwnFormat_t; 2269 2270 /* Link Service Buffer Post Reply */ 2271 typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REPLY 2272 { 2273 U8 Flags; /* 00h */ 2274 U8 Reserved; /* 01h */ 2275 U8 MsgLength; /* 02h */ 2276 U8 Function; /* 03h */ 2277 U16 Reserved1; /* 04h */ 2278 U8 PortNumber; /* 06h */ 2279 U8 MsgFlags; /* 07h */ 2280 U32 MsgContext; /* 08h */ 2281 U16 Reserved2; /* 0Ch */ 2282 U16 IOCStatus; /* 0Eh */ 2283 U32 IOCLogInfo; /* 10h */ 2284 U32 TransferLength; /* 14h */ 2285 U32 TransactionContext; /* 18h */ 2286 U32 Rctl_Did; /* 1Ch */ 2287 U32 Csctl_Sid; /* 20h */ 2288 U32 Type_Fctl; /* 24h */ 2289 U16 SeqCnt; /* 28h */ 2290 U8 Dfctl; /* 2Ah */ 2291 U8 SeqId; /* 2Bh */ 2292 U16 Rxid; /* 2Ch */ 2293 U16 Oxid; /* 2Eh */ 2294 U32 Parameter; /* 30h */ 2295 WWNFORMAT Wwn; /* 34h */ 2296 } MSG_LINK_SERVICE_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REPLY, 2297 LinkServiceBufferPostReply_t, MPI_POINTER pLinkServiceBufferPostReply_t; 2298 2299 #define MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED (0x80) 2300 2301 #define MPI_FC_DID_MASK (0x00FFFFFF) 2302 #define MPI_FC_DID_SHIFT (0) 2303 #define MPI_FC_RCTL_MASK (0xFF000000) 2304 #define MPI_FC_RCTL_SHIFT (24) 2305 #define MPI_FC_SID_MASK (0x00FFFFFF) 2306 #define MPI_FC_SID_SHIFT (0) 2307 #define MPI_FC_CSCTL_MASK (0xFF000000) 2308 #define MPI_FC_CSCTL_SHIFT (24) 2309 #define MPI_FC_FCTL_MASK (0x00FFFFFF) 2310 #define MPI_FC_FCTL_SHIFT (0) 2311 #define MPI_FC_TYPE_MASK (0xFF000000) 2312 #define MPI_FC_TYPE_SHIFT (24) 2313 2314 /* obsolete name for the above */ 2315 #define FCP_TARGET_DID_MASK (0x00FFFFFF) 2316 #define FCP_TARGET_DID_SHIFT (0) 2317 #define FCP_TARGET_RCTL_MASK (0xFF000000) 2318 #define FCP_TARGET_RCTL_SHIFT (24) 2319 #define FCP_TARGET_SID_MASK (0x00FFFFFF) 2320 #define FCP_TARGET_SID_SHIFT (0) 2321 #define FCP_TARGET_CSCTL_MASK (0xFF000000) 2322 #define FCP_TARGET_CSCTL_SHIFT (24) 2323 #define FCP_TARGET_FCTL_MASK (0x00FFFFFF) 2324 #define FCP_TARGET_FCTL_SHIFT (0) 2325 #define FCP_TARGET_TYPE_MASK (0xFF000000) 2326 #define FCP_TARGET_TYPE_SHIFT (24) 2327 2328 2329 /****************************************************************************/ 2330 /* Link Service Response messages */ 2331 /****************************************************************************/ 2332 2333 typedef struct _MSG_LINK_SERVICE_RSP_REQUEST 2334 { 2335 U8 RspFlags; /* 00h */ 2336 U8 RspLength; /* 01h */ 2337 U8 ChainOffset; /* 02h */ 2338 U8 Function; /* 03h */ 2339 U16 Reserved1; /* 04h */ 2340 U8 Reserved2; /* 06h */ 2341 U8 MsgFlags; /* 07h */ 2342 U32 MsgContext; /* 08h */ 2343 U32 Rctl_Did; /* 0Ch */ 2344 U32 Csctl_Sid; /* 10h */ 2345 U32 Type_Fctl; /* 14h */ 2346 U16 SeqCnt; /* 18h */ 2347 U8 Dfctl; /* 1Ah */ 2348 U8 SeqId; /* 1Bh */ 2349 U16 Rxid; /* 1Ch */ 2350 U16 Oxid; /* 1Eh */ 2351 U32 Parameter; /* 20h */ 2352 SGE_SIMPLE_UNION SGL; /* 24h */ 2353 } MSG_LINK_SERVICE_RSP_REQUEST, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REQUEST, 2354 LinkServiceRspRequest_t, MPI_POINTER pLinkServiceRspRequest_t; 2355 2356 #define LINK_SERVICE_RSP_FLAGS_IMMEDIATE (0x80) 2357 #define LINK_SERVICE_RSP_FLAGS_PORT_MASK (0x01) 2358 2359 2360 /* Link Service Response Reply */ 2361 typedef struct _MSG_LINK_SERVICE_RSP_REPLY 2362 { 2363 U16 Reserved; /* 00h */ 2364 U8 MsgLength; /* 02h */ 2365 U8 Function; /* 03h */ 2366 U16 Reserved1; /* 04h */ 2367 U8 Reserved_0100_InitiatorIndex; /* 06h */ /* obsolete InitiatorIndex */ 2368 U8 MsgFlags; /* 07h */ 2369 U32 MsgContext; /* 08h */ 2370 U16 Reserved3; /* 0Ch */ 2371 U16 IOCStatus; /* 0Eh */ 2372 U32 IOCLogInfo; /* 10h */ 2373 U32 InitiatorIndex; /* 14h */ 2374 } MSG_LINK_SERVICE_RSP_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REPLY, 2375 LinkServiceRspReply_t, MPI_POINTER pLinkServiceRspReply_t; 2376 2377 2378 /****************************************************************************/ 2379 /* Extended Link Service Send messages */ 2380 /****************************************************************************/ 2381 2382 typedef struct _MSG_EXLINK_SERVICE_SEND_REQUEST 2383 { 2384 U8 SendFlags; /* 00h */ 2385 U8 Reserved; /* 01h */ 2386 U8 ChainOffset; /* 02h */ 2387 U8 Function; /* 03h */ 2388 U32 MsgFlags_Did; /* 04h */ 2389 U32 MsgContext; /* 08h */ 2390 U32 ElsCommandCode; /* 0Ch */ 2391 SGE_SIMPLE_UNION SGL; /* 10h */ 2392 } MSG_EXLINK_SERVICE_SEND_REQUEST, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REQUEST, 2393 ExLinkServiceSendRequest_t, MPI_POINTER pExLinkServiceSendRequest_t; 2394 2395 #define EX_LINK_SERVICE_SEND_DID_MASK (0x00FFFFFF) 2396 #define EX_LINK_SERVICE_SEND_DID_SHIFT (0) 2397 #define EX_LINK_SERVICE_SEND_MSGFLAGS_MASK (0xFF000000) 2398 #define EX_LINK_SERVICE_SEND_MSGFLAGS_SHIFT (24) 2399 2400 2401 /* Extended Link Service Send Reply */ 2402 typedef struct _MSG_EXLINK_SERVICE_SEND_REPLY 2403 { 2404 U16 Reserved; /* 00h */ 2405 U8 MsgLength; /* 02h */ 2406 U8 Function; /* 03h */ 2407 U16 Reserved1; /* 04h */ 2408 U8 Reserved2; /* 06h */ 2409 U8 MsgFlags; /* 07h */ 2410 U32 MsgContext; /* 08h */ 2411 U16 Reserved3; /* 0Ch */ 2412 U16 IOCStatus; /* 0Eh */ 2413 U32 IOCLogInfo; /* 10h */ 2414 U32 ResponseLength; /* 14h */ 2415 } MSG_EXLINK_SERVICE_SEND_REPLY, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REPLY, 2416 ExLinkServiceSendReply_t, MPI_POINTER pExLinkServiceSendReply_t; 2417 2418 /****************************************************************************/ 2419 /* FC Abort messages */ 2420 /****************************************************************************/ 2421 2422 typedef struct _MSG_FC_ABORT_REQUEST 2423 { 2424 U8 AbortFlags; /* 00h */ 2425 U8 AbortType; /* 01h */ 2426 U8 ChainOffset; /* 02h */ 2427 U8 Function; /* 03h */ 2428 U16 Reserved1; /* 04h */ 2429 U8 Reserved2; /* 06h */ 2430 U8 MsgFlags; /* 07h */ 2431 U32 MsgContext; /* 08h */ 2432 U32 TransactionContextToAbort; /* 0Ch */ 2433 } MSG_FC_ABORT_REQUEST, MPI_POINTER PTR_MSG_FC_ABORT_REQUEST, 2434 FcAbortRequest_t, MPI_POINTER pFcAbortRequest_t; 2435 2436 #define FC_ABORT_FLAG_PORT_MASK (0x01) 2437 2438 #define FC_ABORT_TYPE_ALL_FC_BUFFERS (0x00) 2439 #define FC_ABORT_TYPE_EXACT_FC_BUFFER (0x01) 2440 #define FC_ABORT_TYPE_CT_SEND_REQUEST (0x02) 2441 #define FC_ABORT_TYPE_EXLINKSEND_REQUEST (0x03) 2442 2443 /* FC Abort Reply */ 2444 typedef struct _MSG_FC_ABORT_REPLY 2445 { 2446 U16 Reserved; /* 00h */ 2447 U8 MsgLength; /* 02h */ 2448 U8 Function; /* 03h */ 2449 U16 Reserved1; /* 04h */ 2450 U8 Reserved2; /* 06h */ 2451 U8 MsgFlags; /* 07h */ 2452 U32 MsgContext; /* 08h */ 2453 U16 Reserved3; /* 0Ch */ 2454 U16 IOCStatus; /* 0Eh */ 2455 U32 IOCLogInfo; /* 10h */ 2456 } MSG_FC_ABORT_REPLY, MPI_POINTER PTR_MSG_FC_ABORT_REPLY, 2457 FcAbortReply_t, MPI_POINTER pFcAbortReply_t; 2458 2459 2460 /****************************************************************************/ 2461 /* FC Common Transport Send messages */ 2462 /****************************************************************************/ 2463 2464 typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REQUEST 2465 { 2466 U8 SendFlags; /* 00h */ 2467 U8 Reserved; /* 01h */ 2468 U8 ChainOffset; /* 02h */ 2469 U8 Function; /* 03h */ 2470 U32 MsgFlags_Did; /* 04h */ 2471 U32 MsgContext; /* 08h */ 2472 U16 CTCommandCode; /* 0Ch */ 2473 U8 FsType; /* 0Eh */ 2474 U8 Reserved1; /* 0Fh */ 2475 SGE_SIMPLE_UNION SGL; /* 10h */ 2476 } MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, 2477 MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, 2478 FcCommonTransportSendRequest_t, MPI_POINTER pFcCommonTransportSendRequest_t; 2479 2480 #define MPI_FC_CT_SEND_DID_MASK (0x00FFFFFF) 2481 #define MPI_FC_CT_SEND_DID_SHIFT (0) 2482 #define MPI_FC_CT_SEND_MSGFLAGS_MASK (0xFF000000) 2483 #define MPI_FC_CT_SEND_MSGFLAGS_SHIFT (24) 2484 2485 2486 /* FC Common Transport Send Reply */ 2487 typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REPLY 2488 { 2489 U16 Reserved; /* 00h */ 2490 U8 MsgLength; /* 02h */ 2491 U8 Function; /* 03h */ 2492 U16 Reserved1; /* 04h */ 2493 U8 Reserved2; /* 06h */ 2494 U8 MsgFlags; /* 07h */ 2495 U32 MsgContext; /* 08h */ 2496 U16 Reserved3; /* 0Ch */ 2497 U16 IOCStatus; /* 0Eh */ 2498 U32 IOCLogInfo; /* 10h */ 2499 U32 ResponseLength; /* 14h */ 2500 } MSG_FC_COMMON_TRANSPORT_SEND_REPLY, MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REPLY, 2501 FcCommonTransportSendReply_t, MPI_POINTER pFcCommonTransportSendReply_t; 2502 2503 2504 /****************************************************************************/ 2505 /* FC Primitive Send messages */ 2506 /****************************************************************************/ 2507 2508 typedef struct _MSG_FC_PRIMITIVE_SEND_REQUEST 2509 { 2510 U8 SendFlags; /* 00h */ 2511 U8 Reserved; /* 01h */ 2512 U8 ChainOffset; /* 02h */ 2513 U8 Function; /* 03h */ 2514 U16 Reserved1; /* 04h */ 2515 U8 Reserved2; /* 06h */ 2516 U8 MsgFlags; /* 07h */ 2517 U32 MsgContext; /* 08h */ 2518 U8 FcPrimitive[4]; /* 0Ch */ 2519 } MSG_FC_PRIMITIVE_SEND_REQUEST, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REQUEST, 2520 FcPrimitiveSendRequest_t, MPI_POINTER pFcPrimitiveSendRequest_t; 2521 2522 #define MPI_FC_PRIM_SEND_FLAGS_PORT_MASK (0x01) 2523 #define MPI_FC_PRIM_SEND_FLAGS_RESET_LINK (0x04) 2524 #define MPI_FC_PRIM_SEND_FLAGS_STOP_SEND (0x08) 2525 #define MPI_FC_PRIM_SEND_FLAGS_SEND_ONCE (0x10) 2526 #define MPI_FC_PRIM_SEND_FLAGS_SEND_AROUND (0x20) 2527 #define MPI_FC_PRIM_SEND_FLAGS_UNTIL_FULL (0x40) 2528 #define MPI_FC_PRIM_SEND_FLAGS_FOREVER (0x80) 2529 2530 /* FC Primitive Send Reply */ 2531 typedef struct _MSG_FC_PRIMITIVE_SEND_REPLY 2532 { 2533 U8 SendFlags; /* 00h */ 2534 U8 Reserved; /* 01h */ 2535 U8 MsgLength; /* 02h */ 2536 U8 Function; /* 03h */ 2537 U16 Reserved1; /* 04h */ 2538 U8 Reserved2; /* 06h */ 2539 U8 MsgFlags; /* 07h */ 2540 U32 MsgContext; /* 08h */ 2541 U16 Reserved3; /* 0Ch */ 2542 U16 IOCStatus; /* 0Eh */ 2543 U32 IOCLogInfo; /* 10h */ 2544 } MSG_FC_PRIMITIVE_SEND_REPLY, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REPLY, 2545 FcPrimitiveSendReply_t, MPI_POINTER pFcPrimitiveSendReply_t; 2546 2547 #endif 2548 2549 2550 /* 2551 * Copyright (c) 2000, 2001 by LSI Logic Corporation 2552 * 2553 * Redistribution and use in source and binary forms, with or without 2554 * modification, are permitted provided that the following conditions 2555 * are met: 2556 * 1. Redistributions of source code must retain the above copyright 2557 * notice immediately at the beginning of the file, without modification, 2558 * this list of conditions, and the following disclaimer. 2559 * 2. The name of the author may not be used to endorse or promote products 2560 * derived from this software without specific prior written permission. 2561 * 2562 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2563 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2564 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2565 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2566 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2567 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2568 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2569 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2570 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2571 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2572 * SUCH DAMAGE. 2573 * 2574 * 2575 * Name: MPI_INIT.H 2576 * Title: MPI initiator mode messages and structures 2577 * Creation Date: June 8, 2000 2578 * 2579 * MPI Version: 01.02.04 2580 * 2581 * Version History 2582 * --------------- 2583 * 2584 * Date Version Description 2585 * -------- -------- ------------------------------------------------------ 2586 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 2587 * 05-24-00 00.10.02 Added SenseBufferLength to _MSG_SCSI_IO_REPLY. 2588 * 06-06-00 01.00.01 Update version number for 1.0 release. 2589 * 06-08-00 01.00.02 Added MPI_SCSI_RSP_INFO_ definitions. 2590 * 11-02-00 01.01.01 Original release for post 1.0 work. 2591 * 12-04-00 01.01.02 Added MPI_SCSIIO_CONTROL_NO_DISCONNECT. 2592 * 02-20-01 01.01.03 Started using MPI_POINTER. 2593 * 03-27-01 01.01.04 Added structure offset comments. 2594 * 04-10-01 01.01.05 Added new MsgFlag for MSG_SCSI_TASK_MGMT. 2595 * 08-08-01 01.02.01 Original release for v1.2 work. 2596 * 08-29-01 01.02.02 Added MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET. 2597 * Added MPI_SCSI_STATE_QUEUE_TAG_REJECTED for 2598 * MSG_SCSI_IO_REPLY. 2599 * 09-28-01 01.02.03 Added structures and defines for SCSI Enclosure 2600 * Processor messages. 2601 * 10-04-01 01.02.04 Added defines for SEP request Action field. 2602 * -------------------------------------------------------------------------- 2603 */ 2604 2605 #ifndef MPI_INIT_H 2606 #define MPI_INIT_H 2607 2608 2609 /***************************************************************************** 2610 * 2611 * S C S I I n i t i a t o r M e s s a g e s 2612 * 2613 *****************************************************************************/ 2614 2615 /****************************************************************************/ 2616 /* SCSI IO messages and associated structures */ 2617 /****************************************************************************/ 2618 2619 typedef struct _MSG_SCSI_IO_REQUEST 2620 { 2621 U8 TargetID; /* 00h */ 2622 U8 Bus; /* 01h */ 2623 U8 ChainOffset; /* 02h */ 2624 U8 Function; /* 03h */ 2625 U8 CDBLength; /* 04h */ 2626 U8 SenseBufferLength; /* 05h */ 2627 U8 Reserved; /* 06h */ 2628 U8 MsgFlags; /* 07h */ 2629 U32 MsgContext; /* 08h */ 2630 U8 LUN[8]; /* 0Ch */ 2631 U32 Control; /* 14h */ 2632 U8 CDB[16]; /* 18h */ 2633 U32 DataLength; /* 28h */ 2634 U32 SenseBufferLowAddr; /* 2Ch */ 2635 SGE_IO_UNION SGL; /* 30h */ 2636 } MSG_SCSI_IO_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO_REQUEST, 2637 SCSIIORequest_t, MPI_POINTER pSCSIIORequest_t; 2638 2639 2640 /* SCSIO MsgFlags bits */ 2641 2642 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01) 2643 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00) 2644 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01) 2645 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02) 2646 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00) 2647 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02) 2648 2649 /* SCSIIO LUN fields */ 2650 2651 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 2652 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 2653 #define MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 2654 #define MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 2655 #define MPI_SCSIIO_LUN_LEVEL_1_WORD (0xFF00) 2656 #define MPI_SCSIIO_LUN_LEVEL_1_DWORD (0x0000FF00) 2657 2658 /* SCSIO Control bits */ 2659 2660 #define MPI_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 2661 #define MPI_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 2662 #define MPI_SCSIIO_CONTROL_WRITE (0x01000000) 2663 #define MPI_SCSIIO_CONTROL_READ (0x02000000) 2664 2665 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK (0x3C000000) 2666 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 2667 2668 #define MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 2669 #define MPI_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 2670 #define MPI_SCSIIO_CONTROL_HEADOFQ (0x00000100) 2671 #define MPI_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 2672 #define MPI_SCSIIO_CONTROL_ACAQ (0x00000400) 2673 #define MPI_SCSIIO_CONTROL_UNTAGGED (0x00000500) 2674 #define MPI_SCSIIO_CONTROL_NO_DISCONNECT (0x00000700) 2675 2676 #define MPI_SCSIIO_CONTROL_TASKMANAGE_MASK (0x00FF0000) 2677 #define MPI_SCSIIO_CONTROL_OBSOLETE (0x00800000) 2678 #define MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV (0x00400000) 2679 #define MPI_SCSIIO_CONTROL_TARGET_RESET (0x00200000) 2680 #define MPI_SCSIIO_CONTROL_LUN_RESET_RSV (0x00100000) 2681 #define MPI_SCSIIO_CONTROL_RESERVED (0x00080000) 2682 #define MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV (0x00040000) 2683 #define MPI_SCSIIO_CONTROL_ABORT_TASK_SET (0x00020000) 2684 #define MPI_SCSIIO_CONTROL_RESERVED2 (0x00010000) 2685 2686 2687 /* SCSIIO reply structure */ 2688 typedef struct _MSG_SCSI_IO_REPLY 2689 { 2690 U8 TargetID; /* 00h */ 2691 U8 Bus; /* 01h */ 2692 U8 MsgLength; /* 02h */ 2693 U8 Function; /* 03h */ 2694 U8 CDBLength; /* 04h */ 2695 U8 SenseBufferLength; /* 05h */ 2696 U8 Reserved; /* 06h */ 2697 U8 MsgFlags; /* 07h */ 2698 U32 MsgContext; /* 08h */ 2699 U8 SCSIStatus; /* 0Ch */ 2700 U8 SCSIState; /* 0Dh */ 2701 U16 IOCStatus; /* 0Eh */ 2702 U32 IOCLogInfo; /* 10h */ 2703 U32 TransferCount; /* 14h */ 2704 U32 SenseCount; /* 18h */ 2705 U32 ResponseInfo; /* 1Ch */ 2706 } MSG_SCSI_IO_REPLY, MPI_POINTER PTR_MSG_SCSI_IO_REPLY, 2707 SCSIIOReply_t, MPI_POINTER pSCSIIOReply_t; 2708 2709 2710 /* SCSIIO Reply SCSIStatus values (SAM-2 status codes) */ 2711 2712 #define MPI_SCSI_STATUS_SUCCESS (0x00) 2713 #define MPI_SCSI_STATUS_CHECK_CONDITION (0x02) 2714 #define MPI_SCSI_STATUS_CONDITION_MET (0x04) 2715 #define MPI_SCSI_STATUS_BUSY (0x08) 2716 #define MPI_SCSI_STATUS_INTERMEDIATE (0x10) 2717 #define MPI_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14) 2718 #define MPI_SCSI_STATUS_RESERVATION_CONFLICT (0x18) 2719 #define MPI_SCSI_STATUS_COMMAND_TERMINATED (0x22) 2720 #define MPI_SCSI_STATUS_TASK_SET_FULL (0x28) 2721 #define MPI_SCSI_STATUS_ACA_ACTIVE (0x30) 2722 2723 2724 /* SCSIIO Reply SCSIState values */ 2725 2726 #define MPI_SCSI_STATE_AUTOSENSE_VALID (0x01) 2727 #define MPI_SCSI_STATE_AUTOSENSE_FAILED (0x02) 2728 #define MPI_SCSI_STATE_NO_SCSI_STATUS (0x04) 2729 #define MPI_SCSI_STATE_TERMINATED (0x08) 2730 #define MPI_SCSI_STATE_RESPONSE_INFO_VALID (0x10) 2731 #define MPI_SCSI_STATE_QUEUE_TAG_REJECTED (0x20) 2732 2733 /* SCSIIO Reply ResponseInfo values */ 2734 /* (FCP-1 RSP_CODE values and SPI-3 Packetized Failure codes) */ 2735 2736 #define MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE (0x00000000) 2737 #define MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR (0x01000000) 2738 #define MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID (0x02000000) 2739 #define MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR (0x03000000) 2740 #define MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED (0x04000000) 2741 #define MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED (0x05000000) 2742 #define MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE (0x06000000) 2743 2744 2745 /****************************************************************************/ 2746 /* SCSI Task Management messages */ 2747 /****************************************************************************/ 2748 2749 typedef struct _MSG_SCSI_TASK_MGMT 2750 { 2751 U8 TargetID; /* 00h */ 2752 U8 Bus; /* 01h */ 2753 U8 ChainOffset; /* 02h */ 2754 U8 Function; /* 03h */ 2755 U8 Reserved; /* 04h */ 2756 U8 TaskType; /* 05h */ 2757 U8 Reserved1; /* 06h */ 2758 U8 MsgFlags; /* 07h */ 2759 U32 MsgContext; /* 08h */ 2760 U8 LUN[8]; /* 0Ch */ 2761 U32 Reserved2[7]; /* 14h */ 2762 U32 TaskMsgContext; /* 30h */ 2763 } MSG_SCSI_TASK_MGMT, MPI_POINTER PTR_SCSI_TASK_MGMT, 2764 SCSITaskMgmt_t, MPI_POINTER pSCSITaskMgmt_t; 2765 2766 /* TaskType values */ 2767 2768 #define MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 2769 #define MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 2770 #define MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 2771 #define MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS (0x04) 2772 #define MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 2773 2774 /* MsgFlags bits */ 2775 #define MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION (0x00) 2776 #define MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION (0x02) 2777 #define MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION (0x04) 2778 2779 /* SCSI Task Management Reply */ 2780 typedef struct _MSG_SCSI_TASK_MGMT_REPLY 2781 { 2782 U8 TargetID; /* 00h */ 2783 U8 Bus; /* 01h */ 2784 U8 MsgLength; /* 02h */ 2785 U8 Function; /* 03h */ 2786 U8 Reserved; /* 04h */ 2787 U8 TaskType; /* 05h */ 2788 U8 Reserved1; /* 06h */ 2789 U8 MsgFlags; /* 07h */ 2790 U32 MsgContext; /* 08h */ 2791 U8 Reserved2[2]; /* 0Ch */ 2792 U16 IOCStatus; /* 0Eh */ 2793 U32 IOCLogInfo; /* 10h */ 2794 U32 TerminationCount; /* 14h */ 2795 } MSG_SCSI_TASK_MGMT_REPLY, MPI_POINTER PTR_MSG_SCSI_TASK_MGMT_REPLY, 2796 SCSITaskMgmtReply_t, MPI_POINTER pSCSITaskMgmtReply_t; 2797 2798 2799 /****************************************************************************/ 2800 /* SCSI Enclosure Processor messages */ 2801 /****************************************************************************/ 2802 2803 typedef struct _MSG_SEP_REQUEST 2804 { 2805 U8 TargetID; /* 00h */ 2806 U8 Bus; /* 01h */ 2807 U8 ChainOffset; /* 02h */ 2808 U8 Function; /* 03h */ 2809 U8 Action; /* 04h */ 2810 U8 Reserved1; /* 05h */ 2811 U8 Reserved2; /* 06h */ 2812 U8 MsgFlags; /* 07h */ 2813 U32 MsgContext; /* 08h */ 2814 U32 SlotStatus; /* 0Ch */ 2815 } MSG_SEP_REQUEST, MPI_POINTER PTR_MSG_SEP_REQUEST, 2816 SEPRequest_t, MPI_POINTER pSEPRequest_t; 2817 2818 /* Action defines */ 2819 #define MPI_SEP_REQ_ACTION_WRITE_STATUS (0x00) 2820 #define MPI_SEP_REQ_ACTION_READ_STATUS (0x01) 2821 2822 /* SlotStatus bits for MSG_SEP_REQUEST */ 2823 #define MPI_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001) 2824 #define MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002) 2825 #define MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004) 2826 #define MPI_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) 2827 #define MPI_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) 2828 #define MPI_SEP_REQ_SLOTSTATUS_PARITY_CHECK (0x00000020) 2829 #define MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040) 2830 #define MPI_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080) 2831 #define MPI_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100) 2832 #define MPI_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200) 2833 #define MPI_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) 2834 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000) 2835 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_INSERT (0x00080000) 2836 #define MPI_SEP_REQ_SLOTSTATUS_DO_NOT_MOVE (0x00400000) 2837 #define MPI_SEP_REQ_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) 2838 #define MPI_SEP_REQ_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) 2839 #define MPI_SEP_REQ_SLOTSTATUS_DEV_OFF (0x10000000) 2840 #define MPI_SEP_REQ_SLOTSTATUS_SWAP_RESET (0x80000000) 2841 2842 2843 typedef struct _MSG_SEP_REPLY 2844 { 2845 U8 TargetID; /* 00h */ 2846 U8 Bus; /* 01h */ 2847 U8 MsgLength; /* 02h */ 2848 U8 Function; /* 03h */ 2849 U8 Action; /* 04h */ 2850 U8 Reserved1; /* 05h */ 2851 U8 Reserved2; /* 06h */ 2852 U8 MsgFlags; /* 07h */ 2853 U32 MsgContext; /* 08h */ 2854 U16 Reserved3; /* 0Ch */ 2855 U16 IOCStatus; /* 0Eh */ 2856 U32 IOCLogInfo; /* 10h */ 2857 U32 SlotStatus; /* 14h */ 2858 } MSG_SEP_REPLY, MPI_POINTER PTR_MSG_SEP_REPLY, 2859 SEPReply_t, MPI_POINTER pSEPReply_t; 2860 2861 /* SlotStatus bits for MSG_SEP_REPLY */ 2862 #define MPI_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001) 2863 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002) 2864 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004) 2865 #define MPI_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) 2866 #define MPI_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) 2867 #define MPI_SEP_REPLY_SLOTSTATUS_PARITY_CHECK (0x00000020) 2868 #define MPI_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040) 2869 #define MPI_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080) 2870 #define MPI_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100) 2871 #define MPI_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200) 2872 #define MPI_SEP_REPLY_SLOTSTATUS_REPORT (0x00010000) 2873 #define MPI_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) 2874 #define MPI_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000) 2875 #define MPI_SEP_REPLY_SLOTSTATUS_INSERT_READY (0x00080000) 2876 #define MPI_SEP_REPLY_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 2877 #define MPI_SEP_REPLY_SLOTSTATUS_B_BYPASS_ENABLED (0x01000000) 2878 #define MPI_SEP_REPLY_SLOTSTATUS_A_BYPASS_ENABLED (0x02000000) 2879 #define MPI_SEP_REPLY_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) 2880 #define MPI_SEP_REPLY_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) 2881 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x10000000) 2882 #define MPI_SEP_REPLY_SLOTSTATUS_FAULT_SENSED (0x40000000) 2883 #define MPI_SEP_REPLY_SLOTSTATUS_SWAPPED (0x80000000) 2884 2885 #endif 2886 2887 /* 2888 * Copyright (c) 2000, 2001 by LSI Logic Corporation 2889 * 2890 * Redistribution and use in source and binary forms, with or without 2891 * modification, are permitted provided that the following conditions 2892 * are met: 2893 * 1. Redistributions of source code must retain the above copyright 2894 * notice immediately at the beginning of the file, without modification, 2895 * this list of conditions, and the following disclaimer. 2896 * 2. The name of the author may not be used to endorse or promote products 2897 * derived from this software without specific prior written permission. 2898 * 2899 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2900 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2901 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2902 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2903 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2904 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2905 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2906 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2907 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2908 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2909 * SUCH DAMAGE. 2910 * 2911 * 2912 * Name: MPI_IOC.H 2913 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 2914 * Creation Date: August 11, 2000 2915 * 2916 * MPI Version: 01.02.04 2917 * 2918 * Version History 2919 * --------------- 2920 * 2921 * Date Version Description 2922 * -------- -------- ------------------------------------------------------ 2923 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 2924 * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure. 2925 * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY. 2926 * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure. 2927 * Added _MSG_EVENT_ACK_REPLY structure. 2928 * Added _MSG_FW_DOWNLOAD_REPLY structure. 2929 * Added _MSG_TOOLBOX_REPLY structure. 2930 * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure. 2931 * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI, 2932 * _LINK_STATUS, _LOOP_STATE and _LOGOUT. 2933 * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in 2934 * _MSG_EVENT_ACK_REPLY structure to match specification. 2935 * 11-02-00 01.01.01 Original release for post 1.0 work. 2936 * Added a value for Manufacturer to WhoInit. 2937 * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and 2938 * removed toolbox message. 2939 * 01-09-01 01.01.03 Added event enabled and disabled defines. 2940 * Added structures for FwHeader and DataHeader. 2941 * Added ImageType to FwUpload reply. 2942 * 02-20-01 01.01.04 Started using MPI_POINTER. 2943 * 02-27-01 01.01.05 Added event for RAID status change and its event data. 2944 * Added IocNumber field to MSG_IOC_FACTS_REPLY. 2945 * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER. 2946 * Added structure offset comments. 2947 * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE. 2948 * 08-08-01 01.02.01 Original release for v1.2 work. 2949 * New format for FWVersion and ProductId in 2950 * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER. 2951 * 08-31-01 01.02.02 Added event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and 2952 * related structure and defines. 2953 * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED. 2954 * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE. 2955 * Replaced a reserved field in MSG_IOC_FACTS_REPLY with 2956 * IOCExceptions and changed DataImageSize to reserved. 2957 * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and 2958 * MPI_FW_UPLOAD_ITYPE_NVDATA. 2959 * 09-28-01 01.02.03 Modified Event Data for Integrated RAID. 2960 * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field. 2961 * -------------------------------------------------------------------------- 2962 */ 2963 2964 #ifndef MPI_IOC_H 2965 #define MPI_IOC_H 2966 2967 2968 /***************************************************************************** 2969 * 2970 * I O C M e s s a g e s 2971 * 2972 *****************************************************************************/ 2973 2974 /****************************************************************************/ 2975 /* IOCInit message */ 2976 /****************************************************************************/ 2977 2978 typedef struct _MSG_IOC_INIT 2979 { 2980 U8 WhoInit; /* 00h */ 2981 U8 Reserved; /* 01h */ 2982 U8 ChainOffset; /* 02h */ 2983 U8 Function; /* 03h */ 2984 U8 Flags; /* 04h */ 2985 U8 MaxDevices; /* 05h */ 2986 U8 MaxBuses; /* 06h */ 2987 U8 MsgFlags; /* 07h */ 2988 U32 MsgContext; /* 08h */ 2989 U16 ReplyFrameSize; /* 0Ch */ 2990 U8 Reserved1[2]; /* 0Eh */ 2991 U32 HostMfaHighAddr; /* 10h */ 2992 U32 SenseBufferHighAddr; /* 14h */ 2993 } MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT, 2994 IOCInit_t, MPI_POINTER pIOCInit_t; 2995 2996 /* WhoInit values */ 2997 #define MPI_WHOINIT_NO_ONE (0x00) 2998 #define MPI_WHOINIT_SYSTEM_BIOS (0x01) 2999 #define MPI_WHOINIT_ROM_BIOS (0x02) 3000 #define MPI_WHOINIT_PCI_PEER (0x03) 3001 #define MPI_WHOINIT_HOST_DRIVER (0x04) 3002 #define MPI_WHOINIT_MANUFACTURER (0x05) 3003 3004 /* Flags values */ 3005 #define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01) 3006 3007 typedef struct _MSG_IOC_INIT_REPLY 3008 { 3009 U8 WhoInit; /* 00h */ 3010 U8 Reserved; /* 01h */ 3011 U8 MsgLength; /* 02h */ 3012 U8 Function; /* 03h */ 3013 U8 Flags; /* 04h */ 3014 U8 MaxDevices; /* 05h */ 3015 U8 MaxBuses; /* 06h */ 3016 U8 MsgFlags; /* 07h */ 3017 U32 MsgContext; /* 08h */ 3018 U16 Reserved2; /* 0Ch */ 3019 U16 IOCStatus; /* 0Eh */ 3020 U32 IOCLogInfo; /* 10h */ 3021 } MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY, 3022 IOCInitReply_t, MPI_POINTER pIOCInitReply_t; 3023 3024 3025 3026 /****************************************************************************/ 3027 /* IOC Facts message */ 3028 /****************************************************************************/ 3029 3030 typedef struct _MSG_IOC_FACTS 3031 { 3032 U8 Reserved[2]; /* 00h */ 3033 U8 ChainOffset; /* 01h */ 3034 U8 Function; /* 02h */ 3035 U8 Reserved1[3]; /* 03h */ 3036 U8 MsgFlags; /* 04h */ 3037 U32 MsgContext; /* 08h */ 3038 } MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS, 3039 IOCFacts_t, MPI_POINTER pIOCFacts_t; 3040 3041 typedef struct _MPI_FW_VERSION_STRUCT 3042 { 3043 U8 Dev; /* 00h */ 3044 U8 Unit; /* 01h */ 3045 U8 Minor; /* 02h */ 3046 U8 Major; /* 03h */ 3047 } MPI_FW_VERSION_STRUCT; 3048 3049 typedef union _MPI_FW_VERSION 3050 { 3051 MPI_FW_VERSION_STRUCT Struct; 3052 U32 Word; 3053 } MPI_FW_VERSION; 3054 3055 /* IOC Facts Reply */ 3056 typedef struct _MSG_IOC_FACTS_REPLY 3057 { 3058 U16 MsgVersion; /* 00h */ 3059 U8 MsgLength; /* 02h */ 3060 U8 Function; /* 03h */ 3061 U16 Reserved; /* 04h */ 3062 U8 IOCNumber; /* 06h */ 3063 U8 MsgFlags; /* 07h */ 3064 U32 MsgContext; /* 08h */ 3065 U16 IOCExceptions; /* 0Ch */ 3066 U16 IOCStatus; /* 0Eh */ 3067 U32 IOCLogInfo; /* 10h */ 3068 U8 MaxChainDepth; /* 14h */ 3069 U8 WhoInit; /* 15h */ 3070 U8 BlockSize; /* 16h */ 3071 U8 Flags; /* 17h */ 3072 U16 ReplyQueueDepth; /* 18h */ 3073 U16 RequestFrameSize; /* 1Ah */ 3074 U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */ 3075 U16 ProductID; /* 1Eh */ 3076 U32 CurrentHostMfaHighAddr; /* 20h */ 3077 U16 GlobalCredits; /* 24h */ 3078 U8 NumberOfPorts; /* 26h */ 3079 U8 EventState; /* 27h */ 3080 U32 CurrentSenseBufferHighAddr; /* 28h */ 3081 U16 CurReplyFrameSize; /* 2Ch */ 3082 U8 MaxDevices; /* 2Eh */ 3083 U8 MaxBuses; /* 2Fh */ 3084 U32 FWImageSize; /* 30h */ 3085 U32 Reserved4; /* 34h */ 3086 MPI_FW_VERSION FWVersion; /* 38h */ 3087 } MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY, 3088 IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t; 3089 3090 #define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 3091 #define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 3092 3093 #define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 3094 3095 #define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01) 3096 3097 #define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00) 3098 #define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01) 3099 3100 3101 3102 /***************************************************************************** 3103 * 3104 * P o r t M e s s a g e s 3105 * 3106 *****************************************************************************/ 3107 3108 /****************************************************************************/ 3109 /* Port Facts message and Reply */ 3110 /****************************************************************************/ 3111 3112 typedef struct _MSG_PORT_FACTS 3113 { 3114 U8 Reserved[2]; /* 00h */ 3115 U8 ChainOffset; /* 02h */ 3116 U8 Function; /* 03h */ 3117 U8 Reserved1[2]; /* 04h */ 3118 U8 PortNumber; /* 06h */ 3119 U8 MsgFlags; /* 07h */ 3120 U32 MsgContext; /* 08h */ 3121 } MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS, 3122 PortFacts_t, MPI_POINTER pPortFacts_t; 3123 3124 typedef struct _MSG_PORT_FACTS_REPLY 3125 { 3126 U16 Reserved; /* 00h */ 3127 U8 MsgLength; /* 02h */ 3128 U8 Function; /* 03h */ 3129 U16 Reserved1; /* 04h */ 3130 U8 PortNumber; /* 06h */ 3131 U8 MsgFlags; /* 07h */ 3132 U32 MsgContext; /* 08h */ 3133 U16 Reserved2; /* 0Ch */ 3134 U16 IOCStatus; /* 0Eh */ 3135 U32 IOCLogInfo; /* 10h */ 3136 U8 Reserved3; /* 14h */ 3137 U8 PortType; /* 15h */ 3138 U16 MaxDevices; /* 16h */ 3139 U16 PortSCSIID; /* 18h */ 3140 U16 ProtocolFlags; /* 1Ah */ 3141 U16 MaxPostedCmdBuffers; /* 1Ch */ 3142 U16 MaxPersistentIDs; /* 1Eh */ 3143 U16 MaxLanBuckets; /* 20h */ 3144 U16 Reserved4; /* 22h */ 3145 U32 Reserved5; /* 24h */ 3146 } MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY, 3147 PortFactsReply_t, MPI_POINTER pPortFactsReply_t; 3148 3149 3150 /* PortTypes values */ 3151 3152 #define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00) 3153 #define MPI_PORTFACTS_PORTTYPE_SCSI (0x01) 3154 #define MPI_PORTFACTS_PORTTYPE_FC (0x10) 3155 #define MPI_PORTFACTS_PORTTYPE_ISCSI (0x20) 3156 #define MPI_PORTFACTS_PORTTYPE_SAS (0x30) 3157 3158 /* ProtocolFlags values */ 3159 3160 #define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01) 3161 #define MPI_PORTFACTS_PROTOCOL_LAN (0x02) 3162 #define MPI_PORTFACTS_PROTOCOL_TARGET (0x04) 3163 #define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08) 3164 3165 3166 /****************************************************************************/ 3167 /* Port Enable Message */ 3168 /****************************************************************************/ 3169 3170 typedef struct _MSG_PORT_ENABLE 3171 { 3172 U8 Reserved[2]; /* 00h */ 3173 U8 ChainOffset; /* 02h */ 3174 U8 Function; /* 03h */ 3175 U8 Reserved1[2]; /* 04h */ 3176 U8 PortNumber; /* 06h */ 3177 U8 MsgFlags; /* 07h */ 3178 U32 MsgContext; /* 08h */ 3179 } MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE, 3180 PortEnable_t, MPI_POINTER pPortEnable_t; 3181 3182 typedef struct _MSG_PORT_ENABLE_REPLY 3183 { 3184 U8 Reserved[2]; /* 00h */ 3185 U8 MsgLength; /* 02h */ 3186 U8 Function; /* 03h */ 3187 U8 Reserved1[2]; /* 04h */ 3188 U8 PortNumber; /* 05h */ 3189 U8 MsgFlags; /* 07h */ 3190 U32 MsgContext; /* 08h */ 3191 U16 Reserved2; /* 0Ch */ 3192 U16 IOCStatus; /* 0Eh */ 3193 U32 IOCLogInfo; /* 10h */ 3194 } MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY, 3195 PortEnableReply_t, MPI_POINTER pPortEnableReply_t; 3196 3197 3198 /***************************************************************************** 3199 * 3200 * E v e n t M e s s a g e s 3201 * 3202 *****************************************************************************/ 3203 3204 /****************************************************************************/ 3205 /* Event Notification messages */ 3206 /****************************************************************************/ 3207 3208 typedef struct _MSG_EVENT_NOTIFY 3209 { 3210 U8 Switch; /* 00h */ 3211 U8 Reserved; /* 01h */ 3212 U8 ChainOffset; /* 02h */ 3213 U8 Function; /* 03h */ 3214 U8 Reserved1[3]; /* 04h */ 3215 U8 MsgFlags; /* 07h */ 3216 U32 MsgContext; /* 08h */ 3217 } MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY, 3218 EventNotification_t, MPI_POINTER pEventNotification_t; 3219 3220 /* Event Notification Reply */ 3221 3222 typedef struct _MSG_EVENT_NOTIFY_REPLY 3223 { 3224 U16 EventDataLength; /* 00h */ 3225 U8 MsgLength; /* 02h */ 3226 U8 Function; /* 03h */ 3227 U8 Reserved1[2]; /* 04h */ 3228 U8 AckRequired; /* 06h */ 3229 U8 MsgFlags; /* 07h */ 3230 U32 MsgContext; /* 08h */ 3231 U8 Reserved2[2]; /* 0Ch */ 3232 U16 IOCStatus; /* 0Eh */ 3233 U32 IOCLogInfo; /* 10h */ 3234 U32 Event; /* 14h */ 3235 U32 EventContext; /* 18h */ 3236 U32 Data[1]; /* 1Ch */ 3237 } MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY, 3238 EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t; 3239 3240 /* Event Acknowledge */ 3241 3242 typedef struct _MSG_EVENT_ACK 3243 { 3244 U8 Reserved[2]; /* 00h */ 3245 U8 ChainOffset; /* 02h */ 3246 U8 Function; /* 03h */ 3247 U8 Reserved1[3]; /* 04h */ 3248 U8 MsgFlags; /* 07h */ 3249 U32 MsgContext; /* 08h */ 3250 U32 Event; /* 0Ch */ 3251 U32 EventContext; /* 10h */ 3252 } MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK, 3253 EventAck_t, MPI_POINTER pEventAck_t; 3254 3255 typedef struct _MSG_EVENT_ACK_REPLY 3256 { 3257 U8 Reserved[2]; /* 00h */ 3258 U8 MsgLength; /* 02h */ 3259 U8 Function; /* 03h */ 3260 U8 Reserved1[3]; /* 04h */ 3261 U8 MsgFlags; /* 07h */ 3262 U32 MsgContext; /* 08h */ 3263 U16 Reserved2; /* 0Ch */ 3264 U16 IOCStatus; /* 0Eh */ 3265 U32 IOCLogInfo; /* 10h */ 3266 } MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY, 3267 EventAckReply_t, MPI_POINTER pEventAckReply_t; 3268 3269 /* Switch */ 3270 3271 #define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00) 3272 #define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01) 3273 3274 /* Event */ 3275 3276 #define MPI_EVENT_NONE (0x00000000) 3277 #define MPI_EVENT_LOG_DATA (0x00000001) 3278 #define MPI_EVENT_STATE_CHANGE (0x00000002) 3279 #define MPI_EVENT_UNIT_ATTENTION (0x00000003) 3280 #define MPI_EVENT_IOC_BUS_RESET (0x00000004) 3281 #define MPI_EVENT_EXT_BUS_RESET (0x00000005) 3282 #define MPI_EVENT_RESCAN (0x00000006) 3283 #define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007) 3284 #define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008) 3285 #define MPI_EVENT_LOGOUT (0x00000009) 3286 #define MPI_EVENT_EVENT_CHANGE (0x0000000A) 3287 #define MPI_EVENT_INTEGRATED_RAID (0x0000000B) 3288 #define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C) 3289 #define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D) 3290 #define MPI_EVENT_QUEUE_FULL (0x0000000E) 3291 #define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0000000F) 3292 #define MPI_EVENT_SAS_SES (0x00000010) 3293 #define MPI_EVENT_PERSISTENT_TABLE_FULL (0x00000011) 3294 #define MPI_EVENT_SAS_PHY_LINK_STATUS (0x00000012) 3295 #define MPI_EVENT_SAS_DISCOVERY_ERROR (0x00000013) 3296 #define MPI_EVENT_IR_RESYNC_UPDATE (0x00000014) 3297 #define MPI_EVENT_IR2 (0x00000015) 3298 #define MPI_EVENT_SAS_DISCOVERY (0x00000016) 3299 3300 /* AckRequired field values */ 3301 3302 #define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 3303 #define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 3304 3305 /* EventChange Event data */ 3306 3307 typedef struct _EVENT_DATA_EVENT_CHANGE 3308 { 3309 U8 EventState; /* 00h */ 3310 U8 Reserved; /* 01h */ 3311 U16 Reserved1; /* 02h */ 3312 } EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE, 3313 EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t; 3314 3315 /* SCSI Event data for Port, Bus and Device forms */ 3316 3317 typedef struct _EVENT_DATA_SCSI 3318 { 3319 U8 TargetID; /* 00h */ 3320 U8 BusPort; /* 01h */ 3321 U16 Reserved; /* 02h */ 3322 } EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI, 3323 EventDataScsi_t, MPI_POINTER pEventDataScsi_t; 3324 3325 /* SCSI Device Status Change Event data */ 3326 3327 typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE 3328 { 3329 U8 TargetID; /* 00h */ 3330 U8 Bus; /* 01h */ 3331 U8 ReasonCode; /* 02h */ 3332 U8 LUN; /* 03h */ 3333 U8 ASC; /* 04h */ 3334 U8 ASCQ; /* 05h */ 3335 U16 Reserved; /* 06h */ 3336 } EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 3337 MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 3338 MpiEventDataScsiDeviceStatusChange_t, 3339 MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t; 3340 3341 /* MPI SCSI Device Status Change Event data ReasonCode values */ 3342 #define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03) 3343 #define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04) 3344 #define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05) 3345 3346 /* MPI Link Status Change Event data */ 3347 3348 typedef struct _EVENT_DATA_LINK_STATUS 3349 { 3350 U8 State; /* 00h */ 3351 U8 Reserved; /* 01h */ 3352 U16 Reserved1; /* 02h */ 3353 U8 Reserved2; /* 04h */ 3354 U8 Port; /* 05h */ 3355 U16 Reserved3; /* 06h */ 3356 } EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS, 3357 EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t; 3358 3359 #define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000) 3360 #define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001) 3361 3362 /* MPI Loop State Change Event data */ 3363 3364 typedef struct _EVENT_DATA_LOOP_STATE 3365 { 3366 U8 Character4; /* 00h */ 3367 U8 Character3; /* 01h */ 3368 U8 Type; /* 02h */ 3369 U8 Reserved; /* 03h */ 3370 U8 Reserved1; /* 04h */ 3371 U8 Port; /* 05h */ 3372 U16 Reserved2; /* 06h */ 3373 } EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE, 3374 EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t; 3375 3376 #define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001) 3377 #define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002) 3378 #define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003) 3379 3380 /* MPI LOGOUT Event data */ 3381 3382 typedef struct _EVENT_DATA_LOGOUT 3383 { 3384 U32 NPortID; /* 00h */ 3385 U8 Reserved; /* 04h */ 3386 U8 Port; /* 05h */ 3387 U16 Reserved1; /* 06h */ 3388 } EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT, 3389 EventDataLogout_t, MPI_POINTER pEventDataLogout_t; 3390 3391 /* MPI Integrated RAID Event data */ 3392 3393 typedef struct _EVENT_DATA_RAID 3394 { 3395 U8 VolumeID; /* 00h */ 3396 U8 VolumeBus; /* 01h */ 3397 U8 ReasonCode; /* 02h */ 3398 U8 PhysDiskNum; /* 03h */ 3399 U8 ASC; /* 04h */ 3400 U8 ASCQ; /* 05h */ 3401 U16 Reserved; /* 06h */ 3402 U32 SettingsStatus; /* 08h */ 3403 } EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID, 3404 MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t; 3405 3406 /* MPI Integrated RAID Event data ReasonCode values */ 3407 #define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00) 3408 #define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01) 3409 #define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02) 3410 #define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03) 3411 #define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04) 3412 #define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05) 3413 #define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06) 3414 #define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07) 3415 #define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08) 3416 #define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09) 3417 #define MPI_EVENT_RAID_RC_SMART_DATA (0x0A) 3418 #define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B) 3419 3420 /* MPI SAS Phy Link Event data */ 3421 3422 typedef struct _EVENT_DATA_SAS_PHY_LINK_STATUS 3423 { 3424 U8 PhyNum; /* 00h */ 3425 U8 LinkRates; /* 01h */ 3426 U16 DevHandle; /* 02h */ 3427 U64 SASAddress; /* 04h */ 3428 } EVENT_DATA_SAS_PHY_LINK_STATUS, 3429 MPI_POINTER PTR_EVENT_DATA_SAS_PHY_LINK_STATUS, 3430 EventDataSASPhyLinkStatus_t, MPI_POINTER pEventDataSASPhyLinkStatus_t; 3431 3432 #define MPI_EVENT_SAS_PLS_LR_CURRENT_MASK (0xF0) 3433 #define MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT (4) 3434 #define MPI_EVENT_SAS_PLS_LR_PREVIOUS_MASK (0x0F) 3435 #define MPI_EVENT_SAS_PLS_LR_PREVIOUS_SHIFT (0) 3436 #define MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN (0x00) 3437 #define MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED (0x01) 3438 #define MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEG (0x02) 3439 #define MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE (0x03) 3440 #define MPI_EVENT_SAS_PLS_LR_RATE_1_5 (0x08) 3441 #define MPI_EVENT_SAS_PLS_LR_RATE_3_0 (0x09) 3442 3443 /***************************************************************************** 3444 * 3445 * F i r m w a r e L o a d M e s s a g e s 3446 * 3447 *****************************************************************************/ 3448 3449 /****************************************************************************/ 3450 /* Firmware Download message and associated structures */ 3451 /****************************************************************************/ 3452 3453 typedef struct _MSG_FW_DOWNLOAD 3454 { 3455 U8 ImageType; /* 00h */ 3456 U8 Reserved; /* 01h */ 3457 U8 ChainOffset; /* 02h */ 3458 U8 Function; /* 03h */ 3459 U8 Reserved1[3]; /* 04h */ 3460 U8 MsgFlags; /* 07h */ 3461 U32 MsgContext; /* 08h */ 3462 SGE_MPI_UNION SGL; /* 0Ch */ 3463 } MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD, 3464 FWDownload_t, MPI_POINTER pFWDownload_t; 3465 3466 #define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00) 3467 #define MPI_FW_DOWNLOAD_ITYPE_FW (0x01) 3468 #define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02) 3469 #define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03) 3470 3471 3472 typedef struct _FWDownloadTCSGE 3473 { 3474 U8 Reserved; /* 00h */ 3475 U8 ContextSize; /* 01h */ 3476 U8 DetailsLength; /* 02h */ 3477 U8 Flags; /* 03h */ 3478 U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */ 3479 U32 ImageOffset; /* 08h */ 3480 U32 ImageSize; /* 0Ch */ 3481 } FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE, 3482 FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t; 3483 3484 /* Firmware Download reply */ 3485 typedef struct _MSG_FW_DOWNLOAD_REPLY 3486 { 3487 U8 ImageType; /* 00h */ 3488 U8 Reserved; /* 01h */ 3489 U8 MsgLength; /* 02h */ 3490 U8 Function; /* 03h */ 3491 U8 Reserved1[3]; /* 04h */ 3492 U8 MsgFlags; /* 07h */ 3493 U32 MsgContext; /* 08h */ 3494 U16 Reserved2; /* 0Ch */ 3495 U16 IOCStatus; /* 0Eh */ 3496 U32 IOCLogInfo; /* 10h */ 3497 } MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY, 3498 FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t; 3499 3500 3501 /****************************************************************************/ 3502 /* Firmware Upload message and associated structures */ 3503 /****************************************************************************/ 3504 3505 typedef struct _MSG_FW_UPLOAD 3506 { 3507 U8 ImageType; /* 00h */ 3508 U8 Reserved; /* 01h */ 3509 U8 ChainOffset; /* 02h */ 3510 U8 Function; /* 03h */ 3511 U8 Reserved1[3]; /* 04h */ 3512 U8 MsgFlags; /* 07h */ 3513 U32 MsgContext; /* 08h */ 3514 SGE_MPI_UNION SGL; /* 0Ch */ 3515 } MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD, 3516 FWUpload_t, MPI_POINTER pFWUpload_t; 3517 3518 #define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00) 3519 #define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 3520 #define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 3521 #define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03) 3522 3523 typedef struct _FWUploadTCSGE 3524 { 3525 U8 Reserved; /* 00h */ 3526 U8 ContextSize; /* 01h */ 3527 U8 DetailsLength; /* 02h */ 3528 U8 Flags; /* 03h */ 3529 U32 Reserved1; /* 04h */ 3530 U32 ImageOffset; /* 08h */ 3531 U32 ImageSize; /* 0Ch */ 3532 } FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE, 3533 FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t; 3534 3535 /* Firmware Upload reply */ 3536 typedef struct _MSG_FW_UPLOAD_REPLY 3537 { 3538 U8 ImageType; /* 00h */ 3539 U8 Reserved; /* 01h */ 3540 U8 MsgLength; /* 02h */ 3541 U8 Function; /* 03h */ 3542 U8 Reserved1[3]; /* 04h */ 3543 U8 MsgFlags; /* 07h */ 3544 U32 MsgContext; /* 08h */ 3545 U16 Reserved2; /* 0Ch */ 3546 U16 IOCStatus; /* 0Eh */ 3547 U32 IOCLogInfo; /* 10h */ 3548 U32 ActualImageSize; /* 14h */ 3549 } MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY, 3550 FWUploadReply_t, MPI_POINTER pFWUploadReply_t; 3551 3552 3553 typedef struct _MPI_FW_HEADER 3554 { 3555 U32 ArmBranchInstruction0; /* 00h */ 3556 U32 Signature0; /* 04h */ 3557 U32 Signature1; /* 08h */ 3558 U32 Signature2; /* 0Ch */ 3559 U32 ArmBranchInstruction1; /* 10h */ 3560 U32 ArmBranchInstruction2; /* 14h */ 3561 U32 Reserved; /* 18h */ 3562 U32 Checksum; /* 1Ch */ 3563 U16 VendorId; /* 20h */ 3564 U16 ProductId; /* 22h */ 3565 MPI_FW_VERSION FWVersion; /* 24h */ 3566 U32 SeqCodeVersion; /* 28h */ 3567 U32 ImageSize; /* 2Ch */ 3568 U32 NextImageHeaderOffset; /* 30h */ 3569 U32 LoadStartAddress; /* 34h */ 3570 U32 IopResetVectorValue; /* 38h */ 3571 U32 IopResetRegAddr; /* 3Ch */ 3572 U32 VersionNameWhat; /* 40h */ 3573 U8 VersionName[32]; /* 44h */ 3574 U32 VendorNameWhat; /* 64h */ 3575 U8 VendorName[32]; /* 68h */ 3576 } MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER, 3577 MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t; 3578 3579 #define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840) 3580 3581 /* defines for using the ProductId field */ 3582 #define MPI_FW_HEADER_PID_TYPE_MASK (0xF000) 3583 #define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000) 3584 #define MPI_FW_HEADER_PID_TYPE_FC (0x1000) 3585 3586 #define MPI_FW_HEADER_PID_PROD_MASK (0x0F00) 3587 #define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100) 3588 #define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 3589 #define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300) 3590 #define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400) 3591 #define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500) 3592 #define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600) 3593 3594 #define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF) 3595 #define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001) 3596 #define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002) 3597 #define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003) 3598 #define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004) 3599 #define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005) 3600 #define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006) 3601 #define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007) 3602 #define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008) 3603 #define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009) 3604 #define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A) 3605 #define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000) 3606 #define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) 3607 #define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) 3608 3609 typedef struct _MPI_EXT_IMAGE_HEADER 3610 { 3611 U8 ImageType; /* 00h */ 3612 U8 Reserved; /* 01h */ 3613 U16 Reserved1; /* 02h */ 3614 U32 Checksum; /* 04h */ 3615 U32 ImageSize; /* 08h */ 3616 U32 NextImageHeaderOffset; /* 0Ch */ 3617 U32 LoadStartAddress; /* 10h */ 3618 U32 Reserved2; /* 14h */ 3619 } MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER, 3620 MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t; 3621 3622 /* defines for the ImageType field */ 3623 #define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 3624 #define MPI_EXT_IMAGE_TYPE_FW (0x01) 3625 #define MPI_EXT_IMAGE_TYPE_NVDATA (0x03) 3626 3627 #endif 3628 3629 /* 3630 * Copyright (c) 2000, 2001 by LSI Logic Corporation 3631 * 3632 * Redistribution and use in source and binary forms, with or without 3633 * modification, are permitted provided that the following conditions 3634 * are met: 3635 * 1. Redistributions of source code must retain the above copyright 3636 * notice immediately at the beginning of the file, without modification, 3637 * this list of conditions, and the following disclaimer. 3638 * 2. The name of the author may not be used to endorse or promote products 3639 * derived from this software without specific prior written permission. 3640 * 3641 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 3642 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 3643 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 3644 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 3645 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3646 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3647 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3648 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3649 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3650 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3651 * SUCH DAMAGE. 3652 * 3653 * 3654 * Name: MPI_LAN.H 3655 * Title: MPI LAN messages and structures 3656 * Creation Date: June 30, 2000 3657 * 3658 * MPI Version: 01.02.01 3659 * 3660 * Version History 3661 * --------------- 3662 * 3663 * Date Version Description 3664 * -------- -------- ------------------------------------------------------ 3665 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 3666 * 05-24-00 00.10.02 Added LANStatus field to _MSG_LAN_SEND_REPLY. 3667 * Added LANStatus field to _MSG_LAN_RECEIVE_POST_REPLY. 3668 * Moved ListCount field in _MSG_LAN_RECEIVE_POST_REPLY. 3669 * 06-06-00 01.00.01 Update version number for 1.0 release. 3670 * 06-12-00 01.00.02 Added MPI_ to BUCKETSTATUS_ definitions. 3671 * 06-22-00 01.00.03 Major changes to match new LAN definition in 1.0 spec. 3672 * 06-30-00 01.00.04 Added Context Reply definitions per revised proposal. 3673 * Changed transaction context usage to bucket/buffer. 3674 * 07-05-00 01.00.05 Removed LAN_RECEIVE_POST_BUCKET_CONTEXT_MASK definition 3675 * to lan private header file 3676 * 11-02-00 01.01.01 Original release for post 1.0 work 3677 * 02-20-01 01.01.02 Started using MPI_POINTER. 3678 * 03-27-01 01.01.03 Added structure offset comments. 3679 * 08-08-01 01.02.01 Original release for v1.2 work. 3680 * -------------------------------------------------------------------------- 3681 */ 3682 3683 #ifndef MPI_LAN_H 3684 #define MPI_LAN_H 3685 3686 3687 /****************************************************************************** 3688 * 3689 * L A N M e s s a g e s 3690 * 3691 *******************************************************************************/ 3692 3693 /* LANSend messages */ 3694 3695 typedef struct _MSG_LAN_SEND_REQUEST 3696 { 3697 U16 Reserved; /* 00h */ 3698 U8 ChainOffset; /* 02h */ 3699 U8 Function; /* 03h */ 3700 U16 Reserved2; /* 04h */ 3701 U8 PortNumber; /* 06h */ 3702 U8 MsgFlags; /* 07h */ 3703 U32 MsgContext; /* 08h */ 3704 SGE_MPI_UNION SG_List[1]; /* 0Ch */ 3705 } MSG_LAN_SEND_REQUEST, MPI_POINTER PTR_MSG_LAN_SEND_REQUEST, 3706 LANSendRequest_t, MPI_POINTER pLANSendRequest_t; 3707 3708 3709 typedef struct _MSG_LAN_SEND_REPLY 3710 { 3711 U16 Reserved; /* 00h */ 3712 U8 MsgLength; /* 02h */ 3713 U8 Function; /* 03h */ 3714 U8 Reserved2; /* 04h */ 3715 U8 NumberOfContexts; /* 05h */ 3716 U8 PortNumber; /* 06h */ 3717 U8 MsgFlags; /* 07h */ 3718 U32 MsgContext; /* 08h */ 3719 U16 Reserved3; /* 0Ch */ 3720 U16 IOCStatus; /* 0Eh */ 3721 U32 IOCLogInfo; /* 10h */ 3722 U32 BufferContext; /* 14h */ 3723 } MSG_LAN_SEND_REPLY, MPI_POINTER PTR_MSG_LAN_SEND_REPLY, 3724 LANSendReply_t, MPI_POINTER pLANSendReply_t; 3725 3726 3727 /* LANReceivePost */ 3728 3729 typedef struct _MSG_LAN_RECEIVE_POST_REQUEST 3730 { 3731 U16 Reserved; /* 00h */ 3732 U8 ChainOffset; /* 02h */ 3733 U8 Function; /* 03h */ 3734 U16 Reserved2; /* 04h */ 3735 U8 PortNumber; /* 06h */ 3736 U8 MsgFlags; /* 07h */ 3737 U32 MsgContext; /* 08h */ 3738 U32 BucketCount; /* 0Ch */ 3739 SGE_MPI_UNION SG_List[1]; /* 10h */ 3740 } MSG_LAN_RECEIVE_POST_REQUEST, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REQUEST, 3741 LANReceivePostRequest_t, MPI_POINTER pLANReceivePostRequest_t; 3742 3743 3744 typedef struct _MSG_LAN_RECEIVE_POST_REPLY 3745 { 3746 U16 Reserved; /* 00h */ 3747 U8 MsgLength; /* 02h */ 3748 U8 Function; /* 03h */ 3749 U8 Reserved2; /* 04h */ 3750 U8 NumberOfContexts; /* 05h */ 3751 U8 PortNumber; /* 06h */ 3752 U8 MsgFlags; /* 07h */ 3753 U32 MsgContext; /* 08h */ 3754 U16 Reserved3; /* 0Ch */ 3755 U16 IOCStatus; /* 0Eh */ 3756 U32 IOCLogInfo; /* 10h */ 3757 U32 BucketsRemaining; /* 14h */ 3758 U32 PacketOffset; /* 18h */ 3759 U32 PacketLength; /* 1Ch */ 3760 U32 BucketContext[1]; /* 20h */ 3761 } MSG_LAN_RECEIVE_POST_REPLY, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REPLY, 3762 LANReceivePostReply_t, MPI_POINTER pLANReceivePostReply_t; 3763 3764 3765 /* LANReset */ 3766 3767 typedef struct _MSG_LAN_RESET_REQUEST 3768 { 3769 U16 Reserved; /* 00h */ 3770 U8 ChainOffset; /* 02h */ 3771 U8 Function; /* 03h */ 3772 U16 Reserved2; /* 04h */ 3773 U8 PortNumber; /* 05h */ 3774 U8 MsgFlags; /* 07h */ 3775 U32 MsgContext; /* 08h */ 3776 } MSG_LAN_RESET_REQUEST, MPI_POINTER PTR_MSG_LAN_RESET_REQUEST, 3777 LANResetRequest_t, MPI_POINTER pLANResetRequest_t; 3778 3779 3780 typedef struct _MSG_LAN_RESET_REPLY 3781 { 3782 U16 Reserved; /* 00h */ 3783 U8 MsgLength; /* 02h */ 3784 U8 Function; /* 03h */ 3785 U16 Reserved2; /* 04h */ 3786 U8 PortNumber; /* 06h */ 3787 U8 MsgFlags; /* 07h */ 3788 U32 MsgContext; /* 08h */ 3789 U16 Reserved3; /* 0Ch */ 3790 U16 IOCStatus; /* 0Eh */ 3791 U32 IOCLogInfo; /* 10h */ 3792 } MSG_LAN_RESET_REPLY, MPI_POINTER PTR_MSG_LAN_RESET_REPLY, 3793 LANResetReply_t, MPI_POINTER pLANResetReply_t; 3794 3795 3796 /****************************************************************************/ 3797 /* LAN Context Reply defines and macros */ 3798 /****************************************************************************/ 3799 3800 #define LAN_REPLY_PACKET_LENGTH_MASK (0x0000FFFF) 3801 #define LAN_REPLY_PACKET_LENGTH_SHIFT (0) 3802 #define LAN_REPLY_BUCKET_CONTEXT_MASK (0x07FF0000) 3803 #define LAN_REPLY_BUCKET_CONTEXT_SHIFT (16) 3804 #define LAN_REPLY_BUFFER_CONTEXT_MASK (0x07FFFFFF) 3805 #define LAN_REPLY_BUFFER_CONTEXT_SHIFT (0) 3806 #define LAN_REPLY_FORM_MASK (0x18000000) 3807 #define LAN_REPLY_FORM_RECEIVE_SINGLE (0x00) 3808 #define LAN_REPLY_FORM_RECEIVE_MULTIPLE (0x01) 3809 #define LAN_REPLY_FORM_SEND_SINGLE (0x02) 3810 #define LAN_REPLY_FORM_MESSAGE_CONTEXT (0x03) 3811 #define LAN_REPLY_FORM_SHIFT (27) 3812 3813 #define GET_LAN_PACKET_LENGTH(x) (((x) & LAN_REPLY_PACKET_LENGTH_MASK) \ 3814 >> LAN_REPLY_PACKET_LENGTH_SHIFT) 3815 3816 #define SET_LAN_PACKET_LENGTH(x, lth) \ 3817 ((x) = ((x) & ~LAN_REPLY_PACKET_LENGTH_MASK) | \ 3818 (((lth) << LAN_REPLY_PACKET_LENGTH_SHIFT) & \ 3819 LAN_REPLY_PACKET_LENGTH_MASK)) 3820 3821 #define GET_LAN_BUCKET_CONTEXT(x) (((x) & LAN_REPLY_BUCKET_CONTEXT_MASK) \ 3822 >> LAN_REPLY_BUCKET_CONTEXT_SHIFT) 3823 3824 #define SET_LAN_BUCKET_CONTEXT(x, ctx) \ 3825 ((x) = ((x) & ~LAN_REPLY_BUCKET_CONTEXT_MASK) | \ 3826 (((ctx) << LAN_REPLY_BUCKET_CONTEXT_SHIFT) & \ 3827 LAN_REPLY_BUCKET_CONTEXT_MASK)) 3828 3829 #define GET_LAN_BUFFER_CONTEXT(x) (((x) & LAN_REPLY_BUFFER_CONTEXT_MASK) \ 3830 >> LAN_REPLY_BUFFER_CONTEXT_SHIFT) 3831 3832 #define SET_LAN_BUFFER_CONTEXT(x, ctx) \ 3833 ((x) = ((x) & ~LAN_REPLY_BUFFER_CONTEXT_MASK) | \ 3834 (((ctx) << LAN_REPLY_BUFFER_CONTEXT_SHIFT) & \ 3835 LAN_REPLY_BUFFER_CONTEXT_MASK)) 3836 3837 #define GET_LAN_FORM(x) (((x) & LAN_REPLY_FORM_MASK) \ 3838 >> LAN_REPLY_FORM_SHIFT) 3839 3840 #define SET_LAN_FORM(x, frm) \ 3841 ((x) = ((x) & ~LAN_REPLY_FORM_MASK) | \ 3842 (((frm) << LAN_REPLY_FORM_SHIFT) & \ 3843 LAN_REPLY_FORM_MASK)) 3844 3845 3846 /****************************************************************************/ 3847 /* LAN Current Device State defines */ 3848 /****************************************************************************/ 3849 3850 #define MPI_LAN_DEVICE_STATE_RESET (0x00) 3851 #define MPI_LAN_DEVICE_STATE_OPERATIONAL (0x01) 3852 3853 3854 /****************************************************************************/ 3855 /* LAN Loopback defines */ 3856 /****************************************************************************/ 3857 3858 #define MPI_LAN_TX_MODES_ENABLE_LOOPBACK_SUPPRESSION (0x01) 3859 3860 #endif 3861 3862 3863 /* 3864 * Copyright (c) 2000, 2001 by LSI Logic Corporation 3865 * 3866 * Redistribution and use in source and binary forms, with or without 3867 * modification, are permitted provided that the following conditions 3868 * are met: 3869 * 1. Redistributions of source code must retain the above copyright 3870 * notice immediately at the beginning of the file, without modification, 3871 * this list of conditions, and the following disclaimer. 3872 * 2. The name of the author may not be used to endorse or promote products 3873 * derived from this software without specific prior written permission. 3874 * 3875 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 3876 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 3877 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 3878 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 3879 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3880 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3881 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3882 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3883 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3884 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3885 * SUCH DAMAGE. 3886 * 3887 * 3888 * Name: MPI_TARG.H 3889 * Title: MPI Target mode messages and structures 3890 * Creation Date: June 22, 2000 3891 * 3892 * MPI Version: 01.02.04 3893 * 3894 * Version History 3895 * --------------- 3896 * 3897 * Date Version Description 3898 * -------- -------- ------------------------------------------------------ 3899 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 3900 * 06-06-00 01.00.01 Update version number for 1.0 release. 3901 * 06-22-00 01.00.02 Added _MSG_TARGET_CMD_BUFFER_POST_REPLY structure. 3902 * Corrected DECSRIPTOR typo to DESCRIPTOR. 3903 * 11-02-00 01.01.01 Original release for post 1.0 work 3904 * Modified target mode to use IoIndex instead of 3905 * HostIndex and IocIndex. Added Alias. 3906 * 01-09-01 01.01.02 Added defines for TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER 3907 * and TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER. 3908 * 02-20-01 01.01.03 Started using MPI_POINTER. 3909 * Added structures for MPI_TARGET_SCSI_SPI_CMD_BUFFER and 3910 * MPI_TARGET_FCP_CMD_BUFFER. 3911 * 03-27-01 01.01.04 Added structure offset comments. 3912 * 08-08-01 01.02.01 Original release for v1.2 work. 3913 * 09-28-01 01.02.02 Added structure for MPI_TARGET_SCSI_SPI_STATUS_IU. 3914 * Added PriorityReason field to some replies and 3915 * defined more PriorityReason codes. 3916 * Added some defines for to support previous version 3917 * of MPI. 3918 * 10-04-01 01.02.03 Added PriorityReason to MSG_TARGET_ERROR_REPLY. 3919 * 11-01-01 01.02.04 Added define for TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY. 3920 * -------------------------------------------------------------------------- 3921 */ 3922 3923 #ifndef MPI_TARG_H 3924 #define MPI_TARG_H 3925 3926 3927 /****************************************************************************** 3928 * 3929 * S C S I T a r g e t M e s s a g e s 3930 * 3931 *******************************************************************************/ 3932 3933 typedef struct _CMD_BUFFER_DESCRIPTOR 3934 { 3935 U16 IoIndex; /* 00h */ 3936 U16 Reserved; /* 02h */ 3937 union /* 04h */ 3938 { 3939 U32 PhysicalAddress32; 3940 U64 PhysicalAddress64; 3941 } _u; 3942 } CMD_BUFFER_DESCRIPTOR, MPI_POINTER PTR_CMD_BUFFER_DESCRIPTOR, 3943 CmdBufferDescriptor_t, MPI_POINTER pCmdBufferDescriptor_t; 3944 3945 3946 /****************************************************************************/ 3947 /* Target Command Buffer Post Request */ 3948 /****************************************************************************/ 3949 3950 typedef struct _MSG_TARGET_CMD_BUFFER_POST_REQUEST 3951 { 3952 U8 BufferPostFlags; /* 00h */ 3953 U8 BufferCount; /* 01h */ 3954 U8 ChainOffset; /* 02h */ 3955 U8 Function; /* 03h */ 3956 U8 BufferLength; /* 04h */ 3957 U8 Reserved; /* 05h */ 3958 U8 Reserved1; /* 06h */ 3959 U8 MsgFlags; /* 07h */ 3960 U32 MsgContext; /* 08h */ 3961 CMD_BUFFER_DESCRIPTOR Buffer[1]; /* 0Ch */ 3962 } MSG_TARGET_CMD_BUFFER_POST_REQUEST, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REQUEST, 3963 TargetCmdBufferPostRequest_t, MPI_POINTER pTargetCmdBufferPostRequest_t; 3964 3965 #define CMD_BUFFER_POST_FLAGS_PORT_MASK (0x01) 3966 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_MASK (0x80) 3967 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_32 (0) 3968 #define CMD_BUFFER_POST_FLAGS_ADDR_MODE_64 (1) 3969 #define CMD_BUFFER_POST_FLAGS_64_BIT_ADDR (0x80) 3970 3971 #define CMD_BUFFER_POST_IO_INDEX_MASK (0x00003FFF) 3972 #define CMD_BUFFER_POST_IO_INDEX_MASK_0100 (0x000003FF) /* obsolete */ 3973 3974 3975 typedef struct _MSG_TARGET_CMD_BUFFER_POST_REPLY 3976 { 3977 U8 BufferPostFlags; /* 00h */ 3978 U8 BufferCount; /* 01h */ 3979 U8 MsgLength; /* 02h */ 3980 U8 Function; /* 03h */ 3981 U8 BufferLength; /* 04h */ 3982 U8 Reserved; /* 05h */ 3983 U8 Reserved1; /* 06h */ 3984 U8 MsgFlags; /* 07h */ 3985 U32 MsgContext; /* 08h */ 3986 U16 Reserved2; /* 0Ch */ 3987 U16 IOCStatus; /* 0Eh */ 3988 U32 IOCLogInfo; /* 10h */ 3989 } MSG_TARGET_CMD_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REPLY, 3990 TargetCmdBufferPostReply_t, MPI_POINTER pTargetCmdBufferPostReply_t; 3991 3992 /* the following structure is obsolete as of MPI v1.2 */ 3993 typedef struct _MSG_PRIORITY_CMD_RECEIVED_REPLY 3994 { 3995 U16 Reserved; /* 00h */ 3996 U8 MsgLength; /* 02h */ 3997 U8 Function; /* 03h */ 3998 U16 Reserved1; /* 04h */ 3999 U8 Reserved2; /* 06h */ 4000 U8 MsgFlags; /* 07h */ 4001 U32 MsgContext; /* 08h */ 4002 U8 PriorityReason; /* 0Ch */ 4003 U8 Reserved3; /* 0Dh */ 4004 U16 IOCStatus; /* 0Eh */ 4005 U32 IOCLogInfo; /* 10h */ 4006 U32 ReplyWord; /* 14h */ 4007 } MSG_PRIORITY_CMD_RECEIVED_REPLY, MPI_POINTER PTR_MSG_PRIORITY_CMD_RECEIVED_REPLY, 4008 PriorityCommandReceivedReply_t, MPI_POINTER pPriorityCommandReceivedReply_t; 4009 4010 #define PRIORITY_REASON_NO_DISCONNECT (0x00) 4011 #define PRIORITY_REASON_SCSI_TASK_MANAGEMENT (0x01) 4012 #define PRIORITY_REASON_CMD_PARITY_ERR (0x02) 4013 #define PRIORITY_REASON_MSG_OUT_PARITY_ERR (0x03) 4014 #define PRIORITY_REASON_LQ_CRC_ERR (0x04) 4015 #define PRIORITY_REASON_CMD_CRC_ERR (0x05) 4016 #define PRIORITY_REASON_PROTOCOL_ERR (0x06) 4017 #define PRIORITY_REASON_DATA_OUT_PARITY_ERR (0x07) 4018 #define PRIORITY_REASON_DATA_OUT_CRC_ERR (0x08) 4019 #define PRIORITY_REASON_UNKNOWN (0xFF) 4020 4021 4022 typedef struct _MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY 4023 { 4024 U16 Reserved; /* 00h */ 4025 U8 MsgLength; /* 02h */ 4026 U8 Function; /* 03h */ 4027 U16 Reserved1; /* 04h */ 4028 U8 Reserved2; /* 06h */ 4029 U8 MsgFlags; /* 07h */ 4030 U32 MsgContext; /* 08h */ 4031 U8 PriorityReason; /* 0Ch */ 4032 U8 Reserved3; /* 0Dh */ 4033 U16 IOCStatus; /* 0Eh */ 4034 U32 IOCLogInfo; /* 10h */ 4035 U32 ReplyWord; /* 14h */ 4036 } MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, 4037 MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, 4038 TargetCmdBufferPostErrorReply_t, MPI_POINTER pTargetCmdBufferPostErrorReply_t; 4039 4040 4041 typedef struct _MPI_TARGET_FCP_CMD_BUFFER 4042 { 4043 U8 FcpLun[8]; /* 00h */ 4044 U8 FcpCntl[4]; /* 08h */ 4045 U8 FcpCdb[16]; /* 0Ch */ 4046 U32 FcpDl; /* 1Ch */ 4047 } MPI_TARGET_FCP_CMD_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_CMD_BUFFER, 4048 MpiTargetFcpCmdBuffer, MPI_POINTER pMpiTargetFcpCmdBuffer; 4049 4050 4051 typedef struct _MPI_TARGET_SCSI_SPI_CMD_BUFFER 4052 { 4053 /* SPI L_Q information unit */ 4054 U8 L_QType; /* 00h */ 4055 U8 Reserved; /* 01h */ 4056 U16 Tag; /* 02h */ 4057 U8 LogicalUnitNumber[8]; /* 04h */ 4058 U32 DataLength; /* 0Ch */ 4059 /* SPI command information unit */ 4060 U8 ReservedFirstByteOfCommandIU; /* 10h */ 4061 U8 TaskAttribute; /* 11h */ 4062 U8 TaskManagementFlags; /* 12h */ 4063 U8 AdditionalCDBLength; /* 13h */ 4064 U8 CDB[16]; /* 14h */ 4065 } MPI_TARGET_SCSI_SPI_CMD_BUFFER, 4066 MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_CMD_BUFFER, 4067 MpiTargetScsiSpiCmdBuffer, MPI_POINTER pMpiTargetScsiSpiCmdBuffer; 4068 4069 4070 /****************************************************************************/ 4071 /* Target Assist Request */ 4072 /****************************************************************************/ 4073 4074 typedef struct _MSG_TARGET_ASSIST_REQUEST 4075 { 4076 U8 StatusCode; /* 00h */ 4077 U8 TargetAssistFlags; /* 01h */ 4078 U8 ChainOffset; /* 02h */ 4079 U8 Function; /* 03h */ 4080 U16 QueueTag; /* 04h */ 4081 U8 Reserved; /* 06h */ 4082 U8 MsgFlags; /* 07h */ 4083 U32 MsgContext; /* 08h */ 4084 U32 ReplyWord; /* 0Ch */ 4085 U8 LUN[8]; /* 10h */ 4086 U32 RelativeOffset; /* 18h */ 4087 U32 DataLength; /* 1Ch */ 4088 SGE_IO_UNION SGL[1]; /* 20h */ 4089 } MSG_TARGET_ASSIST_REQUEST, MPI_POINTER PTR_MSG_TARGET_ASSIST_REQUEST, 4090 TargetAssistRequest_t, MPI_POINTER pTargetAssistRequest_t; 4091 4092 #define TARGET_ASSIST_FLAGS_DATA_DIRECTION (0x01) 4093 #define TARGET_ASSIST_FLAGS_AUTO_STATUS (0x02) 4094 #define TARGET_ASSIST_FLAGS_HIGH_PRIORITY (0x04) 4095 #define TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x80) 4096 4097 4098 typedef struct _MSG_TARGET_ERROR_REPLY 4099 { 4100 U16 Reserved; /* 00h */ 4101 U8 MsgLength; /* 02h */ 4102 U8 Function; /* 03h */ 4103 U16 Reserved1; /* 04h */ 4104 U8 Reserved2; /* 06h */ 4105 U8 MsgFlags; /* 07h */ 4106 U32 MsgContext; /* 08h */ 4107 U8 PriorityReason; /* 0Ch */ 4108 U8 Reserved3; /* 0Dh */ 4109 U16 IOCStatus; /* 0Eh */ 4110 U32 IOCLogInfo; /* 10h */ 4111 U32 ReplyWord; /* 14h */ 4112 U32 TransferCount; /* 18h */ 4113 } MSG_TARGET_ERROR_REPLY, MPI_POINTER PTR_MSG_TARGET_ERROR_REPLY, 4114 TargetErrorReply_t, MPI_POINTER pTargetErrorReply_t; 4115 4116 4117 /****************************************************************************/ 4118 /* Target Status Send Request */ 4119 /****************************************************************************/ 4120 4121 typedef struct _MSG_TARGET_STATUS_SEND_REQUEST 4122 { 4123 U8 StatusCode; /* 00h */ 4124 U8 StatusFlags; /* 01h */ 4125 U8 ChainOffset; /* 02h */ 4126 U8 Function; /* 03h */ 4127 U16 QueueTag; /* 04h */ 4128 U8 Reserved; /* 06h */ 4129 U8 MsgFlags; /* 07h */ 4130 U32 MsgContext; /* 08h */ 4131 U32 ReplyWord; /* 0Ch */ 4132 U8 LUN[8]; /* 10h */ 4133 SGE_SIMPLE_UNION StatusDataSGE; /* 18h */ 4134 } MSG_TARGET_STATUS_SEND_REQUEST, MPI_POINTER PTR_MSG_TARGET_STATUS_SEND_REQUEST, 4135 TargetStatusSendRequest_t, MPI_POINTER pTargetStatusSendRequest_t; 4136 4137 #define TARGET_STATUS_SEND_FLAGS_AUTO_GOOD_STATUS (0x01) 4138 #define TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY (0x04) 4139 #define TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER (0x80) 4140 4141 typedef struct _MPI_TARGET_FCP_RSP_BUFFER 4142 { 4143 U8 Reserved0[8]; /* 00h */ 4144 U8 FcpStatus; /* 08h */ 4145 U8 FcpFlags; /* 09h */ 4146 U8 Reserved1[2]; /* 0Ah */ 4147 U32 FcpResid; /* 0Ch */ 4148 U32 FcpSenseLength; /* 10h */ 4149 U32 FcpResponseLength; /* 14h */ 4150 U8 FcpResponseData[8]; /* 18h */ 4151 U8 FcpSenseData[32]; /* Pad to 64 bytes */ /* 20h */ 4152 } MPI_TARGET_FCP_RSP_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_RSP_BUFFER, 4153 MpiTargetFcpRspBuffer, MPI_POINTER pMpiTargetFcpRspBuffer; 4154 4155 typedef struct _MPI_TARGET_SCSI_SPI_STATUS_IU 4156 { 4157 U8 Reserved0; /* 00h */ 4158 U8 Reserved1; /* 01h */ 4159 U8 Valid; /* 02h */ 4160 U8 Status; /* 03h */ 4161 U32 SenseDataListLength; /* 04h */ 4162 U32 PktFailuresListLength; /* 08h */ 4163 U8 SenseData[52]; /* Pad the IU to 64 bytes */ /* 0Ch */ 4164 } MPI_TARGET_SCSI_SPI_STATUS_IU, MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_STATUS_IU, 4165 TargetScsiSpiStatusIU_t, MPI_POINTER pTargetScsiSpiStatusIU_t; 4166 4167 /****************************************************************************/ 4168 /* Target Mode Abort Request */ 4169 /****************************************************************************/ 4170 4171 typedef struct _MSG_TARGET_MODE_ABORT_REQUEST 4172 { 4173 U8 AbortType; /* 00h */ 4174 U8 Reserved; /* 01h */ 4175 U8 ChainOffset; /* 02h */ 4176 U8 Function; /* 03h */ 4177 U16 Reserved1; /* 04h */ 4178 U8 Reserved2; /* 06h */ 4179 U8 MsgFlags; /* 07h */ 4180 U32 MsgContext; /* 08h */ 4181 U32 ReplyWord; /* 0Ch */ 4182 U32 MsgContextToAbort; /* 10h */ 4183 } MSG_TARGET_MODE_ABORT, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT, 4184 TargetModeAbort_t, MPI_POINTER pTargetModeAbort_t; 4185 4186 #define TARGET_MODE_ABORT_TYPE_ALL_CMD_BUFFERS (0x00) 4187 #define TARGET_MODE_ABORT_TYPE_ALL_IO (0x01) 4188 #define TARGET_MODE_ABORT_TYPE_EXACT_IO (0x02) 4189 #define TARGET_MODE_ABORT_TYPE_EXACT_IO_REQUEST (0x03) 4190 4191 /* Target Mode Abort Reply */ 4192 4193 typedef struct _MSG_TARGET_MODE_ABORT_REPLY 4194 { 4195 U16 Reserved; /* 00h */ 4196 U8 MsgLength; /* 02h */ 4197 U8 Function; /* 03h */ 4198 U16 Reserved1; /* 04h */ 4199 U8 Reserved2; /* 06h */ 4200 U8 MsgFlags; /* 07h */ 4201 U32 MsgContext; /* 08h */ 4202 U16 Reserved3; /* 0Ch */ 4203 U16 IOCStatus; /* 0Eh */ 4204 U32 IOCLogInfo; /* 10h */ 4205 U32 AbortCount; /* 14h */ 4206 } MSG_TARGET_MODE_ABORT_REPLY, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT_REPLY, 4207 TargetModeAbortReply_t, MPI_POINTER pTargetModeAbortReply_t; 4208 4209 4210 /****************************************************************************/ 4211 /* Target Mode Context Reply */ 4212 /****************************************************************************/ 4213 4214 #define TARGET_MODE_REPLY_IO_INDEX_MASK (0x00003FFF) 4215 #define TARGET_MODE_REPLY_IO_INDEX_SHIFT (0) 4216 #define TARGET_MODE_REPLY_INITIATOR_INDEX_MASK (0x03FFC000) 4217 #define TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT (14) 4218 #define TARGET_MODE_REPLY_ALIAS_MASK (0x0C000000) 4219 #define TARGET_MODE_REPLY_ALIAS_SHIFT (26) 4220 #define TARGET_MODE_REPLY_PORT_MASK (0x10000000) 4221 #define TARGET_MODE_REPLY_PORT_SHIFT (28) 4222 4223 4224 #define GET_IO_INDEX(x) (((x) & TARGET_MODE_REPLY_IO_INDEX_MASK) \ 4225 >> TARGET_MODE_REPLY_IO_INDEX_SHIFT) 4226 4227 #define SET_IO_INDEX(t, i) \ 4228 ((t) = ((t) & ~TARGET_MODE_REPLY_IO_INDEX_MASK) | \ 4229 (((i) << TARGET_MODE_REPLY_IO_INDEX_SHIFT) & \ 4230 TARGET_MODE_REPLY_IO_INDEX_MASK)) 4231 4232 #define GET_INITIATOR_INDEX(x) (((x) & TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) \ 4233 >> TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) 4234 4235 #define SET_INITIATOR_INDEX(t, ii) \ 4236 ((t) = ((t) & ~TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) | \ 4237 (((ii) << TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) & \ 4238 TARGET_MODE_REPLY_INITIATOR_INDEX_MASK)) 4239 4240 #define GET_ALIAS(x) (((x) & TARGET_MODE_REPLY_ALIAS_MASK) \ 4241 >> TARGET_MODE_REPLY_ALIAS_SHIFT) 4242 4243 #define SET_ALIAS(t, a) ((t) = ((t) & ~TARGET_MODE_REPLY_ALIAS_MASK) | \ 4244 (((a) << TARGET_MODE_REPLY_ALIAS_SHIFT) & \ 4245 TARGET_MODE_REPLY_ALIAS_MASK)) 4246 4247 #define GET_PORT(x) (((x) & TARGET_MODE_REPLY_PORT_MASK) \ 4248 >> TARGET_MODE_REPLY_PORT_SHIFT) 4249 4250 #define SET_PORT(t, p) ((t) = ((t) & ~TARGET_MODE_REPLY_PORT_MASK) | \ 4251 (((p) << TARGET_MODE_REPLY_PORT_SHIFT) & \ 4252 TARGET_MODE_REPLY_PORT_MASK)) 4253 4254 /* the following obsolete values are for MPI v1.0 support */ 4255 #define TARGET_MODE_REPLY_0100_MASK_HOST_INDEX (0x000003FF) 4256 #define TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX (0) 4257 #define TARGET_MODE_REPLY_0100_MASK_IOC_INDEX (0x001FF800) 4258 #define TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX (11) 4259 #define TARGET_MODE_REPLY_0100_PORT_MASK (0x00400000) 4260 #define TARGET_MODE_REPLY_0100_PORT_SHIFT (22) 4261 #define TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX (0x1F800000) 4262 #define TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX (23) 4263 4264 #define GET_HOST_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) \ 4265 >> TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) 4266 4267 #define SET_HOST_INDEX_0100(t, hi) \ 4268 ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) | \ 4269 (((hi) << TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) & \ 4270 TARGET_MODE_REPLY_0100_MASK_HOST_INDEX)) 4271 4272 #define GET_IOC_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) \ 4273 >> TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) 4274 4275 #define SET_IOC_INDEX_0100(t, ii) \ 4276 ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) | \ 4277 (((ii) << TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) & \ 4278 TARGET_MODE_REPLY_0100_MASK_IOC_INDEX)) 4279 4280 #define GET_INITIATOR_INDEX_0100(x) \ 4281 (((x) & TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) \ 4282 >> TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) 4283 4284 #define SET_INITIATOR_INDEX_0100(t, ii) \ 4285 ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) | \ 4286 (((ii) << TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) & \ 4287 TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX)) 4288 4289 4290 #endif 4291 4292
Indexes created Sun Sep 21 20:09:37 GMT 2025