1 //===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone helper functions and enum definitions for 10 // the Hexagon target useful for the compiler back-end and the MC libraries. 11 // As such, it deliberately does not include references to LLVM core 12 // code gen types, passes, etc.. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 17 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 18 19 #include "HexagonDepITypes.h" 20 #include "MCTargetDesc/HexagonMCTargetDesc.h" 21 22 namespace llvm { 23 24 /// HexagonII - This namespace holds all of the target specific flags that 25 /// instruction info tracks. 26 namespace HexagonII { 27 unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY; 28 unsigned const TypeCVI_LAST = TypeCVI_ZW; 29 30 enum AddrMode { 31 NoAddrMode = 0, // No addressing mode 32 Absolute = 1, // Absolute addressing mode 33 AbsoluteSet = 2, // Absolute set addressing mode 34 BaseImmOffset = 3, // Indirect with offset 35 BaseLongOffset = 4, // Indirect with long offset 36 BaseRegOffset = 5, // Indirect with register offset 37 PostInc = 6 // Post increment addressing mode 38 }; 39 40 enum MemAccessSize { 41 NoMemAccess = 0, 42 ByteAccess, 43 HalfWordAccess, 44 WordAccess, 45 DoubleWordAccess, 46 HVXVectorAccess 47 }; 48 49 // MCInstrDesc TSFlags 50 // *** Must match HexagonInstrFormat*.td *** 51 enum { 52 // This 7-bit field describes the insn type. 53 TypePos = 0, 54 TypeMask = 0x7f, 55 56 // Solo instructions. 57 SoloPos = 7, 58 SoloMask = 0x1, 59 // Packed only with A or X-type instructions. 60 SoloAXPos = 8, 61 SoloAXMask = 0x1, 62 // Only A-type instruction in first slot or nothing. 63 RestrictSlot1AOKPos = 9, 64 RestrictSlot1AOKMask = 0x1, 65 66 // Predicated instructions. 67 PredicatedPos = 10, 68 PredicatedMask = 0x1, 69 PredicatedFalsePos = 11, 70 PredicatedFalseMask = 0x1, 71 PredicatedNewPos = 12, 72 PredicatedNewMask = 0x1, 73 PredicateLatePos = 13, 74 PredicateLateMask = 0x1, 75 76 // New-Value consumer instructions. 77 NewValuePos = 14, 78 NewValueMask = 0x1, 79 // New-Value producer instructions. 80 hasNewValuePos = 15, 81 hasNewValueMask = 0x1, 82 // Which operand consumes or produces a new value. 83 NewValueOpPos = 16, 84 NewValueOpMask = 0x7, 85 // Stores that can become new-value stores. 86 mayNVStorePos = 19, 87 mayNVStoreMask = 0x1, 88 // New-value store instructions. 89 NVStorePos = 20, 90 NVStoreMask = 0x1, 91 // Loads that can become current-value loads. 92 mayCVLoadPos = 21, 93 mayCVLoadMask = 0x1, 94 // Current-value load instructions. 95 CVLoadPos = 22, 96 CVLoadMask = 0x1, 97 98 // Extendable insns. 99 ExtendablePos = 23, 100 ExtendableMask = 0x1, 101 // Insns must be extended. 102 ExtendedPos = 24, 103 ExtendedMask = 0x1, 104 // Which operand may be extended. 105 ExtendableOpPos = 25, 106 ExtendableOpMask = 0x7, 107 // Signed or unsigned range. 108 ExtentSignedPos = 28, 109 ExtentSignedMask = 0x1, 110 // Number of bits of range before extending operand. 111 ExtentBitsPos = 29, 112 ExtentBitsMask = 0x1f, 113 // Alignment power-of-two before extending operand. 114 ExtentAlignPos = 34, 115 ExtentAlignMask = 0x3, 116 117 CofMax1Pos = 36, 118 CofMax1Mask = 0x1, 119 CofRelax1Pos = 37, 120 CofRelax1Mask = 0x1, 121 CofRelax2Pos = 38, 122 CofRelax2Mask = 0x1, 123 124 RestrictNoSlot1StorePos = 39, 125 RestrictNoSlot1StoreMask = 0x1, 126 127 // Addressing mode for load/store instructions. 128 AddrModePos = 42, 129 AddrModeMask = 0x7, 130 // Access size for load/store instructions. 131 MemAccessSizePos = 45, 132 MemAccesSizeMask = 0xf, 133 134 // Branch predicted taken. 135 TakenPos = 49, 136 TakenMask = 0x1, 137 138 // Floating-point instructions. 139 FPPos = 50, 140 FPMask = 0x1, 141 142 // New-Value producer-2 instructions. 143 hasNewValuePos2 = 52, 144 hasNewValueMask2 = 0x1, 145 // Which operand consumes or produces a new value. 146 NewValueOpPos2 = 53, 147 NewValueOpMask2 = 0x7, 148 149 // Accumulator instructions. 150 AccumulatorPos = 56, 151 AccumulatorMask = 0x1, 152 153 // Complex XU, prevent xu competition by preferring slot3 154 PrefersSlot3Pos = 57, 155 PrefersSlot3Mask = 0x1, 156 157 // v65 158 HasTmpDstPos = 60, 159 HasTmpDstMask = 0x1, 160 161 CVINewPos = 62, 162 CVINewMask = 0x1, 163 164 isCVIPos = 63, 165 isCVIMask = 0x1, 166 }; 167 168 // *** The code above must match HexagonInstrFormat*.td *** // 169 170 // Hexagon specific MO operand flag mask. 171 enum HexagonMOTargetFlagVal { 172 // Hexagon-specific MachineOperand target flags. 173 // 174 // When changing these, make sure to update 175 // getSerializableDirectMachineOperandTargetFlags and 176 // getSerializableBitmaskMachineOperandTargetFlags if needed. 177 MO_NO_FLAG, 178 179 /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation 180 /// Used for computing a global address for PIC compilations 181 MO_PCREL, 182 183 /// MO_GOT - Indicates a GOT-relative relocation 184 MO_GOT, 185 186 // Low or high part of a symbol. 187 MO_LO16, 188 MO_HI16, 189 190 // Offset from the base of the SDA. 191 MO_GPREL, 192 193 // MO_GDGOT - indicates GOT relative relocation for TLS 194 // GeneralDynamic method 195 MO_GDGOT, 196 197 // MO_GDPLT - indicates PLT relative relocation for TLS 198 // GeneralDynamic method 199 MO_GDPLT, 200 201 // MO_IE - indicates non PIC relocation for TLS 202 // Initial Executable method 203 MO_IE, 204 205 // MO_IEGOT - indicates PIC relocation for TLS 206 // Initial Executable method 207 MO_IEGOT, 208 209 // MO_TPREL - indicates relocation for TLS 210 // local Executable method 211 MO_TPREL, 212 213 // HMOTF_ConstExtended 214 // Addendum to above, indicates a const extended op 215 // Can be used as a mask. 216 HMOTF_ConstExtended = 0x80, 217 218 // Union of all bitmasks (currently only HMOTF_ConstExtended). 219 MO_Bitmasks = HMOTF_ConstExtended 220 }; 221 222 // Hexagon Sub-instruction classes. 223 enum SubInstructionGroup { 224 HSIG_None = 0, 225 HSIG_L1, 226 HSIG_L2, 227 HSIG_S1, 228 HSIG_S2, 229 HSIG_A, 230 HSIG_Compound 231 }; 232 233 // Hexagon Compound classes. 234 enum CompoundGroup { 235 HCG_None = 0, 236 HCG_A, 237 HCG_B, 238 HCG_C 239 }; 240 241 enum InstParseBits { 242 INST_PARSE_MASK = 0x0000c000, 243 INST_PARSE_PACKET_END = 0x0000c000, 244 INST_PARSE_LOOP_END = 0x00008000, 245 INST_PARSE_NOT_END = 0x00004000, 246 INST_PARSE_DUPLEX = 0x00000000, 247 INST_PARSE_EXTENDER = 0x00000000 248 }; 249 250 enum InstIClassBits : unsigned { 251 INST_ICLASS_MASK = 0xf0000000, 252 INST_ICLASS_EXTENDER = 0x00000000, 253 INST_ICLASS_J_1 = 0x10000000, 254 INST_ICLASS_J_2 = 0x20000000, 255 INST_ICLASS_LD_ST_1 = 0x30000000, 256 INST_ICLASS_LD_ST_2 = 0x40000000, 257 INST_ICLASS_J_3 = 0x50000000, 258 INST_ICLASS_CR = 0x60000000, 259 INST_ICLASS_ALU32_1 = 0x70000000, 260 INST_ICLASS_XTYPE_1 = 0x80000000, 261 INST_ICLASS_LD = 0x90000000, 262 INST_ICLASS_ST = 0xa0000000, 263 INST_ICLASS_ALU32_2 = 0xb0000000, 264 INST_ICLASS_XTYPE_2 = 0xc0000000, 265 INST_ICLASS_XTYPE_3 = 0xd0000000, 266 INST_ICLASS_XTYPE_4 = 0xe0000000, 267 INST_ICLASS_ALU32_3 = 0xf0000000 268 }; 269 270 LLVM_ATTRIBUTE_UNUSED 271 static unsigned getMemAccessSizeInBytes(MemAccessSize S) { 272 switch (S) { 273 case ByteAccess: return 1; 274 case HalfWordAccess: return 2; 275 case WordAccess: return 4; 276 case DoubleWordAccess: return 8; 277 default: return 0; 278 } 279 } 280 } // end namespace HexagonII 281 282 } // end namespace llvm 283 284 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 285
Indexes created Sun Jun 07 00:24:08 UTC 2026