1 /* 2 * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, 3 * Precision Insight, Inc., Cedar Park, Texas, and 4 * VA Linux Systems Inc., Fremont, California. 5 * 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining 9 * a copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation on the rights to use, copy, modify, merge, 12 * publish, distribute, sublicense, and/or sell copies of the Software, 13 * and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial 18 * portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 23 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX 24 * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 25 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 26 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 27 * OTHER DEALINGS IN THE SOFTWARE. 28 */ 29 30 /* 31 * Authors: 32 * Rickard E. Faith <faith (at) valinux.com> 33 * Kevin E. Martin <martin (at) valinux.com> 34 * Gareth Hughes <gareth (at) valinux.com> 35 * 36 * References: 37 * 38 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 39 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 40 * 1999. 41 * 42 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 43 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 44 * 45 */ 46 47 #ifndef _R128_REG_H_ 48 #define _R128_REG_H_ 49 50 #include "compiler.h" 51 52 /* Memory mapped register access macros */ 53 #define INREG8(addr) MMIO_IN8(R128MMIO, addr) 54 #define INREG16(addr) MMIO_IN16(R128MMIO, addr) 55 #define INREG(addr) MMIO_IN32(R128MMIO, addr) 56 #define OUTREG8(addr, val) MMIO_OUT8(R128MMIO, addr, val) 57 #define OUTREG16(addr, val) MMIO_OUT16(R128MMIO, addr, val) 58 #define OUTREG(addr, val) MMIO_OUT32(R128MMIO, addr, val) 59 60 #define ADDRREG(addr) ((volatile uint32_t *)(pointer)(R128MMIO + (addr))) 61 62 63 #define OUTREGP(addr, val, mask) \ 64 do { \ 65 uint32_t tmp = INREG(addr); \ 66 tmp &= (mask); \ 67 tmp |= ((val) & ~(mask)); \ 68 OUTREG(addr, tmp); \ 69 } while (0) 70 71 #define INPLL(pScrn, addr) R128INPLL(pScrn, addr) 72 73 #define OUTPLL(addr, val) \ 74 do { \ 75 OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x3f) | R128_PLL_WR_EN); \ 76 OUTREG(R128_CLOCK_CNTL_DATA, val); \ 77 } while (0) 78 79 #define OUTPLLP(pScrn, addr, val, mask) \ 80 do { \ 81 uint32_t tmp = INPLL(pScrn, addr); \ 82 tmp &= (mask); \ 83 tmp |= ((val) & ~(mask)); \ 84 OUTPLL(addr, tmp); \ 85 } while (0) 86 87 #define OUTPAL_START(idx) \ 88 do { \ 89 OUTREG8(R128_PALETTE_INDEX, (idx)); \ 90 } while (0) 91 92 #define OUTPAL_NEXT(r, g, b) \ 93 do { \ 94 OUTREG(R128_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \ 95 } while (0) 96 97 #define OUTPAL_NEXT_uint32_t(v) \ 98 do { \ 99 OUTREG(R128_PALETTE_DATA, (v & 0x00ffffff)); \ 100 } while (0) 101 102 #define OUTPAL(idx, r, g, b) \ 103 do { \ 104 OUTPAL_START((idx)); \ 105 OUTPAL_NEXT((r), (g), (b)); \ 106 } while (0) 107 108 #define INPAL_START(idx) \ 109 do { \ 110 OUTREG(R128_PALETTE_INDEX, (idx) << 16); \ 111 } while (0) 112 113 #define INPAL_NEXT() INREG(R128_PALETTE_DATA) 114 115 #define PAL_SELECT(idx) \ 116 do { \ 117 uint32_t tmp = INREG(R128_DAC_CNTL); \ 118 if (idx) { \ 119 OUTREG(R128_DAC_CNTL, tmp | R128_DAC_PALETTE_ACC_CTL); \ 120 } else { \ 121 OUTREG(R128_DAC_CNTL, tmp & \ 122 (uint32_t)~R128_DAC_PALETTE_ACC_CTL); \ 123 } \ 124 } while (0) 125 126 #define R128_ADAPTER_ID 0x0f2c /* PCI */ 127 #define R128_AGP_APER_OFFSET 0x0178 128 #define R128_AGP_BASE 0x0170 129 #define R128_AGP_CNTL 0x0174 130 # define R128_AGP_APER_SIZE_256MB (0x00 << 0) 131 # define R128_AGP_APER_SIZE_128MB (0x20 << 0) 132 # define R128_AGP_APER_SIZE_64MB (0x30 << 0) 133 # define R128_AGP_APER_SIZE_32MB (0x38 << 0) 134 # define R128_AGP_APER_SIZE_16MB (0x3c << 0) 135 # define R128_AGP_APER_SIZE_8MB (0x3e << 0) 136 # define R128_AGP_APER_SIZE_4MB (0x3f << 0) 137 # define R128_AGP_APER_SIZE_MASK (0x3f << 0) 138 #define R128_AGP_CNTL_B 0x0b44 139 #define R128_AGP_COMMAND 0x0f58 /* PCI */ 140 #define R128_AGP_PLL_CNTL 0x0010 /* PLL */ 141 #define R128_AGP_STATUS 0x0f54 /* PCI */ 142 # define R128_AGP_1X_MODE 0x01 143 # define R128_AGP_2X_MODE 0x02 144 # define R128_AGP_4X_MODE 0x04 145 # define R128_AGP_MODE_MASK 0x07 146 #define R128_AMCGPIO_A_REG 0x01a0 147 #define R128_AMCGPIO_EN_REG 0x01a8 148 #define R128_AMCGPIO_MASK 0x0194 149 #define R128_AMCGPIO_Y_REG 0x01a4 150 #define R128_ATTRDR 0x03c1 /* VGA */ 151 #define R128_ATTRDW 0x03c0 /* VGA */ 152 #define R128_ATTRX 0x03c0 /* VGA */ 153 #define R128_AUX_SC_CNTL 0x1660 154 # define R128_AUX1_SC_EN (1 << 0) 155 # define R128_AUX1_SC_MODE_OR (0 << 1) 156 # define R128_AUX1_SC_MODE_NAND (1 << 1) 157 # define R128_AUX2_SC_EN (1 << 2) 158 # define R128_AUX2_SC_MODE_OR (0 << 3) 159 # define R128_AUX2_SC_MODE_NAND (1 << 3) 160 # define R128_AUX3_SC_EN (1 << 4) 161 # define R128_AUX3_SC_MODE_OR (0 << 5) 162 # define R128_AUX3_SC_MODE_NAND (1 << 5) 163 #define R128_AUX1_SC_BOTTOM 0x1670 164 #define R128_AUX1_SC_LEFT 0x1664 165 #define R128_AUX1_SC_RIGHT 0x1668 166 #define R128_AUX1_SC_TOP 0x166c 167 #define R128_AUX2_SC_BOTTOM 0x1680 168 #define R128_AUX2_SC_LEFT 0x1674 169 #define R128_AUX2_SC_RIGHT 0x1678 170 #define R128_AUX2_SC_TOP 0x167c 171 #define R128_AUX3_SC_BOTTOM 0x1690 172 #define R128_AUX3_SC_LEFT 0x1684 173 #define R128_AUX3_SC_RIGHT 0x1688 174 #define R128_AUX3_SC_TOP 0x168c 175 #define R128_AUX_WINDOW_HORZ_CNTL 0x02d8 176 #define R128_AUX_WINDOW_VERT_CNTL 0x02dc 177 178 #define R128_BASE_CODE 0x0f0b 179 #define R128_BIOS_0_SCRATCH 0x0010 180 #define R128_BIOS_1_SCRATCH 0x0014 181 #define R128_BIOS_2_SCRATCH 0x0018 182 #define R128_BIOS_3_SCRATCH 0x001c 183 #define R128_BIOS_4_SCRATCH 0x0020 184 #define R128_BIOS_5_SCRATCH 0x0024 185 # define R128_BIOS_DISPLAY_FP (1 << 0) 186 # define R128_BIOS_DISPLAY_CRT (2 << 0) 187 # define R128_BIOS_DISPLAY_FP_CRT (3 << 0) 188 /* R128_DUALHEAD is just a flag for the driver; 189 it doesn't actually correspond to any bits */ 190 # define R128_DUALHEAD 4 191 #define R128_BIOS_6_SCRATCH 0x0028 192 #define R128_BIOS_7_SCRATCH 0x002c 193 #define R128_BIOS_ROM 0x0f30 /* PCI */ 194 #define R128_BIST 0x0f0f /* PCI */ 195 #define R128_BM_CHUNK_0_VAL 0x0a18 196 # define R128_BM_PTR_FORCE_TO_PCI (1 << 21) 197 # define R128_BM_PM4_RD_FORCE_TO_PCI (1 << 22) 198 # define R128_BM_GLOBAL_FORCE_TO_PCI (1 << 23) 199 #define R128_BRUSH_DATA0 0x1480 200 #define R128_BRUSH_DATA1 0x1484 201 #define R128_BRUSH_DATA10 0x14a8 202 #define R128_BRUSH_DATA11 0x14ac 203 #define R128_BRUSH_DATA12 0x14b0 204 #define R128_BRUSH_DATA13 0x14b4 205 #define R128_BRUSH_DATA14 0x14b8 206 #define R128_BRUSH_DATA15 0x14bc 207 #define R128_BRUSH_DATA16 0x14c0 208 #define R128_BRUSH_DATA17 0x14c4 209 #define R128_BRUSH_DATA18 0x14c8 210 #define R128_BRUSH_DATA19 0x14cc 211 #define R128_BRUSH_DATA2 0x1488 212 #define R128_BRUSH_DATA20 0x14d0 213 #define R128_BRUSH_DATA21 0x14d4 214 #define R128_BRUSH_DATA22 0x14d8 215 #define R128_BRUSH_DATA23 0x14dc 216 #define R128_BRUSH_DATA24 0x14e0 217 #define R128_BRUSH_DATA25 0x14e4 218 #define R128_BRUSH_DATA26 0x14e8 219 #define R128_BRUSH_DATA27 0x14ec 220 #define R128_BRUSH_DATA28 0x14f0 221 #define R128_BRUSH_DATA29 0x14f4 222 #define R128_BRUSH_DATA3 0x148c 223 #define R128_BRUSH_DATA30 0x14f8 224 #define R128_BRUSH_DATA31 0x14fc 225 #define R128_BRUSH_DATA32 0x1500 226 #define R128_BRUSH_DATA33 0x1504 227 #define R128_BRUSH_DATA34 0x1508 228 #define R128_BRUSH_DATA35 0x150c 229 #define R128_BRUSH_DATA36 0x1510 230 #define R128_BRUSH_DATA37 0x1514 231 #define R128_BRUSH_DATA38 0x1518 232 #define R128_BRUSH_DATA39 0x151c 233 #define R128_BRUSH_DATA4 0x1490 234 #define R128_BRUSH_DATA40 0x1520 235 #define R128_BRUSH_DATA41 0x1524 236 #define R128_BRUSH_DATA42 0x1528 237 #define R128_BRUSH_DATA43 0x152c 238 #define R128_BRUSH_DATA44 0x1530 239 #define R128_BRUSH_DATA45 0x1534 240 #define R128_BRUSH_DATA46 0x1538 241 #define R128_BRUSH_DATA47 0x153c 242 #define R128_BRUSH_DATA48 0x1540 243 #define R128_BRUSH_DATA49 0x1544 244 #define R128_BRUSH_DATA5 0x1494 245 #define R128_BRUSH_DATA50 0x1548 246 #define R128_BRUSH_DATA51 0x154c 247 #define R128_BRUSH_DATA52 0x1550 248 #define R128_BRUSH_DATA53 0x1554 249 #define R128_BRUSH_DATA54 0x1558 250 #define R128_BRUSH_DATA55 0x155c 251 #define R128_BRUSH_DATA56 0x1560 252 #define R128_BRUSH_DATA57 0x1564 253 #define R128_BRUSH_DATA58 0x1568 254 #define R128_BRUSH_DATA59 0x156c 255 #define R128_BRUSH_DATA6 0x1498 256 #define R128_BRUSH_DATA60 0x1570 257 #define R128_BRUSH_DATA61 0x1574 258 #define R128_BRUSH_DATA62 0x1578 259 #define R128_BRUSH_DATA63 0x157c 260 #define R128_BRUSH_DATA7 0x149c 261 #define R128_BRUSH_DATA8 0x14a0 262 #define R128_BRUSH_DATA9 0x14a4 263 #define R128_BRUSH_SCALE 0x1470 264 #define R128_BRUSH_Y_X 0x1474 265 #define R128_BUS_CNTL 0x0030 266 # define R128_BUS_MASTER_DIS (1 << 6) 267 # define R128_BUS_RD_DISCARD_EN (1 << 24) 268 # define R128_BUS_RD_ABORT_EN (1 << 25) 269 # define R128_BUS_MSTR_DISCONNECT_EN (1 << 28) 270 # define R128_BUS_WRT_BURST (1 << 29) 271 # define R128_BUS_READ_BURST (1 << 30) 272 #define R128_BUS_CNTL1 0x0034 273 # define R128_BUS_WAIT_ON_LOCK_EN (1 << 4) 274 275 #define R128_CACHE_CNTL 0x1724 276 #define R128_CACHE_LINE 0x0f0c /* PCI */ 277 #define R128_CAP0_TRIG_CNTL 0x0950 /* ? */ 278 #define R128_CAP1_TRIG_CNTL 0x09c0 /* ? */ 279 #define R128_CAPABILITIES_ID 0x0f50 /* PCI */ 280 #define R128_CAPABILITIES_PTR 0x0f34 /* PCI */ 281 #define R128_CLK_PIN_CNTL 0x0001 /* PLL */ 282 #define R128_CLOCK_CNTL_DATA 0x000c 283 #define R128_CLOCK_CNTL_INDEX 0x0008 284 # define R128_PLL_WR_EN (1 << 7) 285 # define R128_PLL_DIV_SEL (3 << 8) 286 # define R128_PLL2_DIV_SEL_MASK ~(3 << 8) 287 #define R128_CLR_CMP_CLR_3D 0x1a24 288 #define R128_CLR_CMP_CLR_DST 0x15c8 289 #define R128_CLR_CMP_CLR_SRC 0x15c4 290 #define R128_CLR_CMP_CNTL 0x15c0 291 # define R128_SRC_CMP_EQ_COLOR (4 << 0) 292 # define R128_SRC_CMP_NEQ_COLOR (5 << 0) 293 # define R128_CLR_CMP_SRC_SOURCE (1 << 24) 294 #define R128_CLR_CMP_MASK 0x15cc 295 # define R128_CLR_CMP_MSK 0xffffffff 296 #define R128_CLR_CMP_MASK_3D 0x1A28 297 #define R128_COMMAND 0x0f04 /* PCI */ 298 #define R128_COMPOSITE_SHADOW_ID 0x1a0c 299 #define R128_CONFIG_APER_0_BASE 0x0100 300 #define R128_CONFIG_APER_1_BASE 0x0104 301 #define R128_CONFIG_APER_SIZE 0x0108 302 #define R128_CONFIG_BONDS 0x00e8 303 #define R128_CONFIG_CNTL 0x00e0 304 # define APER_0_BIG_ENDIAN_16BPP_SWAP (1 << 0) 305 # define APER_0_BIG_ENDIAN_32BPP_SWAP (2 << 0) 306 #define R128_CONFIG_MEMSIZE 0x00f8 307 #define R128_CONFIG_MEMSIZE_EMBEDDED 0x0114 308 #define R128_CONFIG_REG_1_BASE 0x010c 309 #define R128_CONFIG_REG_APER_SIZE 0x0110 310 #define R128_CONFIG_XSTRAP 0x00e4 311 #define R128_CONSTANT_COLOR_C 0x1d34 312 # define R128_CONSTANT_COLOR_MASK 0x00ffffff 313 # define R128_CONSTANT_COLOR_ONE 0x00ffffff 314 # define R128_CONSTANT_COLOR_ZERO 0x00000000 315 #define R128_CRC_CMDFIFO_ADDR 0x0740 316 #define R128_CRC_CMDFIFO_DOUT 0x0744 317 #define R128_CRTC_CRNT_FRAME 0x0214 318 #define R128_CRTC_DEBUG 0x021c 319 #define R128_CRTC_EXT_CNTL 0x0054 320 # define R128_CRTC_VGA_XOVERSCAN (1 << 0) 321 # define R128_VGA_ATI_LINEAR (1 << 3) 322 # define R128_XCRT_CNT_EN (1 << 6) 323 # define R128_CRTC_HSYNC_DIS (1 << 8) 324 # define R128_CRTC_VSYNC_DIS (1 << 9) 325 # define R128_CRTC_DISPLAY_DIS (1 << 10) 326 # define R128_CRTC_CRT_ON (1 << 15) 327 # define R128_FP_OUT_EN (1 << 22) 328 # define R128_FP_ACTIVE (1 << 23) 329 #define R128_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 330 # define R128_CRTC_HSYNC_DIS_BYTE (1 << 0) 331 # define R128_CRTC_VSYNC_DIS_BYTE (1 << 1) 332 # define R128_CRTC_DISPLAY_DIS_BYTE (1 << 2) 333 #define R128_CRTC_GEN_CNTL 0x0050 334 # define R128_CRTC_DBL_SCAN_EN (1 << 0) 335 # define R128_CRTC_INTERLACE_EN (1 << 1) 336 # define R128_CRTC_CSYNC_EN (1 << 4) 337 # define R128_CRTC_CUR_EN (1 << 16) 338 # define R128_CRTC_CUR_MODE_MASK (7 << 17) 339 # define R128_CRTC_ICON_EN (1 << 20) 340 # define R128_CRTC_EXT_DISP_EN (1 << 24) 341 # define R128_CRTC_EN (1 << 25) 342 # define R128_CRTC_DISP_REQ_EN_B (1 << 26) 343 #define R128_CRTC_GUI_TRIG_VLINE 0x0218 344 #define R128_CRTC_H_SYNC_STRT_WID 0x0204 345 # define R128_CRTC_H_SYNC_STRT_PIX (0x07 << 0) 346 # define R128_CRTC_H_SYNC_STRT_CHAR (0x1ff << 3) 347 # define R128_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 348 # define R128_CRTC_H_SYNC_WID (0x3f << 16) 349 # define R128_CRTC_H_SYNC_WID_SHIFT 16 350 # define R128_CRTC_H_SYNC_POL (1 << 23) 351 #define R128_CRTC_H_TOTAL_DISP 0x0200 352 # define R128_CRTC_H_TOTAL (0x01ff << 0) 353 # define R128_CRTC_H_TOTAL_SHIFT 0 354 # define R128_CRTC_H_DISP (0x00ff << 16) 355 # define R128_CRTC_H_DISP_SHIFT 16 356 #define R128_CRTC_OFFSET 0x0224 357 #define R128_CRTC_OFFSET_CNTL 0x0228 358 #define R128_CRTC_PITCH 0x022c 359 #define R128_CRTC_STATUS 0x005c 360 # define R128_CRTC_VBLANK_SAVE (1 << 1) 361 #define R128_CRTC_V_SYNC_STRT_WID 0x020c 362 # define R128_CRTC_V_SYNC_STRT (0x7ff << 0) 363 # define R128_CRTC_V_SYNC_STRT_SHIFT 0 364 # define R128_CRTC_V_SYNC_WID (0x1f << 16) 365 # define R128_CRTC_V_SYNC_WID_SHIFT 16 366 # define R128_CRTC_V_SYNC_POL (1 << 23) 367 #define R128_CRTC_V_TOTAL_DISP 0x0208 368 # define R128_CRTC_V_TOTAL (0x07ff << 0) 369 # define R128_CRTC_V_TOTAL_SHIFT 0 370 # define R128_CRTC_V_DISP (0x07ff << 16) 371 # define R128_CRTC_V_DISP_SHIFT 16 372 #define R128_CRTC_VLINE_CRNT_VLINE 0x0210 373 # define R128_CRTC_CRNT_VLINE_MASK (0x7ff << 16) 374 #define R128_CRTC2_CRNT_FRAME 0x0314 375 #define R128_CRTC2_DEBUG 0x031c 376 #define R128_CRTC2_GEN_CNTL 0x03f8 377 # define R128_CRTC2_DBL_SCAN_EN (1 << 0) 378 # define R128_CRTC2_CUR_EN (1 << 16) 379 # define R128_CRTC2_ICON_EN (1 << 20) 380 # define R128_CRTC2_DISP_DIS (1 << 23) 381 # define R128_CRTC2_EN (1 << 25) 382 # define R128_CRTC2_DISP_REQ_EN_B (1 << 26) 383 #define R128_CRTC2_GUI_TRIG_VLINE 0x0318 384 #define R128_CRTC2_H_SYNC_STRT_WID 0x0304 385 # define R128_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) 386 # define R128_CRTC2_H_SYNC_STRT_CHAR (0x1ff << 3) 387 # define R128_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 388 # define R128_CRTC2_H_SYNC_WID (0x3f << 16) 389 # define R128_CRTC2_H_SYNC_WID_SHIFT 16 390 # define R128_CRTC2_H_SYNC_POL (1 << 23) 391 #define R128_CRTC2_H_TOTAL_DISP 0x0300 392 # define R128_CRTC2_H_TOTAL (0x01ff << 0) 393 # define R128_CRTC2_H_TOTAL_SHIFT 0 394 # define R128_CRTC2_H_DISP (0x00ff << 16) 395 # define R128_CRTC2_H_DISP_SHIFT 16 396 #define R128_CRTC2_OFFSET 0x0324 397 #define R128_CRTC2_OFFSET_CNTL 0x0328 398 # define R128_CRTC2_TILE_EN (1 << 15) 399 #define R128_CRTC2_PITCH 0x032c 400 #define R128_CRTC2_STATUS 0x03fc 401 #define R128_CRTC2_V_SYNC_STRT_WID 0x030c 402 # define R128_CRTC2_V_SYNC_STRT (0x7ff << 0) 403 # define R128_CRTC2_V_SYNC_STRT_SHIFT 0 404 # define R128_CRTC2_V_SYNC_WID (0x1f << 16) 405 # define R128_CRTC2_V_SYNC_WID_SHIFT 16 406 # define R128_CRTC2_V_SYNC_POL (1 << 23) 407 #define R128_CRTC2_V_TOTAL_DISP 0x0308 408 # define R128_CRTC2_V_TOTAL (0x07ff << 0) 409 # define R128_CRTC2_V_TOTAL_SHIFT 0 410 # define R128_CRTC2_V_DISP (0x07ff << 16) 411 # define R128_CRTC2_V_DISP_SHIFT 16 412 #define R128_CRTC2_VLINE_CRNT_VLINE 0x0310 413 #define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ 414 #define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ 415 #define R128_CUR_CLR0 0x026c 416 #define R128_CUR_CLR1 0x0270 417 #define R128_CUR_HORZ_VERT_OFF 0x0268 418 #define R128_CUR_HORZ_VERT_POSN 0x0264 419 #define R128_CUR_OFFSET 0x0260 420 # define R128_CUR_LOCK (1 << 31) 421 #define R128_CUR2_CLR0 0x036c 422 #define R128_CUR2_CLR1 0x0370 423 #define R128_CUR2_HORZ_VERT_OFF 0x0368 424 #define R128_CUR2_HORZ_VERT_POSN 0x0364 425 #define R128_CUR2_OFFSET 0x0360 426 # define R128_CUR2_LOCK (1 << 31) 427 428 #define R128_DAC_CNTL 0x0058 429 # define R128_DAC_RANGE_CNTL (3 << 0) 430 # define R128_DAC_BLANKING (1 << 2) 431 # define R128_DAC_CRT_SEL_CRTC2 (1 << 4) 432 # define R128_DAC_PALETTE_ACC_CTL (1 << 5) 433 # define R128_DAC_PALETTE2_SNOOP_EN (1 << 6) 434 # define R128_DAC_8BIT_EN (1 << 8) 435 # define R128_DAC_VGA_ADR_EN (1 << 13) 436 # define R128_DAC_MASK_ALL (0xff << 24) 437 #define R128_DAC_CRC_SIG 0x02cc 438 #define R128_DAC_DATA 0x03c9 /* VGA */ 439 #define R128_DAC_MASK 0x03c6 /* VGA */ 440 #define R128_DAC_R_INDEX 0x03c7 /* VGA */ 441 #define R128_DAC_W_INDEX 0x03c8 /* VGA */ 442 #define R128_DDA_CONFIG 0x02e0 443 #define R128_DDA_ON_OFF 0x02e4 444 #define R128_DDA2_CONFIG 0x03e0 445 #define R128_DDA2_ON_OFF 0x03e4 446 #define R128_DEFAULT_OFFSET 0x16e0 447 #define R128_DEFAULT_PITCH 0x16e4 448 #define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 449 # define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 450 # define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 451 #define R128_DEFAULT2_OFFSET 0x16f8 452 #define R128_DEFAULT2_PITCH 0x16fc 453 #define R128_DEFAULT2_SC_BOTTOM_RIGHT 0x16dc 454 #define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820 455 #define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824 456 #define R128_DEVICE_ID 0x0f02 /* PCI */ 457 #define R128_DP_BRUSH_BKGD_CLR 0x1478 458 #define R128_DP_BRUSH_FRGD_CLR 0x147c 459 #define R128_DP_CNTL 0x16c0 460 # define R128_DST_X_LEFT_TO_RIGHT (1 << 0) 461 # define R128_DST_Y_TOP_TO_BOTTOM (1 << 1) 462 #define R128_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 463 # define R128_DST_Y_MAJOR (1 << 2) 464 # define R128_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) 465 # define R128_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) 466 #define R128_DP_DATATYPE 0x16c4 467 # define R128_HOST_BIG_ENDIAN_EN (1 << 29) 468 #define R128_DP_GUI_MASTER_CNTL 0x146c 469 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 470 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 471 # define R128_GMC_SRC_CLIPPING (1 << 2) 472 # define R128_GMC_DST_CLIPPING (1 << 3) 473 # define R128_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) 474 # define R128_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) 475 # define R128_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) 476 # define R128_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) 477 # define R128_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) 478 # define R128_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) 479 # define R128_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) 480 # define R128_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) 481 # define R128_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) 482 # define R128_GMC_BRUSH_8x8_COLOR (10 << 4) 483 # define R128_GMC_BRUSH_1X8_COLOR (12 << 4) 484 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) 485 # define R128_GMC_BRUSH_NONE (15 << 4) 486 # define R128_GMC_DST_8BPP_CI (2 << 8) 487 # define R128_GMC_DST_15BPP (3 << 8) 488 # define R128_GMC_DST_16BPP (4 << 8) 489 # define R128_GMC_DST_24BPP (5 << 8) 490 # define R128_GMC_DST_32BPP (6 << 8) 491 # define R128_GMC_DST_8BPP_RGB (7 << 8) 492 # define R128_GMC_DST_Y8 (8 << 8) 493 # define R128_GMC_DST_RGB8 (9 << 8) 494 # define R128_GMC_DST_VYUY (11 << 8) 495 # define R128_GMC_DST_YVYU (12 << 8) 496 # define R128_GMC_DST_AYUV444 (14 << 8) 497 # define R128_GMC_DST_ARGB4444 (15 << 8) 498 # define R128_GMC_DST_DATATYPE_MASK (0x0f << 8) 499 # define R128_GMC_DST_DATATYPE_SHIFT 8 500 # define R128_GMC_SRC_DATATYPE_MASK (3 << 12) 501 # define R128_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) 502 # define R128_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) 503 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) 504 # define R128_GMC_BYTE_PIX_ORDER (1 << 14) 505 # define R128_GMC_BYTE_MSB_TO_LSB (0 << 14) 506 # define R128_GMC_BYTE_LSB_TO_MSB (1 << 14) 507 # define R128_GMC_CONVERSION_TEMP (1 << 15) 508 # define R128_GMC_CONVERSION_TEMP_6500 (0 << 15) 509 # define R128_GMC_CONVERSION_TEMP_9300 (1 << 15) 510 # define R128_GMC_ROP3_MASK (0xff << 16) 511 # define R128_DP_SRC_SOURCE_MASK (7 << 24) 512 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) 513 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) 514 # define R128_GMC_3D_FCN_EN (1 << 27) 515 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) 516 # define R128_GMC_AUX_CLIP_DIS (1 << 29) 517 # define R128_GMC_WR_MSK_DIS (1 << 30) 518 # define R128_GMC_LD_BRUSH_Y_X (1 << 31) 519 # define R128_ROP3_ZERO 0x00000000 520 # define R128_ROP3_DSa 0x00880000 521 # define R128_ROP3_SDna 0x00440000 522 # define R128_ROP3_S 0x00cc0000 523 # define R128_ROP3_DSna 0x00220000 524 # define R128_ROP3_D 0x00aa0000 525 # define R128_ROP3_DSx 0x00660000 526 # define R128_ROP3_DSo 0x00ee0000 527 # define R128_ROP3_DSon 0x00110000 528 # define R128_ROP3_DSxn 0x00990000 529 # define R128_ROP3_Dn 0x00550000 530 # define R128_ROP3_SDno 0x00dd0000 531 # define R128_ROP3_Sn 0x00330000 532 # define R128_ROP3_DSno 0x00bb0000 533 # define R128_ROP3_DSan 0x00770000 534 # define R128_ROP3_ONE 0x00ff0000 535 # define R128_ROP3_DPa 0x00a00000 536 # define R128_ROP3_PDna 0x00500000 537 # define R128_ROP3_P 0x00f00000 538 # define R128_ROP3_DPna 0x000a0000 539 # define R128_ROP3_D 0x00aa0000 540 # define R128_ROP3_DPx 0x005a0000 541 # define R128_ROP3_DPo 0x00fa0000 542 # define R128_ROP3_DPon 0x00050000 543 # define R128_ROP3_PDxn 0x00a50000 544 # define R128_ROP3_PDno 0x00f50000 545 # define R128_ROP3_Pn 0x000f0000 546 # define R128_ROP3_DPno 0x00af0000 547 # define R128_ROP3_DPan 0x005f0000 548 549 550 #define R128_DP_GUI_MASTER_CNTL_C 0x1c84 551 #define R128_DP_MIX 0x16c8 552 #define R128_DP_SRC_BKGD_CLR 0x15dc 553 #define R128_DP_SRC_FRGD_CLR 0x15d8 554 #define R128_DP_WRITE_MASK 0x16cc 555 #define R128_DST_BRES_DEC 0x1630 556 #define R128_DST_BRES_ERR 0x1628 557 #define R128_DST_BRES_INC 0x162c 558 #define R128_DST_BRES_LNTH 0x1634 559 #define R128_DST_BRES_LNTH_SUB 0x1638 560 #define R128_DST_HEIGHT 0x1410 561 #define R128_DST_HEIGHT_WIDTH 0x143c 562 #define R128_DST_HEIGHT_WIDTH_8 0x158c 563 #define R128_DST_HEIGHT_WIDTH_BW 0x15b4 564 #define R128_DST_HEIGHT_Y 0x15a0 565 #define R128_DST_OFFSET 0x1404 566 #define R128_DST_PITCH 0x1408 567 #define R128_DST_PITCH_OFFSET 0x142c 568 #define R128_DST_PITCH_OFFSET_C 0x1c80 569 # define R128_PITCH_SHIFT 21 570 # define R128_DST_TILE (1 << 31) 571 #define R128_DST_WIDTH 0x140c 572 #define R128_DST_WIDTH_HEIGHT 0x1598 573 #define R128_DST_WIDTH_X 0x1588 574 #define R128_DST_WIDTH_X_INCY 0x159c 575 #define R128_DST_X 0x141c 576 #define R128_DST_X_SUB 0x15a4 577 #define R128_DST_X_Y 0x1594 578 #define R128_DST_Y 0x1420 579 #define R128_DST_Y_SUB 0x15a8 580 #define R128_DST_Y_X 0x1438 581 582 #define R128_EXT_MEM_CNTL 0x0144 583 584 #define R128_FCP_CNTL 0x0012 /* PLL */ 585 #define R128_FLUSH_1 0x1704 586 #define R128_FLUSH_2 0x1708 587 #define R128_FLUSH_3 0x170c 588 #define R128_FLUSH_4 0x1710 589 #define R128_FLUSH_5 0x1714 590 #define R128_FLUSH_6 0x1718 591 #define R128_FLUSH_7 0x171c 592 #define R128_FOG_3D_TABLE_START 0x1810 593 #define R128_FOG_3D_TABLE_END 0x1814 594 #define R128_FOG_3D_TABLE_DENSITY 0x181c 595 #define R128_FOG_TABLE_INDEX 0x1a14 596 #define R128_FOG_TABLE_DATA 0x1a18 597 #define R128_FP_CRTC_H_TOTAL_DISP 0x0250 598 #define R128_FP_CRTC_V_TOTAL_DISP 0x0254 599 #define R128_FP_GEN_CNTL 0x0284 600 # define R128_FP_FPON (1 << 0) 601 # define R128_FP_BLANK_DIS (1 << 1) 602 # define R128_FP_TMDS_EN (1 << 2) 603 # define R128_FP_DETECT_SENSE (1 << 8) 604 # define R128_FP_SEL_CRTC2 (1 << 13) 605 # define R128_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 606 # define R128_FP_CRTC_DONT_SHADOW_HEND (1 << 17) 607 # define R128_FP_CRTC_USE_SHADOW_VEND (1 << 18) 608 # define R128_FP_CRTC_USE_SHADOW_ROWCUR (1 << 19) 609 # define R128_FP_CRTC_HORZ_DIV2_EN (1 << 20) 610 # define R128_FP_CRTC_HOR_CRT_DIV2_DIS (1 << 21) 611 # define R128_FP_CRT_SYNC_SEL (1 << 23) 612 # define R128_FP_USE_SHADOW_EN (1 << 24) 613 #define R128_FP_H_SYNC_STRT_WID 0x02c4 614 #define R128_FP_HORZ_STRETCH 0x028c 615 # define R128_HORZ_STRETCH_RATIO_MASK 0xffff 616 # define R128_HORZ_STRETCH_RATIO_SHIFT 0 617 # define R128_HORZ_STRETCH_RATIO_MAX 4096 618 # define R128_HORZ_PANEL_SIZE (0xff << 16) 619 # define R128_HORZ_PANEL_SHIFT 16 620 # define R128_AUTO_HORZ_RATIO (0 << 24) 621 # define R128_HORZ_STRETCH_PIXREP (0 << 25) 622 # define R128_HORZ_STRETCH_BLEND (1 << 25) 623 # define R128_HORZ_STRETCH_ENABLE (1 << 26) 624 # define R128_HORZ_FP_LOOP_STRETCH (0x7 << 27) 625 # define R128_HORZ_STRETCH_RESERVED (1 << 30) 626 # define R128_HORZ_AUTO_RATIO_FIX_EN (1 << 31) 627 628 #define R128_FP_PANEL_CNTL 0x0288 629 # define R128_FP_DIGON (1 << 0) 630 # define R128_FP_BLON (1 << 1) 631 #define R128_FP_V_SYNC_STRT_WID 0x02c8 632 #define R128_FP_VERT_STRETCH 0x0290 633 # define R128_VERT_PANEL_SIZE (0x7ff << 0) 634 # define R128_VERT_PANEL_SHIFT 0 635 # define R128_VERT_STRETCH_RATIO_MASK 0x3ff 636 # define R128_VERT_STRETCH_RATIO_SHIFT 11 637 # define R128_VERT_STRETCH_RATIO_MAX 1024 638 # define R128_VERT_STRETCH_ENABLE (1 << 24) 639 # define R128_VERT_STRETCH_LINEREP (0 << 25) 640 # define R128_VERT_STRETCH_BLEND (1 << 25) 641 # define R128_VERT_AUTO_RATIO_EN (1 << 26) 642 # define R128_VERT_STRETCH_RESERVED 0xf8e00000 643 644 #define R128_GEN_INT_CNTL 0x0040 645 #define R128_GEN_INT_STATUS 0x0044 646 # define R128_VSYNC_INT_AK (1 << 2) 647 # define R128_VSYNC_INT (1 << 2) 648 #define R128_GEN_RESET_CNTL 0x00f0 649 # define R128_SOFT_RESET_GUI (1 << 0) 650 # define R128_SOFT_RESET_VCLK (1 << 8) 651 # define R128_SOFT_RESET_PCLK (1 << 9) 652 # define R128_SOFT_RESET_DISPENG_XCLK (1 << 11) 653 # define R128_SOFT_RESET_MEMCTLR_XCLK (1 << 12) 654 #define R128_GENENB 0x03c3 /* VGA */ 655 #define R128_GENFC_RD 0x03ca /* VGA */ 656 #define R128_GENFC_WT 0x03da /* VGA, 0x03ba */ 657 #define R128_GENMO_RD 0x03cc /* VGA */ 658 #define R128_GENMO_WT 0x03c2 /* VGA */ 659 #define R128_GENS0 0x03c2 /* VGA */ 660 #define R128_GENS1 0x03da /* VGA, 0x03ba */ 661 #define R128_GPIO_MONID 0x0068 662 # define R128_GPIO_MONID_A_0 (1 << 0) 663 # define R128_GPIO_MONID_A_1 (1 << 1) 664 # define R128_GPIO_MONID_A_2 (1 << 2) 665 # define R128_GPIO_MONID_A_3 (1 << 3) 666 # define R128_GPIO_MONID_Y_0 (1 << 8) 667 # define R128_GPIO_MONID_Y_1 (1 << 9) 668 # define R128_GPIO_MONID_Y_2 (1 << 10) 669 # define R128_GPIO_MONID_Y_3 (1 << 11) 670 # define R128_GPIO_MONID_EN_0 (1 << 16) 671 # define R128_GPIO_MONID_EN_1 (1 << 17) 672 # define R128_GPIO_MONID_EN_2 (1 << 18) 673 # define R128_GPIO_MONID_EN_3 (1 << 19) 674 # define R128_GPIO_MONID_MASK_0 (1 << 24) 675 # define R128_GPIO_MONID_MASK_1 (1 << 25) 676 # define R128_GPIO_MONID_MASK_2 (1 << 26) 677 # define R128_GPIO_MONID_MASK_3 (1 << 27) 678 #define R128_GPIO_MONIDB 0x006c 679 #define R128_GRPH8_DATA 0x03cf /* VGA */ 680 #define R128_GRPH8_IDX 0x03ce /* VGA */ 681 #define R128_GUI_DEBUG0 0x16a0 682 #define R128_GUI_DEBUG1 0x16a4 683 #define R128_GUI_DEBUG2 0x16a8 684 #define R128_GUI_DEBUG3 0x16ac 685 #define R128_GUI_DEBUG4 0x16b0 686 #define R128_GUI_DEBUG5 0x16b4 687 #define R128_GUI_DEBUG6 0x16b8 688 #define R128_GUI_PROBE 0x16bc 689 #define R128_GUI_SCRATCH_REG0 0x15e0 690 #define R128_GUI_SCRATCH_REG1 0x15e4 691 #define R128_GUI_SCRATCH_REG2 0x15e8 692 #define R128_GUI_SCRATCH_REG3 0x15ec 693 #define R128_GUI_SCRATCH_REG4 0x15f0 694 #define R128_GUI_SCRATCH_REG5 0x15f4 695 #define R128_GUI_STAT 0x1740 696 # define R128_GUI_FIFOCNT_MASK 0x0fff 697 # define R128_GUI_ACTIVE (1 << 31) 698 699 #define R128_HEADER 0x0f0e /* PCI */ 700 #define R128_HOST_DATA0 0x17c0 701 #define R128_HOST_DATA1 0x17c4 702 #define R128_HOST_DATA2 0x17c8 703 #define R128_HOST_DATA3 0x17cc 704 #define R128_HOST_DATA4 0x17d0 705 #define R128_HOST_DATA5 0x17d4 706 #define R128_HOST_DATA6 0x17d8 707 #define R128_HOST_DATA7 0x17dc 708 #define R128_HOST_DATA_LAST 0x17e0 709 #define R128_HOST_PATH_CNTL 0x0130 710 #define R128_HTOTAL_CNTL 0x0009 /* PLL */ 711 #define R128_HTOTAL2_CNTL 0x002e /* PLL */ 712 #define R128_HW_DEBUG 0x0128 713 #define R128_HW_DEBUG2 0x011c 714 715 #define R128_I2C_CNTL_1 0x0094 /* ? */ 716 #define R128_INTERRUPT_LINE 0x0f3c /* PCI */ 717 #define R128_INTERRUPT_PIN 0x0f3d /* PCI */ 718 #define R128_IO_BASE 0x0f14 /* PCI */ 719 720 #define R128_LATENCY 0x0f0d /* PCI */ 721 #define R128_LEAD_BRES_DEC 0x1608 722 #define R128_LEAD_BRES_ERR 0x1600 723 #define R128_LEAD_BRES_INC 0x1604 724 #define R128_LEAD_BRES_LNTH 0x161c 725 #define R128_LEAD_BRES_LNTH_SUB 0x1624 726 #define R128_LVDS_GEN_CNTL 0x02d0 727 # define R128_LVDS_ON (1 << 0) 728 # define R128_LVDS_DISPLAY_DIS (1 << 1) 729 # define R128_LVDS_EN (1 << 7) 730 # define R128_LVDS_DIGON (1 << 18) 731 # define R128_LVDS_BLON (1 << 19) 732 # define R128_LVDS_SEL_CRTC2 (1 << 23) 733 # define R128_HSYNC_DELAY_SHIFT 28 734 # define R128_HSYNC_DELAY_MASK (0xf << 28) 735 736 #define R128_MAX_LATENCY 0x0f3f /* PCI */ 737 #define R128_MCLK_CNTL 0x000f /* PLL */ 738 # define R128_FORCE_GCP (1 << 16) 739 # define R128_FORCE_PIPE3D_CP (1 << 17) 740 # define R128_FORCE_RCP (1 << 18) 741 #define R128_MDGPIO_A_REG 0x01ac 742 #define R128_MDGPIO_EN_REG 0x01b0 743 #define R128_MDGPIO_MASK 0x0198 744 #define R128_MDGPIO_Y_REG 0x01b4 745 #define R128_MEM_ADDR_CONFIG 0x0148 746 #define R128_MEM_BASE 0x0f10 /* PCI */ 747 #define R128_MEM_CNTL 0x0140 748 #define R128_MEM_INIT_LAT_TIMER 0x0154 749 #define R128_MEM_INTF_CNTL 0x014c 750 #define R128_MEM_SDRAM_MODE_REG 0x0158 751 #define R128_MEM_STR_CNTL 0x0150 752 #define R128_MEM_VGA_RP_SEL 0x003c 753 #define R128_MEM_VGA_WP_SEL 0x0038 754 #define R128_MIN_GRANT 0x0f3e /* PCI */ 755 #define R128_MM_DATA 0x0004 756 #define R128_MM_INDEX 0x0000 757 #define R128_MPLL_CNTL 0x000e /* PLL */ 758 #define R128_MPP_TB_CONFIG 0x01c0 /* ? */ 759 #define R128_MPP_GP_CONFIG 0x01c8 /* ? */ 760 761 #define R128_N_VIF_COUNT 0x0248 762 763 #define R128_OVR_CLR 0x0230 764 #define R128_OVR_WID_LEFT_RIGHT 0x0234 765 #define R128_OVR_WID_TOP_BOTTOM 0x0238 766 767 /* first overlay unit (there is only one) */ 768 769 #define R128_OV0_Y_X_START 0x0400 770 #define R128_OV0_Y_X_END 0x0404 771 #define R128_OV0_EXCLUSIVE_HORZ 0x0408 772 # define R128_EXCL_HORZ_START_MASK 0x000000ff 773 # define R128_EXCL_HORZ_END_MASK 0x0000ff00 774 # define R128_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 775 # define R128_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 776 #define R128_OV0_EXCLUSIVE_VERT 0x040C 777 # define R128_EXCL_VERT_START_MASK 0x000003ff 778 # define R128_EXCL_VERT_END_MASK 0x03ff0000 779 #define R128_OV0_REG_LOAD_CNTL 0x0410 780 # define R128_REG_LD_CTL_LOCK 0x00000001L 781 # define R128_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L 782 # define R128_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L 783 # define R128_REG_LD_CTL_LOCK_READBACK 0x00000008L 784 #define R128_OV0_SCALE_CNTL 0x0420 785 # define R128_SCALER_PIX_EXPAND 0x00000001L 786 # define R128_SCALER_Y2R_TEMP 0x00000002L 787 # define R128_SCALER_HORZ_PICK_NEAREST 0x00000003L 788 # define R128_SCALER_VERT_PICK_NEAREST 0x00000004L 789 # define R128_SCALER_SIGNED_UV 0x00000010L 790 # define R128_SCALER_GAMMA_SEL_MASK 0x00000060L 791 # define R128_SCALER_GAMMA_SEL_BRIGHT 0x00000000L 792 # define R128_SCALER_GAMMA_SEL_G22 0x00000020L 793 # define R128_SCALER_GAMMA_SEL_G18 0x00000040L 794 # define R128_SCALER_GAMMA_SEL_G14 0x00000060L 795 # define R128_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L 796 # define R128_SCALER_SURFAC_FORMAT 0x00000f00L 797 # define R128_SCALER_SOURCE_15BPP 0x00000300L 798 # define R128_SCALER_SOURCE_16BPP 0x00000400L 799 # define R128_SCALER_SOURCE_32BPP 0x00000600L 800 # define R128_SCALER_SOURCE_YUV9 0x00000900L 801 # define R128_SCALER_SOURCE_YUV12 0x00000A00L 802 # define R128_SCALER_SOURCE_VYUY422 0x00000B00L 803 # define R128_SCALER_SOURCE_YVYU422 0x00000C00L 804 # define R128_SCALER_SMART_SWITCH 0x00008000L 805 # define R128_SCALER_BURST_PER_PLANE 0x00ff0000L 806 # define R128_SCALER_DOUBLE_BUFFER 0x01000000L 807 # define R128_SCALER_DIS_LIMIT 0x08000000L 808 # define R128_SCALER_PRG_LOAD_START 0x10000000L 809 # define R128_SCALER_INT_EMU 0x20000000L 810 # define R128_SCALER_ENABLE 0x40000000L 811 # define R128_SCALER_SOFT_RESET 0x80000000L 812 #define R128_OV0_V_INC 0x0424 813 #define R128_OV0_P1_V_ACCUM_INIT 0x0428 814 # define R128_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L 815 # define R128_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L 816 #define R128_OV0_P23_V_ACCUM_INIT 0x042C 817 #define R128_OV0_P1_BLANK_LINES_AT_TOP 0x0430 818 # define R128_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL 819 # define R128_P1_ACTIVE_LINES_M1 0x0fff0000L 820 #define R128_OV0_P23_BLANK_LINES_AT_TOP 0x0434 821 # define R128_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL 822 # define R128_P23_ACTIVE_LINES_M1 0x07ff0000L 823 #define R128_OV0_VID_BUF0_BASE_ADRS 0x0440 824 # define R128_VIF_BUF0_PITCH_SEL 0x00000001L 825 # define R128_VIF_BUF0_TILE_ADRS 0x00000002L 826 # define R128_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L 827 # define R128_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L 828 #define R128_OV0_VID_BUF1_BASE_ADRS 0x0444 829 # define R128_VIF_BUF1_PITCH_SEL 0x00000001L 830 # define R128_VIF_BUF1_TILE_ADRS 0x00000002L 831 # define R128_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L 832 # define R128_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L 833 #define R128_OV0_VID_BUF2_BASE_ADRS 0x0448 834 # define R128_VIF_BUF2_PITCH_SEL 0x00000001L 835 # define R128_VIF_BUF2_TILE_ADRS 0x00000002L 836 # define R128_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L 837 # define R128_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L 838 #define R128_OV0_VID_BUF3_BASE_ADRS 0x044C 839 #define R128_OV0_VID_BUF4_BASE_ADRS 0x0450 840 #define R128_OV0_VID_BUF5_BASE_ADRS 0x0454 841 #define R128_OV0_VID_BUF_PITCH0_VALUE 0x0460 842 #define R128_OV0_VID_BUF_PITCH1_VALUE 0x0464 843 #define R128_OV0_AUTO_FLIP_CNTL 0x0470 844 #define R128_OV0_DEINTERLACE_PATTERN 0x0474 845 #define R128_OV0_H_INC 0x0480 846 #define R128_OV0_STEP_BY 0x0484 847 #define R128_OV0_P1_H_ACCUM_INIT 0x0488 848 #define R128_OV0_P23_H_ACCUM_INIT 0x048C 849 #define R128_OV0_P1_X_START_END 0x0494 850 #define R128_OV0_P2_X_START_END 0x0498 851 #define R128_OV0_P3_X_START_END 0x049C 852 #define R128_OV0_FILTER_CNTL 0x04A0 853 #define R128_OV0_FOUR_TAP_COEF_0 0x04B0 854 #define R128_OV0_FOUR_TAP_COEF_1 0x04B4 855 #define R128_OV0_FOUR_TAP_COEF_2 0x04B8 856 #define R128_OV0_FOUR_TAP_COEF_3 0x04BC 857 #define R128_OV0_FOUR_TAP_COEF_4 0x04C0 858 #define R128_OV0_COLOUR_CNTL 0x04E0 859 #define R128_OV0_VIDEO_KEY_CLR 0x04E4 860 #define R128_OV0_VIDEO_KEY_MSK 0x04E8 861 #define R128_OV0_GRAPHICS_KEY_CLR 0x04EC 862 #define R128_OV0_GRAPHICS_KEY_MSK 0x04F0 863 #define R128_OV0_KEY_CNTL 0x04F4 864 # define R128_VIDEO_KEY_FN_MASK 0x00000007L 865 # define R128_VIDEO_KEY_FN_FALSE 0x00000000L 866 # define R128_VIDEO_KEY_FN_TRUE 0x00000001L 867 # define R128_VIDEO_KEY_FN_EQ 0x00000004L 868 # define R128_VIDEO_KEY_FN_NE 0x00000005L 869 # define R128_GRAPHIC_KEY_FN_MASK 0x00000070L 870 # define R128_GRAPHIC_KEY_FN_FALSE 0x00000000L 871 # define R128_GRAPHIC_KEY_FN_TRUE 0x00000010L 872 # define R128_GRAPHIC_KEY_FN_EQ 0x00000040L 873 # define R128_GRAPHIC_KEY_FN_NE 0x00000050L 874 # define R128_CMP_MIX_MASK 0x00000100L 875 # define R128_CMP_MIX_OR 0x00000000L 876 # define R128_CMP_MIX_AND 0x00000100L 877 #define R128_OV0_TEST 0x04F8 878 879 880 #define R128_PALETTE_DATA 0x00b4 881 #define R128_PALETTE_INDEX 0x00b0 882 #define R128_PC_DEBUG_MODE 0x1760 883 #define R128_PC_GUI_CTLSTAT 0x1748 884 #define R128_PC_GUI_MODE 0x1744 885 # define R128_PC_IGNORE_UNIFY (1 << 5) 886 #define R128_PC_MISC_CNTL 0x0188 887 #define R128_PC_NGUI_CTLSTAT 0x0184 888 # define R128_PC_FLUSH_GUI (3 << 0) 889 # define R128_PC_RI_GUI (1 << 2) 890 # define R128_PC_FLUSH_ALL 0x00ff 891 # define R128_PC_BUSY (1 << 31) 892 #define R128_PC_NGUI_MODE 0x0180 893 #define R128_PCI_GART_PAGE 0x017c 894 #define R128_PLANE_3D_MASK_C 0x1d44 895 #define R128_PLL_TEST_CNTL 0x0013 /* PLL */ 896 #define R128_PMI_CAP_ID 0x0f5c /* PCI */ 897 #define R128_PMI_DATA 0x0f63 /* PCI */ 898 #define R128_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ 899 #define R128_PMI_PMC_REG 0x0f5e /* PCI */ 900 #define R128_PMI_PMCSR_REG 0x0f60 /* PCI */ 901 #define R128_PMI_REGISTER 0x0f5c /* PCI */ 902 #define R128_PPLL_CNTL 0x0002 /* PLL */ 903 # define R128_PPLL_RESET (1 << 0) 904 # define R128_PPLL_SLEEP (1 << 1) 905 # define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16) 906 # define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 907 #define R128_PPLL_DIV_0 0x0004 /* PLL */ 908 # define R128_PPLL_FB0_DIV_MASK 0x07ff 909 # define R128_PPLL_POST0_DIV_MASK 0x00070000 910 #define R128_PPLL_DIV_1 0x0005 /* PLL */ 911 #define R128_PPLL_DIV_2 0x0006 /* PLL */ 912 #define R128_PPLL_DIV_3 0x0007 /* PLL */ 913 # define R128_PPLL_FB3_DIV_MASK 0x07ff 914 # define R128_PPLL_POST3_DIV_MASK 0x00070000 915 #define R128_PPLL_REF_DIV 0x0003 /* PLL */ 916 # define R128_PPLL_REF_DIV_MASK 0x03ff 917 # define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 918 # define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 919 #define R128_P2PLL_CNTL 0x002a /* P2PLL */ 920 # define R128_P2PLL_RESET (1 << 0) 921 # define R128_P2PLL_SLEEP (1 << 1) 922 # define R128_P2PLL_ATOMIC_UPDATE_EN (1 << 16) 923 # define R128_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 924 # define R128_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) 925 #define R128_P2PLL_DIV_0 0x002c 926 # define R128_P2PLL_FB0_DIV_MASK 0x07ff 927 # define R128_P2PLL_POST0_DIV_MASK 0x00070000 928 #define R128_P2PLL_REF_DIV 0x002B /* PLL */ 929 # define R128_P2PLL_REF_DIV_MASK 0x03ff 930 # define R128_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 931 # define R128_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 932 #define R128_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ 933 #define R128_REG_BASE 0x0f18 /* PCI */ 934 #define R128_REGPROG_INF 0x0f09 /* PCI */ 935 #define R128_REVISION_ID 0x0f08 /* PCI */ 936 937 #define R128_SC_BOTTOM 0x164c 938 #define R128_SC_BOTTOM_RIGHT 0x16f0 939 #define R128_SC_BOTTOM_RIGHT_C 0x1c8c 940 #define R128_SC_LEFT 0x1640 941 #define R128_SC_RIGHT 0x1644 942 #define R128_SC_TOP 0x1648 943 #define R128_SC_TOP_LEFT 0x16ec 944 #define R128_SC_TOP_LEFT_C 0x1c88 945 #define R128_SEQ8_DATA 0x03c5 /* VGA */ 946 #define R128_SEQ8_IDX 0x03c4 /* VGA */ 947 #define R128_SNAPSHOT_F_COUNT 0x0244 948 #define R128_SNAPSHOT_VH_COUNTS 0x0240 949 #define R128_SNAPSHOT_VIF_COUNT 0x024c 950 #define R128_SRC_OFFSET 0x15ac 951 #define R128_SRC_PITCH 0x15b0 952 #define R128_SRC_PITCH_OFFSET 0x1428 953 #define R128_SRC_SC_BOTTOM 0x165c 954 #define R128_SRC_SC_BOTTOM_RIGHT 0x16f4 955 #define R128_SRC_SC_RIGHT 0x1654 956 #define R128_SRC_X 0x1414 957 #define R128_SRC_X_Y 0x1590 958 #define R128_SRC_Y 0x1418 959 #define R128_SRC_Y_X 0x1434 960 #define R128_STATUS 0x0f06 /* PCI */ 961 #define R128_SUBPIC_CNTL 0x0540 /* ? */ 962 #define R128_SUB_CLASS 0x0f0a /* PCI */ 963 #define R128_SURFACE_DELAY 0x0b00 964 #define R128_SURFACE0_INFO 0x0b0c 965 #define R128_SURFACE0_LOWER_BOUND 0x0b04 966 #define R128_SURFACE0_UPPER_BOUND 0x0b08 967 #define R128_SURFACE1_INFO 0x0b1c 968 #define R128_SURFACE1_LOWER_BOUND 0x0b14 969 #define R128_SURFACE1_UPPER_BOUND 0x0b18 970 #define R128_SURFACE2_INFO 0x0b2c 971 #define R128_SURFACE2_LOWER_BOUND 0x0b24 972 #define R128_SURFACE2_UPPER_BOUND 0x0b28 973 #define R128_SURFACE3_INFO 0x0b3c 974 #define R128_SURFACE3_LOWER_BOUND 0x0b34 975 #define R128_SURFACE3_UPPER_BOUND 0x0b38 976 #define R128_SW_SEMAPHORE 0x013c 977 978 #define R128_TEST_DEBUG_CNTL 0x0120 979 #define R128_TEST_DEBUG_MUX 0x0124 980 #define R128_TEST_DEBUG_OUT 0x012c 981 #define R128_TMDS_CRC 0x02a0 982 #define R128_TMDS_TRANSMITTER_CNTL 0x02a4 983 # define R128_TMDS_PLLEN (1 << 0) 984 # define R128_TMDS_PLLRST (1 << 1) 985 #define R128_TRAIL_BRES_DEC 0x1614 986 #define R128_TRAIL_BRES_ERR 0x160c 987 #define R128_TRAIL_BRES_INC 0x1610 988 #define R128_TRAIL_X 0x1618 989 #define R128_TRAIL_X_SUB 0x1620 990 991 #define R128_VCLK_ECP_CNTL 0x0008 /* PLL */ 992 # define R128_VCLK_SRC_SEL_MASK 0x03 993 # define R128_VCLK_SRC_SEL_CPUCLK 0x00 994 # define R128_VCLK_SRC_SEL_PPLLCLK 0x03 995 # define R128_ECP_DIV_MASK (3 << 8) 996 #define R128_V2CLK_VCLKTV_CNTL 0x002d /* PLL */ 997 # define R128_V2CLK_SRC_SEL_MASK 0x03 998 # define R128_V2CLK_SRC_SEL_CPUCLK 0x00 999 # define R128_V2CLK_SRC_SEL_P2PLLCLK 0x03 1000 #define R128_VENDOR_ID 0x0f00 /* PCI */ 1001 #define R128_VGA_DDA_CONFIG 0x02e8 1002 #define R128_VGA_DDA_ON_OFF 0x02ec 1003 #define R128_VID_BUFFER_CONTROL 0x0900 1004 #define R128_VIDEOMUX_CNTL 0x0190 1005 #define R128_VIPH_CONTROL 0x01D0 /* ? */ 1006 1007 #define R128_WAIT_UNTIL 0x1720 1008 1009 #define R128_X_MPLL_REF_FB_DIV 0x000a /* PLL */ 1010 #define R128_XCLK_CNTL 0x000d /* PLL */ 1011 #define R128_XDLL_CNTL 0x000c /* PLL */ 1012 #define R128_XPLL_CNTL 0x000b /* PLL */ 1013 1014 /* Registers for CCE and Microcode Engine */ 1015 #define R128_PM4_MICROCODE_ADDR 0x07d4 1016 #define R128_PM4_MICROCODE_RADDR 0x07d8 1017 #define R128_PM4_MICROCODE_DATAH 0x07dc 1018 #define R128_PM4_MICROCODE_DATAL 0x07e0 1019 1020 #define R128_PM4_BUFFER_OFFSET 0x0700 1021 #define R128_PM4_BUFFER_CNTL 0x0704 1022 # define R128_PM4_NONPM4 (0 << 28) 1023 # define R128_PM4_192PIO (1 << 28) 1024 # define R128_PM4_192BM (2 << 28) 1025 # define R128_PM4_128PIO_64INDBM (3 << 28) 1026 # define R128_PM4_128BM_64INDBM (4 << 28) 1027 # define R128_PM4_64PIO_128INDBM (5 << 28) 1028 # define R128_PM4_64BM_128INDBM (6 << 28) 1029 # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) 1030 # define R128_PM4_64BM_64VCBM_64INDBM (8U << 28) 1031 # define R128_PM4_64PIO_64VCPIO_64INDPIO (15U << 28) 1032 #define R128_PM4_BUFFER_WM_CNTL 0x0708 1033 # define R128_WMA_SHIFT 0 1034 # define R128_WMB_SHIFT 8 1035 # define R128_WMC_SHIFT 16 1036 # define R128_WB_WM_SHIFT 24 1037 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c 1038 #define R128_PM4_BUFFER_DL_RPTR 0x0710 1039 #define R128_PM4_BUFFER_DL_WPTR 0x0714 1040 # define R128_PM4_BUFFER_DL_DONE (1U << 31) 1041 #define R128_PM4_BUFFER_DL_WPTR_DELAY 0x0718 1042 # define R128_PRE_WRITE_TIMER_SHIFT 0 1043 # define R128_PRE_WRITE_LIMIT_SHIFT 23 1044 #define R128_PM4_VC_FPU_SETUP 0x071c 1045 # define R128_FRONT_DIR_CW (0 << 0) 1046 # define R128_FRONT_DIR_CCW (1 << 0) 1047 # define R128_FRONT_DIR_MASK (1 << 0) 1048 # define R128_BACKFACE_CULL (0 << 1) 1049 # define R128_BACKFACE_POINTS (1 << 1) 1050 # define R128_BACKFACE_LINES (2 << 1) 1051 # define R128_BACKFACE_SOLID (3 << 1) 1052 # define R128_BACKFACE_MASK (3 << 1) 1053 # define R128_FRONTFACE_CULL (0 << 3) 1054 # define R128_FRONTFACE_POINTS (1 << 3) 1055 # define R128_FRONTFACE_LINES (2 << 3) 1056 # define R128_FRONTFACE_SOLID (3 << 3) 1057 # define R128_FRONTFACE_MASK (3 << 3) 1058 # define R128_FPU_COLOR_SOLID (0 << 5) 1059 # define R128_FPU_COLOR_FLAT (1 << 5) 1060 # define R128_FPU_COLOR_GOURAUD (2 << 5) 1061 # define R128_FPU_COLOR_GOURAUD2 (3 << 5) 1062 # define R128_FPU_COLOR_MASK (3 << 5) 1063 # define R128_FPU_SUB_PIX_2BITS (0 << 7) 1064 # define R128_FPU_SUB_PIX_4BITS (1 << 7) 1065 # define R128_FPU_MODE_2D (0 << 8) 1066 # define R128_FPU_MODE_3D (1 << 8) 1067 # define R128_TRAP_BITS_DISABLE (1 << 9) 1068 # define R128_EDGE_ANTIALIAS (1 << 10) 1069 # define R128_SUPERSAMPLE (1 << 11) 1070 # define R128_XFACTOR_2 (0 << 12) 1071 # define R128_XFACTOR_4 (1 << 12) 1072 # define R128_YFACTOR_2 (0 << 13) 1073 # define R128_YFACTOR_4 (1 << 13) 1074 # define R128_FLAT_SHADE_VERTEX_D3D (0 << 14) 1075 # define R128_FLAT_SHADE_VERTEX_OGL (1 << 14) 1076 # define R128_FPU_ROUND_TRUNCATE (0 << 15) 1077 # define R128_FPU_ROUND_NEAREST (1 << 15) 1078 # define R128_WM_SEL_8DW (0 << 16) 1079 # define R128_WM_SEL_16DW (1 << 16) 1080 # define R128_WM_SEL_32DW (2 << 16) 1081 #define R128_PM4_VC_DEBUG_CONFIG 0x07a4 1082 #define R128_PM4_VC_STAT 0x07a8 1083 #define R128_PM4_VC_TIMESTAMP0 0x07b0 1084 #define R128_PM4_VC_TIMESTAMP1 0x07b4 1085 #define R128_PM4_STAT 0x07b8 1086 # define R128_PM4_FIFOCNT_MASK 0x0fff 1087 # define R128_PM4_BUSY (1 << 16) 1088 # define R128_PM4_GUI_ACTIVE (1U << 31) 1089 #define R128_PM4_BUFFER_ADDR 0x07f0 1090 #define R128_PM4_MICRO_CNTL 0x07fc 1091 # define R128_PM4_MICRO_FREERUN (1 << 30) 1092 #define R128_PM4_FIFO_DATA_EVEN 0x1000 1093 #define R128_PM4_FIFO_DATA_ODD 0x1004 1094 1095 #define R128_SCALE_3D_CNTL 0x1a00 1096 # define R128_SCALE_DITHER_ERR_DIFF (0 << 1) 1097 # define R128_SCALE_DITHER_TABLE (1 << 1) 1098 # define R128_TEX_CACHE_SIZE_FULL (0 << 2) 1099 # define R128_TEX_CACHE_SIZE_HALF (1 << 2) 1100 # define R128_DITHER_INIT_CURR (0 << 3) 1101 # define R128_DITHER_INIT_RESET (1 << 3) 1102 # define R128_ROUND_24BIT (1 << 4) 1103 # define R128_TEX_CACHE_DISABLE (1 << 5) 1104 # define R128_SCALE_3D_NOOP (0 << 6) 1105 # define R128_SCALE_3D_SCALE (1 << 6) 1106 # define R128_SCALE_3D_TEXMAP_SHADE (2 << 6) 1107 # define R128_SCALE_PIX_BLEND (0 << 8) 1108 # define R128_SCALE_PIX_REPLICATE (1 << 8) 1109 # define R128_TEX_CACHE_SPLIT (1 << 9) 1110 # define R128_APPLE_YUV_MODE (1 << 10) 1111 # define R128_TEX_CACHE_PALLETE_MODE (1 << 11) 1112 # define R128_ALPHA_COMB_ADD_CLAMP (0 << 12) 1113 # define R128_ALPHA_COMB_ADD_NCLAMP (1 << 12) 1114 # define R128_ALPHA_COMB_SUB_SRC_DST_CLAMP (2 << 12) 1115 # define R128_ALPHA_COMB_SUB_SRC_DST_NCLAMP (3 << 12) 1116 # define R128_ALPHA_COMB_FCN_MASK (3 << 12) 1117 # define R128_FOG_VERTEX (0 << 14) 1118 # define R128_FOG_TABLE (1 << 14) 1119 # define R128_SIGNED_DST_CLAMP (1 << 15) 1120 1121 # define R128_ALPHA_BLEND_ZERO (0 ) 1122 # define R128_ALPHA_BLEND_ONE (1 ) 1123 # define R128_ALPHA_BLEND_SRCCOLOR (2 ) 1124 # define R128_ALPHA_BLEND_INVSRCCOLOR (3 ) 1125 # define R128_ALPHA_BLEND_SRCALPHA (4 ) 1126 # define R128_ALPHA_BLEND_INVSRCALPHA (5 ) 1127 # define R128_ALPHA_BLEND_DSTALPHA (6 ) 1128 # define R128_ALPHA_BLEND_INVDSTALPHA (7 ) 1129 # define R128_ALPHA_BLEND_DSTCOLOR (8 ) 1130 # define R128_ALPHA_BLEND_INVDSTCOLOR (9 ) 1131 # define R128_ALPHA_BLEND_SAT (10) /* aka SRCALPHASAT */ 1132 # define R128_ALPHA_BLEND_BLEND (11) /* aka BOTHSRCALPHA */ 1133 # define R128_ALPHA_BLEND_INVBLEND (12) /* aka BOTHINVSRCALPHA */ 1134 # define R128_ALPHA_BLEND_MASK (15) 1135 1136 # define R128_ALPHA_BLEND_SRC_SHIFT (16) 1137 # define R128_ALPHA_BLEND_DST_SHIFT (20) 1138 1139 # define R128_ALPHA_TEST_NEVER (0 << 24) 1140 # define R128_ALPHA_TEST_LESS (1 << 24) 1141 # define R128_ALPHA_TEST_LESSEQUAL (2 << 24) 1142 # define R128_ALPHA_TEST_EQUAL (3 << 24) 1143 # define R128_ALPHA_TEST_GREATEREQUAL (4 << 24) 1144 # define R128_ALPHA_TEST_GREATER (5 << 24) 1145 # define R128_ALPHA_TEST_NEQUAL (6 << 24) 1146 # define R128_ALPHA_TEST_ALWAYS (7 << 24) 1147 # define R128_ALPHA_TEST_MASK (7 << 24) 1148 # define R128_COMPOSITE_SHADOW_CMP_EQUAL (0 << 28) 1149 # define R128_COMPOSITE_SHADOW_CMP_NEQUAL (1 << 28) 1150 # define R128_COMPOSITE_SHADOW (1 << 29) 1151 # define R128_TEX_MAP_ALPHA_IN_TEXTURE (1 << 30) 1152 # define R128_TEX_CACHE_LINE_SIZE_8QW (0 << 31) 1153 # define R128_TEX_CACHE_LINE_SIZE_4QW (1U << 31) 1154 #define R128_SCALE_3D_DATATYPE 0x1a20 1155 1156 #define R128_SETUP_CNTL 0x1bc4 1157 # define R128_DONT_START_TRIANGLE (1 << 0) 1158 # define R128_Z_BIAS (0 << 1) 1159 # define R128_DONT_START_ANY_ON (1 << 2) 1160 # define R128_COLOR_SOLID_COLOR (0 << 3) 1161 # define R128_COLOR_FLAT_VERT_1 (1 << 3) 1162 # define R128_COLOR_FLAT_VERT_2 (2 << 3) 1163 # define R128_COLOR_FLAT_VERT_3 (3 << 3) 1164 # define R128_COLOR_GOURAUD (4 << 3) 1165 # define R128_PRIM_TYPE_TRI (0 << 7) 1166 # define R128_PRIM_TYPE_LINE (1 << 7) 1167 # define R128_PRIM_TYPE_POINT (2 << 7) 1168 # define R128_PRIM_TYPE_POLY_EDGE (3 << 7) 1169 # define R128_TEXTURE_ST_MULT_W (0 << 9) 1170 # define R128_TEXTURE_ST_DIRECT (1 << 9) 1171 # define R128_STARTING_VERTEX_1 (1 << 14) 1172 # define R128_STARTING_VERTEX_2 (2 << 14) 1173 # define R128_STARTING_VERTEX_3 (3 << 14) 1174 # define R128_ENDING_VERTEX_1 (1 << 16) 1175 # define R128_ENDING_VERTEX_2 (2 << 16) 1176 # define R128_ENDING_VERTEX_3 (3 << 16) 1177 # define R128_SU_POLY_LINE_LAST (0 << 18) 1178 # define R128_SU_POLY_LINE_NOT_LAST (1 << 18) 1179 # define R128_SUB_PIX_2BITS (0 << 19) 1180 # define R128_SUB_PIX_4BITS (1 << 19) 1181 # define R128_SET_UP_CONTINUE (1U << 31) 1182 1183 #define R128_WINDOW_XY_OFFSET 0x1bcc 1184 # define R128_WINDOW_Y_SHIFT 4 1185 # define R128_WINDOW_X_SHIFT 20 1186 1187 #define R128_Z_OFFSET_C 0x1c90 1188 #define R128_Z_PITCH_C 0x1c94 1189 # define R128_Z_TILE (1 << 16) 1190 #define R128_Z_STEN_CNTL_C 0x1c98 1191 # define R128_Z_PIX_WIDTH_16 (0 << 1) 1192 # define R128_Z_PIX_WIDTH_24 (1 << 1) 1193 # define R128_Z_PIX_WIDTH_32 (2 << 1) 1194 # define R128_Z_PIX_WIDTH_MASK (3 << 1) 1195 # define R128_Z_TEST_NEVER (0 << 4) 1196 # define R128_Z_TEST_LESS (1 << 4) 1197 # define R128_Z_TEST_LESSEQUAL (2 << 4) 1198 # define R128_Z_TEST_EQUAL (3 << 4) 1199 # define R128_Z_TEST_GREATEREQUAL (4 << 4) 1200 # define R128_Z_TEST_GREATER (5 << 4) 1201 # define R128_Z_TEST_NEQUAL (6 << 4) 1202 # define R128_Z_TEST_ALWAYS (7 << 4) 1203 # define R128_Z_TEST_MASK (7 << 4) 1204 # define R128_STENCIL_TEST_NEVER (0 << 12) 1205 # define R128_STENCIL_TEST_LESS (1 << 12) 1206 # define R128_STENCIL_TEST_LESSEQUAL (2 << 12) 1207 # define R128_STENCIL_TEST_EQUAL (3 << 12) 1208 # define R128_STENCIL_TEST_GREATEREQUAL (4 << 12) 1209 # define R128_STENCIL_TEST_GREATER (5 << 12) 1210 # define R128_STENCIL_TEST_NEQUAL (6 << 12) 1211 # define R128_STENCIL_TEST_ALWAYS (7 << 12) 1212 # define R128_STENCIL_S_FAIL_KEEP (0 << 16) 1213 # define R128_STENCIL_S_FAIL_ZERO (1 << 16) 1214 # define R128_STENCIL_S_FAIL_REPLACE (2 << 16) 1215 # define R128_STENCIL_S_FAIL_INC (3 << 16) 1216 # define R128_STENCIL_S_FAIL_DEC (4 << 16) 1217 # define R128_STENCIL_S_FAIL_INV (5 << 16) 1218 # define R128_STENCIL_ZPASS_KEEP (0 << 20) 1219 # define R128_STENCIL_ZPASS_ZERO (1 << 20) 1220 # define R128_STENCIL_ZPASS_REPLACE (2 << 20) 1221 # define R128_STENCIL_ZPASS_INC (3 << 20) 1222 # define R128_STENCIL_ZPASS_DEC (4 << 20) 1223 # define R128_STENCIL_ZPASS_INV (5 << 20) 1224 # define R128_STENCIL_ZFAIL_KEEP (0 << 24) 1225 # define R128_STENCIL_ZFAIL_ZERO (1 << 24) 1226 # define R128_STENCIL_ZFAIL_REPLACE (2 << 24) 1227 # define R128_STENCIL_ZFAIL_INC (3 << 24) 1228 # define R128_STENCIL_ZFAIL_DEC (4 << 24) 1229 # define R128_STENCIL_ZFAIL_INV (5 << 24) 1230 #define R128_TEX_CNTL_C 0x1c9c 1231 # define R128_Z_ENABLE (1 << 0) 1232 # define R128_Z_WRITE_ENABLE (1 << 1) 1233 # define R128_STENCIL_ENABLE (1 << 3) 1234 # define R128_SHADE_ENABLE (0 << 4) 1235 # define R128_TEXMAP_ENABLE (1 << 4) 1236 # define R128_SEC_TEXMAP_ENABLE (1 << 5) 1237 # define R128_FOG_ENABLE (1 << 7) 1238 # define R128_DITHER_ENABLE (1 << 8) 1239 # define R128_ALPHA_ENABLE (1 << 9) 1240 # define R128_ALPHA_TEST_ENABLE (1 << 10) 1241 # define R128_SPEC_LIGHT_ENABLE (1 << 11) 1242 # define R128_TEX_CHROMA_KEY_ENABLE (1 << 12) 1243 # define R128_ALPHA_IN_TEX_COMPLETE_A (0 << 13) 1244 # define R128_ALPHA_IN_TEX_LSB_A (1 << 13) 1245 # define R128_LIGHT_DIS (0 << 14) 1246 # define R128_LIGHT_COPY (1 << 14) 1247 # define R128_LIGHT_MODULATE (2 << 14) 1248 # define R128_LIGHT_ADD (3 << 14) 1249 # define R128_LIGHT_BLEND_CONSTANT (4 << 14) 1250 # define R128_LIGHT_BLEND_TEXTURE (5 << 14) 1251 # define R128_LIGHT_BLEND_VERTEX (6 << 14) 1252 # define R128_LIGHT_BLEND_CONST_COLOR (7 << 14) 1253 # define R128_ALPHA_LIGHT_DIS (0 << 18) 1254 # define R128_ALPHA_LIGHT_COPY (1 << 18) 1255 # define R128_ALPHA_LIGHT_MODULATE (2 << 18) 1256 # define R128_ALPHA_LIGHT_ADD (3 << 18) 1257 # define R128_ANTI_ALIAS (1 << 21) 1258 # define R128_TEX_CACHE_FLUSH (1 << 23) 1259 # define R128_LOD_BIAS_SHIFT 24 1260 # define R128_LOD_BIAS_MASK (0xffU << 24) 1261 #define R128_MISC_3D_STATE_CNTL_REG 0x1ca0 1262 # define R128_REF_ALPHA_MASK 0xff 1263 # define R128_MISC_SCALE_3D_NOOP (0 << 8) 1264 # define R128_MISC_SCALE_3D_SCALE (1 << 8) 1265 # define R128_MISC_SCALE_3D_TEXMAP_SHADE (2 << 8) 1266 # define R128_MISC_SCALE_PIX_BLEND (0 << 10) 1267 # define R128_MISC_SCALE_PIX_REPLICATE (1 << 10) 1268 /* Bits [14:12] are the same as R128_SCALE_3D_CNTL */ 1269 /* Bit [15] is unknown */ 1270 /* Bits [26:16] are the same as R128_SCALE_3D_CNTL */ 1271 /* Bits [31:27] are unknown */ 1272 1273 #define R128_TEXTURE_CLR_CMP_CLR_C 0x1ca4 1274 #define R128_TEXTURE_CLR_CMP_MSK_C 0x1ca8 1275 #define R128_FOG_COLOR_C 0x1cac 1276 # define R128_FOG_BLUE_SHIFT 0 1277 # define R128_FOG_GREEN_SHIFT 8 1278 # define R128_FOG_RED_SHIFT 16 1279 #define R128_PRIM_TEX_CNTL_C 0x1cb0 1280 # define R128_MIN_BLEND_NEAREST (0 << 1) 1281 # define R128_MIN_BLEND_LINEAR (1 << 1) 1282 # define R128_MIN_BLEND_MIPNEAREST (2 << 1) 1283 # define R128_MIN_BLEND_MIPLINEAR (3 << 1) 1284 # define R128_MIN_BLEND_LINEARMIPNEAREST (4 << 1) 1285 # define R128_MIN_BLEND_LINEARMIPLINEAR (5 << 1) 1286 # define R128_MIN_BLEND_MASK (7 << 1) 1287 # define R128_MAG_BLEND_NEAREST (0 << 4) 1288 # define R128_MAG_BLEND_LINEAR (1 << 4) 1289 # define R128_MAG_BLEND_MASK (7 << 4) 1290 # define R128_MIP_MAP_DISABLE (1 << 7) 1291 # define R128_TEX_CLAMP_S_WRAP (0 << 8) 1292 # define R128_TEX_CLAMP_S_MIRROR (1 << 8) 1293 # define R128_TEX_CLAMP_S_CLAMP (2 << 8) 1294 # define R128_TEX_CLAMP_S_BORDER_COLOR (3 << 8) 1295 # define R128_TEX_CLAMP_S_MASK (3 << 8) 1296 # define R128_TEX_WRAP_S (1 << 10) 1297 # define R128_TEX_CLAMP_T_WRAP (0 << 11) 1298 # define R128_TEX_CLAMP_T_MIRROR (1 << 11) 1299 # define R128_TEX_CLAMP_T_CLAMP (2 << 11) 1300 # define R128_TEX_CLAMP_T_BORDER_COLOR (3 << 11) 1301 # define R128_TEX_CLAMP_T_MASK (3 << 11) 1302 # define R128_TEX_WRAP_T (1 << 13) 1303 # define R128_TEX_PERSPECTIVE_DISABLE (1 << 14) 1304 # define R128_DATATYPE_VQ (0 << 16) 1305 # define R128_DATATYPE_CI4 (1 << 16) 1306 # define R128_DATATYPE_CI8 (2 << 16) 1307 # define R128_DATATYPE_ARGB1555 (3 << 16) 1308 # define R128_DATATYPE_RGB565 (4 << 16) 1309 # define R128_DATATYPE_RGB888 (5 << 16) 1310 # define R128_DATATYPE_ARGB8888 (6 << 16) 1311 # define R128_DATATYPE_RGB332 (7 << 16) 1312 # define R128_DATATYPE_Y8 (8 << 16) 1313 # define R128_DATATYPE_RGB8 (9 << 16) 1314 # define R128_DATATYPE_CI16 (10 << 16) 1315 # define R128_DATATYPE_YVYU422 (11 << 16) 1316 # define R128_DATATYPE_VYUY422 (12 << 16) 1317 # define R128_DATATYPE_AYUV444 (14 << 16) 1318 # define R128_DATATYPE_ARGB4444 (15 << 16) 1319 # define R128_PALLETE_EITHER (0 << 20) 1320 # define R128_PALLETE_1 (1 << 20) 1321 # define R128_PALLETE_2 (2 << 20) 1322 # define R128_PSEUDOCOLOR_DT_RGB565 (0 << 24) 1323 # define R128_PSEUDOCOLOR_DT_ARGB1555 (1 << 24) 1324 # define R128_PSEUDOCOLOR_DT_ARGB4444 (2 << 24) 1325 #define R128_PRIM_TEXTURE_COMBINE_CNTL_C 0x1cb4 1326 # define R128_COMB_DIS (0 << 0) 1327 # define R128_COMB_COPY (1 << 0) 1328 # define R128_COMB_COPY_INP (2 << 0) 1329 # define R128_COMB_MODULATE (3 << 0) 1330 # define R128_COMB_MODULATE2X (4 << 0) 1331 # define R128_COMB_MODULATE4X (5 << 0) 1332 # define R128_COMB_ADD (6 << 0) 1333 # define R128_COMB_ADD_SIGNED (7 << 0) 1334 # define R128_COMB_BLEND_VERTEX (8 << 0) 1335 # define R128_COMB_BLEND_TEXTURE (9 << 0) 1336 # define R128_COMB_BLEND_CONST (10 << 0) 1337 # define R128_COMB_BLEND_PREMULT (11 << 0) 1338 # define R128_COMB_BLEND_PREV (12 << 0) 1339 # define R128_COMB_BLEND_PREMULT_INV (13 << 0) 1340 # define R128_COMB_ADD_SIGNED2X (14 << 0) 1341 # define R128_COMB_BLEND_CONST_COLOR (15 << 0) 1342 # define R128_COMB_MASK (15 << 0) 1343 # define R128_COLOR_FACTOR_CONST_COLOR (0 << 4) 1344 # define R128_COLOR_FACTOR_NCONST_COLOR (1 << 4) 1345 # define R128_COLOR_FACTOR_TEX (4 << 4) 1346 # define R128_COLOR_FACTOR_NTEX (5 << 4) 1347 # define R128_COLOR_FACTOR_ALPHA (6 << 4) 1348 # define R128_COLOR_FACTOR_NALPHA (7 << 4) 1349 # define R128_COLOR_FACTOR_PREV_COLOR (8 << 4) 1350 # define R128_COLOR_FACTOR_MASK (15 << 4) 1351 # define R128_COMB_FCN_MSB (1 << 8) 1352 # define R128_INPUT_FACTOR_CONST_COLOR (2 << 10) 1353 # define R128_INPUT_FACTOR_CONST_ALPHA (3 << 10) 1354 # define R128_INPUT_FACTOR_INT_COLOR (4 << 10) 1355 # define R128_INPUT_FACTOR_INT_ALPHA (5 << 10) 1356 # define R128_INPUT_FACTOR_MASK (15 << 10) 1357 # define R128_COMB_ALPHA_DIS (0 << 14) 1358 # define R128_COMB_ALPHA_COPY (1 << 14) 1359 # define R128_COMB_ALPHA_COPY_INP (2 << 14) 1360 # define R128_COMB_ALPHA_MODULATE (3 << 14) 1361 # define R128_COMB_ALPHA_MODULATE2X (4 << 14) 1362 # define R128_COMB_ALPHA_MODULATE4X (5 << 14) 1363 # define R128_COMB_ALPHA_ADD (6 << 14) 1364 # define R128_COMB_ALPHA_ADD_SIGNED (7 << 14) 1365 # define R128_COMB_ALPHA_ADD_SIGNED2X (14 << 14) 1366 # define R128_COMB_ALPHA_MASK (15 << 14) 1367 # define R128_ALPHA_FACTOR_TEX_ALPHA (6 << 18) 1368 # define R128_ALPHA_FACTOR_NTEX_ALPHA (7 << 18) 1369 # define R128_ALPHA_FACTOR_MASK (15 << 18) 1370 # define R128_INP_FACTOR_A_CONST_ALPHA (1 << 25) 1371 # define R128_INP_FACTOR_A_INT_ALPHA (2 << 25) 1372 # define R128_INP_FACTOR_A_MASK (7 << 25) 1373 #define R128_TEX_SIZE_PITCH_C 0x1cb8 1374 # define R128_TEX_PITCH_SHIFT 0 1375 # define R128_TEX_SIZE_SHIFT 4 1376 # define R128_TEX_HEIGHT_SHIFT 8 1377 # define R128_TEX_MIN_SIZE_SHIFT 12 1378 # define R128_SEC_TEX_PITCH_SHIFT 16 1379 # define R128_SEC_TEX_SIZE_SHIFT 20 1380 # define R128_SEC_TEX_HEIGHT_SHIFT 24 1381 # define R128_SEC_TEX_MIN_SIZE_SHIFT 28 1382 # define R128_TEX_PITCH_MASK (0x0f << 0) 1383 # define R128_TEX_SIZE_MASK (0x0f << 4) 1384 # define R128_TEX_HEIGHT_MASK (0x0f << 8) 1385 # define R128_TEX_MIN_SIZE_MASK (0x0f << 12) 1386 # define R128_SEC_TEX_PITCH_MASK (0x0f << 16) 1387 # define R128_SEC_TEX_SIZE_MASK (0x0f << 20) 1388 # define R128_SEC_TEX_HEIGHT_MASK (0x0f << 24) 1389 # define R128_SEC_TEX_MIN_SIZE_MASK (0x0fU << 28) 1390 # define R128_TEX_SIZE_PITCH_SHIFT 0 1391 # define R128_SEC_TEX_SIZE_PITCH_SHIFT 16 1392 # define R128_TEX_SIZE_PITCH_MASK (0xffff << 0) 1393 # define R128_SEC_TEX_SIZE_PITCH_MASK (0xffffU << 16) 1394 #define R128_PRIM_TEX_0_OFFSET_C 0x1cbc 1395 #define R128_PRIM_TEX_1_OFFSET_C 0x1cc0 1396 #define R128_PRIM_TEX_2_OFFSET_C 0x1cc4 1397 #define R128_PRIM_TEX_3_OFFSET_C 0x1cc8 1398 #define R128_PRIM_TEX_4_OFFSET_C 0x1ccc 1399 #define R128_PRIM_TEX_5_OFFSET_C 0x1cd0 1400 #define R128_PRIM_TEX_6_OFFSET_C 0x1cd4 1401 #define R128_PRIM_TEX_7_OFFSET_C 0x1cd8 1402 #define R128_PRIM_TEX_8_OFFSET_C 0x1cdc 1403 #define R128_PRIM_TEX_9_OFFSET_C 0x1ce0 1404 #define R128_PRIM_TEX_10_OFFSET_C 0x1ce4 1405 # define R128_TEX_NO_TILE (0 << 30) 1406 # define R128_TEX_TILED_BY_HOST (1 << 30) 1407 # define R128_TEX_TILED_BY_STORAGE (2U << 30) 1408 # define R128_TEX_TILED_BY_STORAGE2 (3U << 30) 1409 1410 #define R128_SEC_TEX_CNTL_C 0x1d00 1411 # define R128_SEC_SELECT_PRIM_ST (0 << 0) 1412 # define R128_SEC_SELECT_SEC_ST (1 << 0) 1413 #define R128_SEC_TEX_COMBINE_CNTL_C 0x1d04 1414 # define R128_INPUT_FACTOR_PREV_COLOR (8 << 10) 1415 # define R128_INPUT_FACTOR_PREV_ALPHA (9 << 10) 1416 # define R128_INP_FACTOR_A_PREV_ALPHA (4 << 25) 1417 #define R128_SEC_TEX_0_OFFSET_C 0x1d08 1418 #define R128_SEC_TEX_1_OFFSET_C 0x1d0c 1419 #define R128_SEC_TEX_2_OFFSET_C 0x1d10 1420 #define R128_SEC_TEX_3_OFFSET_C 0x1d14 1421 #define R128_SEC_TEX_4_OFFSET_C 0x1d18 1422 #define R128_SEC_TEX_5_OFFSET_C 0x1d1c 1423 #define R128_SEC_TEX_6_OFFSET_C 0x1d20 1424 #define R128_SEC_TEX_7_OFFSET_C 0x1d24 1425 #define R128_SEC_TEX_8_OFFSET_C 0x1d28 1426 #define R128_SEC_TEX_9_OFFSET_C 0x1d2c 1427 #define R128_SEC_TEX_10_OFFSET_C 0x1d30 1428 #define R128_CONSTANT_COLOR_C 0x1d34 1429 # define R128_CONSTANT_BLUE_SHIFT 0 1430 # define R128_CONSTANT_GREEN_SHIFT 8 1431 # define R128_CONSTANT_RED_SHIFT 16 1432 # define R128_CONSTANT_ALPHA_SHIFT 24 1433 #define R128_PRIM_TEXTURE_BORDER_COLOR_C 0x1d38 1434 # define R128_PRIM_TEX_BORDER_BLUE_SHIFT 0 1435 # define R128_PRIM_TEX_BORDER_GREEN_SHIFT 8 1436 # define R128_PRIM_TEX_BORDER_RED_SHIFT 16 1437 # define R128_PRIM_TEX_BORDER_ALPHA_SHIFT 24 1438 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c 1439 # define R128_SEC_TEX_BORDER_BLUE_SHIFT 0 1440 # define R128_SEC_TEX_BORDER_GREEN_SHIFT 8 1441 # define R128_SEC_TEX_BORDER_RED_SHIFT 16 1442 # define R128_SEC_TEX_BORDER_ALPHA_SHIFT 24 1443 #define R128_STEN_REF_MASK_C 0x1d40 1444 # define R128_STEN_REFERENCE_SHIFT 0 1445 # define R128_STEN_MASK_SHIFT 16 1446 # define R128_STEN_WRITE_MASK_SHIFT 24 1447 #define R128_PLANE_3D_MASK_C 0x1d44 1448 #define R128_TEX_CACHE_STAT_COUNT 0x1974 1449 1450 1451 /* Constants */ 1452 #define R128_AGP_TEX_OFFSET 0x02000000 1453 1454 #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 1455 1456 /* CCE packet types */ 1457 #define R128_CCE_PACKET0 0x00000000 1458 #define R128_CCE_PACKET0_ONE_REG_WR 0x00008000 1459 #define R128_CCE_PACKET1 0x40000000 1460 #define R128_CCE_PACKET2 0x80000000 1461 #define R128_CCE_PACKET3 0xC0000000 1462 #define R128_CCE_PACKET3_NOP 0xC0001000 1463 #define R128_CCE_PACKET3_PAINT 0xC0001100 1464 #define R128_CCE_PACKET3_BITBLT 0xC0001200 1465 #define R128_CCE_PACKET3_SMALLTEXT 0xC0001300 1466 #define R128_CCE_PACKET3_HOSTDATA_BLT 0xC0001400 1467 #define R128_CCE_PACKET3_POLYLINE 0xC0001500 1468 #define R128_CCE_PACKET3_SCALING 0xC0001600 1469 #define R128_CCE_PACKET3_TRANS_SCALING 0xC0001700 1470 #define R128_CCE_PACKET3_POLYSCANLINES 0xC0001800 1471 #define R128_CCE_PACKET3_NEXT_CHAR 0xC0001900 1472 #define R128_CCE_PACKET3_PAINT_MULTI 0xC0001A00 1473 #define R128_CCE_PACKET3_BITBLT_MULTI 0xC0001B00 1474 #define R128_CCE_PACKET3_PLY_NEXTSCAN 0xC0001D00 1475 #define R128_CCE_PACKET3_SET_SCISSORS 0xC0001E00 1476 #define R128_CCE_PACKET3_SET_MODE24BPP 0xC0001F00 1477 #define R128_CCE_PACKET3_CNTL_PAINT 0xC0009100 1478 #define R128_CCE_PACKET3_CNTL_BITBLT 0xC0009200 1479 #define R128_CCE_PACKET3_CNTL_SMALLTEXT 0xC0009300 1480 #define R128_CCE_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 1481 #define R128_CCE_PACKET3_CNTL_POLYLINE 0xC0009500 1482 #define R128_CCE_PACKET3_CNTL_SCALING 0xC0009600 1483 #define R128_CCE_PACKET3_CNTL_TRANS_SCALING 0xC0009700 1484 #define R128_CCE_PACKET3_CNTL_POLYSCANLINES 0xC0009800 1485 #define R128_CCE_PACKET3_CNTL_NEXT_CHAR 0xC0009900 1486 #define R128_CCE_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 1487 #define R128_CCE_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 1488 #define R128_CCE_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 1489 #define R128_CCE_PACKET3_3D_SAVE_CONTEXT 0xC0002000 1490 #define R128_CCE_PACKET3_3D_PLAY_CONTEXT 0xC0002100 1491 #define R128_CCE_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 1492 #define R128_CCE_PACKET3_3D_RNDR_GEN_PRIM 0xC0002500 1493 #define R128_CCE_PACKET3_LOAD_PALETTE 0xC0002C00 1494 #define R128_CCE_PACKET3_PURGE 0xC0002D00 1495 #define R128_CCE_PACKET3_NEXT_VERTEX_BUNDLE 0xC0002E00 1496 # define R128_CCE_PACKET_MASK 0xC0000000 1497 # define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 1498 # define R128_CCE_PACKET_MAX_DWORDS (1 << 12) 1499 # define R128_CCE_PACKET0_REG_MASK 0x000007ff 1500 # define R128_CCE_PACKET1_REG0_MASK 0x000007ff 1501 # define R128_CCE_PACKET1_REG1_MASK 0x003ff800 1502 1503 #define R128_CCE_VC_FRMT_RHW 0x00000001 1504 #define R128_CCE_VC_FRMT_DIFFUSE_BGR 0x00000002 1505 #define R128_CCE_VC_FRMT_DIFFUSE_A 0x00000004 1506 #define R128_CCE_VC_FRMT_DIFFUSE_ARGB 0x00000008 1507 #define R128_CCE_VC_FRMT_SPEC_BGR 0x00000010 1508 #define R128_CCE_VC_FRMT_SPEC_F 0x00000020 1509 #define R128_CCE_VC_FRMT_SPEC_FRGB 0x00000040 1510 #define R128_CCE_VC_FRMT_S_T 0x00000080 1511 #define R128_CCE_VC_FRMT_S2_T2 0x00000100 1512 #define R128_CCE_VC_FRMT_RHW2 0x00000200 1513 1514 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 1515 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 1516 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 1517 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 1518 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 1519 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 1520 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 1521 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 1522 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 1523 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 1524 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 1525 #define R128_CCE_VC_CNTL_NUM_SHIFT 16 1526 1527 /* hmm copied blindly (no specs) from radeon.h ... */ 1528 #define R128_RE_TOP_LEFT 0x26c0 1529 # define R128_RE_LEFT_SHIFT 0 1530 # define R128_RE_TOP_SHIFT 16 1531 #define R128_RE_WIDTH_HEIGHT 0x1c44 1532 # define R128_RE_WIDTH_SHIFT 0 1533 # define R128_RE_HEIGHT_SHIFT 16 1534 1535 #endif 1536
Indexes created Fri Jul 24 00:25:35 UTC 2026