| /src/external/gpl3/gcc/dist/libgcc/config/mips/ |
| crtn.S | 31 #define RA $7
33 #define RA $31
39 ld RA,40($sp)
42 lw RA,20($sp)
45 j RA
50 ld RA,40($sp)
53 lw RA,20($sp)
56 j RA
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/mips/ |
| crtn.S | 31 #define RA $7
33 #define RA $31
39 ld RA,40($sp)
42 lw RA,20($sp)
45 j RA
50 ld RA,40($sp)
53 lw RA,20($sp)
56 j RA
|
| /src/sys/external/bsd/gnu-efi/dist/inc/mips64el/ |
| efisetjmp_arch.h | 10 UINT64 RA;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| RDFDeadCode.cpp | 88 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) {
89 if (!LiveNodes.count(RA.Id))
90 WorkQ.push_back(RA.Id);
135 auto RA = DFG.addr<RefNode*>(N);
136 if (DFG.IsDef(RA))
137 processDef(RA, WorkQ);
139 processUse(RA, WorkQ);
145 auto RA = DFG.addr<RefNode*>(N);
146 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n";
159 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)
[all...] |
| RDFCopy.cpp | 90 NodeAddr<RefNode*> RA = L.getNearestAliasedRef(RefRR, IA);
91 if (RA.Id != 0) {
92 if (RA.Addr->getKind() == NodeAttrs::Def)
93 return RA.Id;
94 assert(RA.Addr->getKind() == NodeAttrs::Use);
95 if (NodeId RD = RA.Addr->getReachingDef())
|
| HexagonEarlyIfConv.cpp | 472 const MachineOperand &RA = MI.getOperand(1);
474 assert(RA.isReg() && RB.isReg());
476 if (RA.getSubReg() != 0 || RB.getSubReg() != 0) {
480 const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCMacroFusion.cpp | 40 // load rt, ra, rx
87 // [addi rt,ra,si - lxvd2x xt,ra,rb] etc.
89 // lxvd2x(ra) cannot be zero
90 const MachineOperand &RA = SecondMI.getOperand(1);
91 if (!RA.isReg())
94 return Register::isVirtualRegister(RA.getReg()) ||
95 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8);
97 // [addis rt,ra,si - ld rt,ds(ra)] etc
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Object/ |
| RelocationResolver.cpp | 430 int64_t RA = Addend;
436 return (S + RA) & 0xFFFFFFFF;
438 return (S + RA - Offset) & 0xFFFFFFFF;
440 return S + RA;
442 return (A & 0xC0) | ((S + RA) & 0x3F);
444 return (A & 0xC0) | (((A & 0x3F) - (S + RA)) & 0x3F);
446 return (A + (S + RA)) & 0xFF;
448 return (A - (S + RA)) & 0xFF;
450 return (A + (S + RA)) & 0xFFFF;
452 return (A - (S + RA)) & 0xFFFF
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 73 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
76 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
|
| /src/external/gpl3/gdb.old/dist/sim/microblaze/ |
| microblaze.h | 30 #define RA CPU.regs[ra]
|
| /src/external/gpl3/gdb/dist/sim/microblaze/ |
| microblaze.h | 30 #define RA CPU.regs[ra]
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| ScalarEvolution.cpp | 632 const auto *RA = cast<Argument>(RV);
633 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo();
732 const APInt &RA = RC->getAPInt();
733 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth();
736 return LA.ult(RA) ? -1 : 1;
741 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS);
746 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop();
759 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands();
766 LA->getOperand(i), RA->getOperand(i), DT,
5463 const SCEV *RA = getSCEV(FalseVal)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 308 unsigned RA = (TT.getArch() == Triple::x86_64)
313 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
314 X86_MC::getDwarfRegFlavour(TT, true), RA);
|
| /src/external/bsd/nsd/dist/ |
| packet.h | 33 * |QR| Opcode |AA|TC|RD|RA| Z|AD|CD| RCODE |
107 #define RA(packet) (*buffer_at((packet), 3) & RA_MASK)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 801 // RA and return address is taken, because it has already been added in
803 // It's killed at the spill, unless the register is RA and return address
806 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
867 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
871 // Mark $ra and $fp as used if function has dedicated frame pointer.
873 setAliasRegs(MF, SavedRegs, RA);
|
| MipsSEInstrInfo.cpp | 695 .addReg(Mips::RA, RegState::Undef);
892 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
898 // addu $ra, $v0, $zero
900 // jr $ra (via RetRA)
906 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 705 APInt RA = Rem->getValue().abs();
706 if (RA.isPowerOf2()) {
707 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
710 APInt LowBits = RA - 1;
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| FunctionComparator.cpp | 120 Attribute RA = *RI;
121 if (LA.isTypeAttribute() && RA.isTypeAttribute()) {
122 if (LA.getKindAsEnum() != RA.getKindAsEnum())
123 return cmpNumbers(LA.getKindAsEnum(), RA.getKindAsEnum());
126 Type *TyR = RA.getValueAsType();
139 if (LA < RA)
141 if (RA < LA)
309 const ConstantArray *RA = cast<ConstantArray>(R);
316 cast<Constant>(RA->getOperand(i))))
|
| /src/external/bsd/pcc/dist/pcc/arch/mips/ |
| macdefs.h | 180 #define RA 31
295 { -1 }, /* $ra */ \
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| alpha-opc.c | 57 /* The RB field when it is the same as the RA field in the same insn.
59 the RA field into the RB field, and the extraction function just
208 #define RA (UNUSED + 1)
210 #define RB (RA + 1)
240 /* The RB field when it must be the same as the RA field. */
248 /* The RC field when it can *default* to RA. */
258 /* The FC field when it can *default* to RA. */
412 #define ARG_BRA { RA, BDISP }
416 #define ARG_MEM { RA, MDISP, PRB }
418 #define ARG_OPR { RA, RB, DRC1
[all...] |
| nds32-asm.c | 105 {"ra", 15, 5, 0, HW_GPR, NULL},
226 #define RA(r) (r << 15)
233 {"lbi", "=rt,[%ra{+%i15s}]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
234 {"lhi", "=rt,[%ra{+%i15s1}]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
235 {"lwi", "=rt,[%ra{+%i15s2}]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
236 {"lbi.bi", "=rt,[%ra],%i15s", OP6 (LBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
237 {"lhi.bi", "=rt,[%ra],%i15s1", OP6 (LHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
238 {"lwi.bi", "=rt,[%ra],%i15s2", OP6 (LWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
239 {"sbi", "%rt,[%ra{+%i15s}]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
240 {"shi", "%rt,[%ra{+%i15s1}]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL}
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| alpha-opc.c | 57 /* The RB field when it is the same as the RA field in the same insn.
59 the RA field into the RB field, and the extraction function just
208 #define RA (UNUSED + 1)
210 #define RB (RA + 1)
240 /* The RB field when it must be the same as the RA field. */
248 /* The RC field when it can *default* to RA. */
258 /* The FC field when it can *default* to RA. */
412 #define ARG_BRA { RA, BDISP }
416 #define ARG_MEM { RA, MDISP, PRB }
418 #define ARG_OPR { RA, RB, DRC1
[all...] |
| nds32-asm.c | 105 {"ra", 15, 5, 0, HW_GPR, NULL},
226 #define RA(r) (r << 15)
233 {"lbi", "=rt,[%ra{+%i15s}]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
234 {"lhi", "=rt,[%ra{+%i15s1}]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
235 {"lwi", "=rt,[%ra{+%i15s2}]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
236 {"lbi.bi", "=rt,[%ra],%i15s", OP6 (LBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
237 {"lhi.bi", "=rt,[%ra],%i15s1", OP6 (LHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
238 {"lwi.bi", "=rt,[%ra],%i15s2", OP6 (LWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
239 {"sbi", "%rt,[%ra{+%i15s}]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
240 {"shi", "%rt,[%ra{+%i15s1}]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL}
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| alpha-opc.c | 57 /* The RB field when it is the same as the RA field in the same insn.
59 the RA field into the RB field, and the extraction function just
208 #define RA (UNUSED + 1)
210 #define RB (RA + 1)
240 /* The RB field when it must be the same as the RA field. */
248 /* The RC field when it can *default* to RA. */
258 /* The FC field when it can *default* to RA. */
412 #define ARG_BRA { RA, BDISP }
416 #define ARG_MEM { RA, MDISP, PRB }
418 #define ARG_OPR { RA, RB, DRC1
[all...] |
| nds32-asm.c | 105 {"ra", 15, 5, 0, HW_GPR, NULL},
226 #define RA(r) (r << 15)
233 {"lbi", "=rt,[%ra{+%i15s}]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
234 {"lhi", "=rt,[%ra{+%i15s1}]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
235 {"lwi", "=rt,[%ra{+%i15s2}]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
236 {"lbi.bi", "=rt,[%ra],%i15s", OP6 (LBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
237 {"lhi.bi", "=rt,[%ra],%i15s1", OP6 (LHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
238 {"lwi.bi", "=rt,[%ra],%i15s2", OP6 (LWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
239 {"sbi", "%rt,[%ra{+%i15s}]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
240 {"shi", "%rt,[%ra{+%i15s1}]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL}
[all...] |
