1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29 #ifdef HAVE_CONFIG_H 30 #include "config.h" 31 #endif 32 33 #include <string.h> 34 #include <stdio.h> 35 36 /* X and server generic header files */ 37 #include "xf86.h" 38 #include "xf86_OSproc.h" 39 #include "vgaHW.h" 40 #include "xf86Modes.h" 41 42 /* Driver data structures */ 43 #include "radeon.h" 44 #include "radeon_reg.h" 45 #include "radeon_macros.h" 46 #include "radeon_probe.h" 47 #include "radeon_version.h" 48 #include "radeon_tv.h" 49 #include "radeon_atombios.h" 50 51 #include "ati_pciids_gen.h" 52 53 static RADEONMonitorType radeon_detect_tv(ScrnInfoPtr pScrn); 54 static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color); 55 static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color); 56 static RADEONMonitorType radeon_detect_ext_dac(ScrnInfoPtr pScrn); 57 58 extern Bool 59 RADEONI2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, char *name, RADEONI2CBusPtr pRADEONI2CBus); 60 61 static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = 62 { 63 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_UNKNOW*/ 64 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_LEGACY*/ 65 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RADEON*/ 66 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV100*/ 67 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS100*/ 68 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV200*/ 69 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS200*/ 70 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R200*/ 71 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV250*/ 72 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS300*/ 73 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /*CHIP_FAMILY_RV280*/ 74 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R300*/ 75 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R350*/ 76 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV350*/ 77 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV380*/ 78 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R420*/ 79 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV410*/ /* FIXME: just values from r420 used... */ 80 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */ 81 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS480*/ /* FIXME: just values from rv380 used... */ 82 }; 83 84 static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = 85 { 86 0x00000000, /* unknown */ 87 0x00000000, /* legacy */ 88 0x00000000, /* r100 */ 89 0x00280000, /* rv100 */ 90 0x00000000, /* rs100 */ 91 0x00880000, /* rv200 */ 92 0x00000000, /* rs200 */ 93 0x00000000, /* r200 */ 94 0x00770000, /* rv250 */ 95 0x00290000, /* rs300 */ 96 0x00560000, /* rv280 */ 97 0x00780000, /* r300 */ 98 0x00770000, /* r350 */ 99 0x00780000, /* rv350 */ 100 0x00780000, /* rv380 */ 101 0x01080000, /* r420 */ 102 0x01080000, /* rv410 */ /* FIXME: just values from r420 used... */ 103 0x00780000, /* rs400 */ /* FIXME: just values from rv380 used... */ 104 0x00780000, /* rs480 */ /* FIXME: just values from rv380 used... */ 105 }; 106 107 void 108 RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac) 109 { 110 RADEONInfoPtr info = RADEONPTR(pScrn); 111 112 if (!RADEONGetDAC2InfoFromBIOS(pScrn, tvdac)) { 113 tvdac->ps2_tvdac_adj = default_tvdac_adj[info->ChipFamily]; 114 if (info->IsMobility) { /* some mobility chips may different */ 115 if (info->ChipFamily == CHIP_FAMILY_RV250) 116 tvdac->ps2_tvdac_adj = 0x00880000; 117 } 118 tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; 119 tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; 120 } 121 } 122 123 void 124 RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds) 125 { 126 RADEONInfoPtr info = RADEONPTR(pScrn); 127 int i; 128 129 for (i = 0; i < 4; i++) { 130 tmds->tmds_pll[i].value = default_tmds_pll[info->ChipFamily][i].value; 131 tmds->tmds_pll[i].freq = default_tmds_pll[info->ChipFamily][i].freq; 132 } 133 } 134 135 void 136 RADEONGetTMDSInfo(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds) 137 { 138 int i; 139 140 for (i = 0; i < 4; i++) { 141 tmds->tmds_pll[i].value = 0; 142 tmds->tmds_pll[i].freq = 0; 143 } 144 145 if (!RADEONGetTMDSInfoFromBIOS(pScrn, tmds)) 146 RADEONGetTMDSInfoFromTable(pScrn, tmds); 147 } 148 149 void 150 RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo) 151 { 152 RADEONInfoPtr info = RADEONPTR(pScrn); 153 154 if (!info->IsAtomBios) { 155 #if defined(__powerpc__) 156 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 157 dvo->dvo_i2c_slave_addr = 0x70; 158 #else 159 if (!RADEONGetExtTMDSInfoFromBIOS(pScrn, dvo)) { 160 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 161 dvo->dvo_i2c_slave_addr = 0x70; 162 } 163 #endif 164 if (RADEONI2CInit(pScrn, &dvo->pI2CBus, "DVO", &dvo->dvo_i2c)) { 165 dvo->DVOChip = 166 RADEONDVODeviceInit(dvo->pI2CBus, dvo->dvo_i2c_slave_addr); 167 if (!dvo->DVOChip) 168 free(dvo->pI2CBus); 169 } 170 } 171 } 172 173 static void 174 RADEONGetPanelInfoFromReg (ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) 175 { 176 RADEONInfoPtr info = RADEONPTR(pScrn); 177 unsigned char *RADEONMMIO = info->MMIO; 178 radeon_native_mode_ptr native_mode = &lvds->native_mode; 179 uint32_t fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); 180 uint32_t fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); 181 182 lvds->PanelPwrDly = 200; 183 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) { 184 native_mode->PanelYRes = ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 185 RADEON_VERT_PANEL_SHIFT) + 1; 186 } else { 187 native_mode->PanelYRes = (INREG(RADEON_CRTC_V_TOTAL_DISP)>>16) + 1; 188 } 189 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) { 190 native_mode->PanelXRes = (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 191 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 192 } else { 193 native_mode->PanelXRes = ((INREG(RADEON_CRTC_H_TOTAL_DISP)>>16) + 1) * 8; 194 } 195 196 if ((native_mode->PanelXRes < 640) || (native_mode->PanelYRes < 480)) { 197 native_mode->PanelXRes = 640; 198 native_mode->PanelYRes = 480; 199 } 200 201 // move this to crtc function 202 if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) { 203 uint32_t ppll_div_sel, ppll_val; 204 205 ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 206 RADEONPllErrataAfterIndex(info); 207 ppll_val = INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel); 208 if ((ppll_val & 0x000707ff) == 0x1bb) 209 goto noprobe; 210 info->FeedbackDivider = ppll_val & 0x7ff; 211 info->PostDivider = (ppll_val >> 16) & 0x7; 212 info->RefDivider = info->pll.reference_div; 213 info->UseBiosDividers = TRUE; 214 215 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 216 "Existing panel PLL dividers will be used.\n"); 217 } 218 noprobe: 219 220 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 221 "Panel size %dx%d is derived, this may not be correct.\n" 222 "If not, use PanelSize option to overwrite this setting\n", 223 native_mode->PanelXRes, native_mode->PanelYRes); 224 } 225 226 void 227 RADEONGetLVDSInfo (ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) 228 { 229 RADEONInfoPtr info = RADEONPTR(pScrn); 230 radeon_native_mode_ptr native_mode = &lvds->native_mode; 231 const char* s; 232 233 if (!RADEONGetLVDSInfoFromBIOS(pScrn, lvds)) 234 RADEONGetPanelInfoFromReg(pScrn, lvds); 235 236 if ((s = xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) { 237 lvds->PanelPwrDly = 200; 238 if (sscanf (s, "%dx%d", &native_mode->PanelXRes, &native_mode->PanelYRes) != 2) { 239 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Invalid PanelSize option: %s\n", s); 240 RADEONGetPanelInfoFromReg(pScrn, lvds); 241 } 242 } 243 } 244 245 void 246 RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, 247 RADEONSavePtr restore) 248 { 249 RADEONInfoPtr info = RADEONPTR(pScrn); 250 unsigned char *RADEONMMIO = info->MMIO; 251 252 if (IS_R300_VARIANT) 253 OUTREGP(RADEON_GPIOPAD_A, restore->gpiopad_a, ~1); 254 255 OUTREGP(RADEON_DAC_CNTL, 256 restore->dac_cntl, 257 RADEON_DAC_RANGE_CNTL | 258 RADEON_DAC_BLANKING); 259 260 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); 261 262 if ((info->ChipFamily != CHIP_FAMILY_RADEON) && 263 (info->ChipFamily != CHIP_FAMILY_R200)) 264 OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); 265 266 OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl); 267 268 if ((info->ChipFamily == CHIP_FAMILY_R200) || 269 IS_R300_VARIANT) { 270 OUTREG(RADEON_DISP_TV_OUT_CNTL, restore->disp_tv_out_cntl); 271 } else { 272 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug); 273 } 274 275 OUTREG(RADEON_DAC_MACRO_CNTL, restore->dac_macro_cntl); 276 277 /* R200 DAC connected via DVO */ 278 if (info->ChipFamily == CHIP_FAMILY_R200) 279 OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); 280 } 281 282 283 /* Write TMDS registers */ 284 void 285 RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) 286 { 287 RADEONInfoPtr info = RADEONPTR(pScrn); 288 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 289 unsigned char *RADEONMMIO = info->MMIO; 290 291 OUTREG(RADEON_TMDS_PLL_CNTL, restore->tmds_pll_cntl); 292 OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl); 293 OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl); 294 295 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 296 (info->ChipFamily == CHIP_FAMILY_RS480)) { 297 OUTREG(RS400_FP_2ND_GEN_CNTL, restore->fp_2nd_gen_cntl); 298 /*OUTREG(RS400_TMDS2_CNTL, restore->tmds2_cntl);*/ 299 OUTREG(RS400_TMDS2_TRANSMITTER_CNTL, restore->tmds2_transmitter_cntl); 300 } 301 302 /* old AIW Radeon has some BIOS initialization problem 303 * with display buffer underflow, only occurs to DFP 304 */ 305 if (!pRADEONEnt->HasCRTC2) 306 OUTREG(RADEON_GRPH_BUFFER_CNTL, 307 INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000); 308 309 } 310 311 /* Write FP2 registers */ 312 void 313 RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) 314 { 315 RADEONInfoPtr info = RADEONPTR(pScrn); 316 unsigned char *RADEONMMIO = info->MMIO; 317 318 OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); 319 320 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 321 (info->ChipFamily == CHIP_FAMILY_RS480)) 322 OUTREG(RS400_FP2_2_GEN_CNTL, restore->fp2_2_gen_cntl); 323 } 324 325 /* Write RMX registers */ 326 void 327 RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) 328 { 329 RADEONInfoPtr info = RADEONPTR(pScrn); 330 unsigned char *RADEONMMIO = info->MMIO; 331 332 OUTREG(RADEON_FP_HORZ_STRETCH, restore->fp_horz_stretch); 333 OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch); 334 OUTREG(RADEON_CRTC_MORE_CNTL, restore->crtc_more_cntl); 335 OUTREG(RADEON_FP_HORZ_VERT_ACTIVE, restore->fp_horz_vert_active); 336 OUTREG(RADEON_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid); 337 OUTREG(RADEON_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid); 338 OUTREG(RADEON_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp); 339 OUTREG(RADEON_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp); 340 341 } 342 343 /* Write LVDS registers */ 344 void 345 RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) 346 { 347 RADEONInfoPtr info = RADEONPTR(pScrn); 348 unsigned char *RADEONMMIO = info->MMIO; 349 350 if (info->IsMobility) { 351 OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl); 352 /*OUTREG(RADEON_LVDS_PLL_CNTL, restore->lvds_pll_cntl);*/ 353 354 if (info->ChipFamily == CHIP_FAMILY_RV410) { 355 OUTREG(RADEON_CLOCK_CNTL_INDEX, 0); 356 } 357 } 358 359 } 360 361 void 362 RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 363 { 364 RADEONInfoPtr info = RADEONPTR(pScrn); 365 unsigned char *RADEONMMIO = info->MMIO; 366 367 save->dac_cntl = INREG(RADEON_DAC_CNTL); 368 save->dac2_cntl = INREG(RADEON_DAC_CNTL2); 369 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); 370 save->disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL); 371 save->disp_tv_out_cntl = INREG(RADEON_DISP_TV_OUT_CNTL); 372 save->disp_hw_debug = INREG(RADEON_DISP_HW_DEBUG); 373 save->dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); 374 save->gpiopad_a = INREG(RADEON_GPIOPAD_A); 375 376 } 377 378 /* Read flat panel registers */ 379 void 380 RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 381 { 382 RADEONInfoPtr info = RADEONPTR(pScrn); 383 unsigned char *RADEONMMIO = info->MMIO; 384 385 save->fp_gen_cntl = INREG(RADEON_FP_GEN_CNTL); 386 save->fp2_gen_cntl = INREG (RADEON_FP2_GEN_CNTL); 387 save->fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); 388 save->fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); 389 save->fp_horz_vert_active = INREG(RADEON_FP_HORZ_VERT_ACTIVE); 390 save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL); 391 save->lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL); 392 save->lvds_pll_cntl = INREG(RADEON_LVDS_PLL_CNTL); 393 save->tmds_pll_cntl = INREG(RADEON_TMDS_PLL_CNTL); 394 save->tmds_transmitter_cntl= INREG(RADEON_TMDS_TRANSMITTER_CNTL); 395 396 save->fp_h_sync_strt_wid = INREG(RADEON_FP_H_SYNC_STRT_WID); 397 save->fp_v_sync_strt_wid = INREG(RADEON_FP_V_SYNC_STRT_WID); 398 save->fp_crtc_h_total_disp = INREG(RADEON_FP_CRTC_H_TOTAL_DISP); 399 save->fp_crtc_v_total_disp = INREG(RADEON_FP_CRTC_V_TOTAL_DISP); 400 401 if (info->ChipFamily == CHIP_FAMILY_RV280) { 402 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ 403 save->tmds_pll_cntl ^= (1 << 22); 404 } 405 406 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 407 (info->ChipFamily == CHIP_FAMILY_RS480)) { 408 save->fp_2nd_gen_cntl = INREG(RS400_FP_2ND_GEN_CNTL); 409 save->fp2_2_gen_cntl = INREG(RS400_FP2_2_GEN_CNTL); 410 save->tmds2_cntl = INREG(RS400_TMDS2_CNTL); 411 save->tmds2_transmitter_cntl = INREG(RS400_TMDS2_TRANSMITTER_CNTL); 412 } 413 414 } 415 416 Bool 417 RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch) 418 { 419 if (!xf86I2CReadByte(dvo, addr, ch)) { 420 xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, 421 "Unable to read from %s Slave %d.\n", 422 dvo->pI2CBus->BusName, dvo->SlaveAddr); 423 return FALSE; 424 } 425 return TRUE; 426 } 427 428 Bool 429 RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch) 430 { 431 if (!xf86I2CWriteByte(dvo, addr, ch)) { 432 xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, 433 "Unable to write to %s Slave %d.\n", 434 dvo->pI2CBus->BusName, dvo->SlaveAddr); 435 return FALSE; 436 } 437 return TRUE; 438 } 439 440 I2CDevPtr 441 RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr) 442 { 443 I2CDevPtr dvo; 444 445 dvo = calloc(1, sizeof(I2CDevRec)); 446 if (dvo == NULL) 447 return NULL; 448 449 dvo->DevName = "RADEON DVO Controller"; 450 dvo->SlaveAddr = addr; 451 dvo->pI2CBus = b; 452 dvo->StartTimeout = b->StartTimeout; 453 dvo->BitTimeout = b->BitTimeout; 454 dvo->AcknTimeout = b->AcknTimeout; 455 dvo->ByteTimeout = b->ByteTimeout; 456 457 if (xf86I2CDevInit(dvo)) { 458 return dvo; 459 } 460 461 free(dvo); 462 return NULL; 463 } 464 465 static void 466 RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) 467 { 468 RADEONInfoPtr info = RADEONPTR(pScrn); 469 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 470 radeon_dvo_ptr dvo = NULL; 471 472 if (radeon_encoder == NULL) 473 return; 474 475 dvo = (radeon_dvo_ptr)radeon_encoder->dev_priv; 476 477 if (dvo == NULL) 478 return; 479 480 if (!dvo->DVOChip) 481 return; 482 483 RADEONI2CDoLock(output, dvo->pI2CBus, TRUE); 484 if (!RADEONInitExtTMDSInfoFromBIOS(output)) { 485 if (dvo->DVOChip) { 486 switch(info->ext_tmds_chip) { 487 case RADEON_SIL_164: 488 RADEONDVOWriteByte(dvo->DVOChip, 0x08, 0x30); 489 RADEONDVOWriteByte(dvo->DVOChip, 0x09, 0x00); 490 RADEONDVOWriteByte(dvo->DVOChip, 0x0a, 0x90); 491 RADEONDVOWriteByte(dvo->DVOChip, 0x0c, 0x89); 492 RADEONDVOWriteByte(dvo->DVOChip, 0x08, 0x3b); 493 break; 494 #if 0 495 /* needs work see bug 10418 */ 496 case RADEON_SIL_1178: 497 RADEONDVOWriteByte(dvo->DVOChip, 0x0f, 0x44); 498 RADEONDVOWriteByte(dvo->DVOChip, 0x0f, 0x4c); 499 RADEONDVOWriteByte(dvo->DVOChip, 0x0e, 0x01); 500 RADEONDVOWriteByte(dvo->DVOChip, 0x0a, 0x80); 501 RADEONDVOWriteByte(dvo->DVOChip, 0x09, 0x30); 502 RADEONDVOWriteByte(dvo->DVOChip, 0x0c, 0xc9); 503 RADEONDVOWriteByte(dvo->DVOChip, 0x0d, 0x70); 504 RADEONDVOWriteByte(dvo->DVOChip, 0x08, 0x32); 505 RADEONDVOWriteByte(dvo->DVOChip, 0x08, 0x33); 506 break; 507 #endif 508 default: 509 break; 510 } 511 } 512 } 513 RADEONI2CDoLock(output, dvo->pI2CBus, FALSE); 514 } 515 516 #if 0 517 static RADEONMonitorType 518 RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) 519 { 520 RADEONInfoPtr info = RADEONPTR(pScrn); 521 unsigned char *RADEONMMIO = info->MMIO; 522 int bConnected = 0; 523 524 /* the monitor either wasn't connected or it is a non-DDC CRT. 525 * try to probe it 526 */ 527 if(IsCrtDac) { 528 unsigned long ulOrigVCLK_ECP_CNTL; 529 unsigned long ulOrigDAC_CNTL; 530 unsigned long ulOrigDAC_MACRO_CNTL; 531 unsigned long ulOrigDAC_EXT_CNTL; 532 unsigned long ulOrigCRTC_EXT_CNTL; 533 unsigned long ulData; 534 unsigned long ulMask; 535 536 ulOrigVCLK_ECP_CNTL = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 537 538 ulData = ulOrigVCLK_ECP_CNTL; 539 ulData &= ~(RADEON_PIXCLK_ALWAYS_ONb 540 | RADEON_PIXCLK_DAC_ALWAYS_ONb); 541 ulMask = ~(RADEON_PIXCLK_ALWAYS_ONb 542 |RADEON_PIXCLK_DAC_ALWAYS_ONb); 543 OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask); 544 545 ulOrigCRTC_EXT_CNTL = INREG(RADEON_CRTC_EXT_CNTL); 546 ulData = ulOrigCRTC_EXT_CNTL; 547 ulData |= RADEON_CRTC_CRT_ON; 548 OUTREG(RADEON_CRTC_EXT_CNTL, ulData); 549 550 ulOrigDAC_EXT_CNTL = INREG(RADEON_DAC_EXT_CNTL); 551 ulData = ulOrigDAC_EXT_CNTL; 552 ulData &= ~RADEON_DAC_FORCE_DATA_MASK; 553 ulData |= (RADEON_DAC_FORCE_BLANK_OFF_EN 554 |RADEON_DAC_FORCE_DATA_EN 555 |RADEON_DAC_FORCE_DATA_SEL_MASK); 556 if ((info->ChipFamily == CHIP_FAMILY_RV250) || 557 (info->ChipFamily == CHIP_FAMILY_RV280)) 558 ulData |= (0x01b6 << RADEON_DAC_FORCE_DATA_SHIFT); 559 else 560 ulData |= (0x01ac << RADEON_DAC_FORCE_DATA_SHIFT); 561 562 OUTREG(RADEON_DAC_EXT_CNTL, ulData); 563 564 /* turn on power so testing can go through */ 565 ulOrigDAC_CNTL = INREG(RADEON_DAC_CNTL); 566 ulOrigDAC_CNTL &= ~RADEON_DAC_PDWN; 567 OUTREG(RADEON_DAC_CNTL, ulOrigDAC_CNTL); 568 569 ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL); 570 ulOrigDAC_MACRO_CNTL &= ~(RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | 571 RADEON_DAC_PDWN_B); 572 OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL); 573 574 /* Enable comparators and set DAC range to PS2 (VGA) output level */ 575 ulData = ulOrigDAC_CNTL; 576 ulData |= RADEON_DAC_CMP_EN; 577 ulData &= ~RADEON_DAC_RANGE_CNTL_MASK; 578 ulData |= 0x2; 579 OUTREG(RADEON_DAC_CNTL, ulData); 580 581 /* Settle down */ 582 usleep(10000); 583 584 /* Read comparators */ 585 ulData = INREG(RADEON_DAC_CNTL); 586 bConnected = (RADEON_DAC_CMP_OUTPUT & ulData)?1:0; 587 588 /* Restore things */ 589 ulData = ulOrigVCLK_ECP_CNTL; 590 ulMask = 0xFFFFFFFFL; 591 OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask); 592 593 OUTREG(RADEON_DAC_CNTL, ulOrigDAC_CNTL ); 594 OUTREG(RADEON_DAC_EXT_CNTL, ulOrigDAC_EXT_CNTL ); 595 OUTREG(RADEON_CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL); 596 597 if (!bConnected) { 598 /* Power DAC down if CRT is not connected */ 599 ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL); 600 ulOrigDAC_MACRO_CNTL |= (RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | 601 RADEON_DAC_PDWN_B); 602 OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL); 603 604 ulData = INREG(RADEON_DAC_CNTL); 605 ulData |= RADEON_DAC_PDWN; 606 OUTREG(RADEON_DAC_CNTL, ulData); 607 } 608 } else { /* TV DAC */ 609 610 /* This doesn't seem to work reliably (maybe worse on some OEM cards), 611 for now we always return false. If one wants to connected a 612 non-DDC monitor on the DVI port when CRT port is also connected, 613 he will need to explicitly tell the driver in the config file 614 with Option MonitorLayout. 615 */ 616 bConnected = FALSE; 617 618 #if 0 619 if (info->ChipFamily == CHIP_FAMILY_R200) { 620 unsigned long ulOrigGPIO_MONID; 621 unsigned long ulOrigFP2_GEN_CNTL; 622 unsigned long ulOrigDISP_OUTPUT_CNTL; 623 unsigned long ulOrigCRTC2_GEN_CNTL; 624 unsigned long ulOrigDISP_LIN_TRANS_GRPH_A; 625 unsigned long ulOrigDISP_LIN_TRANS_GRPH_B; 626 unsigned long ulOrigDISP_LIN_TRANS_GRPH_C; 627 unsigned long ulOrigDISP_LIN_TRANS_GRPH_D; 628 unsigned long ulOrigDISP_LIN_TRANS_GRPH_E; 629 unsigned long ulOrigDISP_LIN_TRANS_GRPH_F; 630 unsigned long ulOrigCRTC2_H_TOTAL_DISP; 631 unsigned long ulOrigCRTC2_V_TOTAL_DISP; 632 unsigned long ulOrigCRTC2_H_SYNC_STRT_WID; 633 unsigned long ulOrigCRTC2_V_SYNC_STRT_WID; 634 unsigned long ulData, i; 635 636 ulOrigGPIO_MONID = INREG(RADEON_GPIO_MONID); 637 ulOrigFP2_GEN_CNTL = INREG(RADEON_FP2_GEN_CNTL); 638 ulOrigDISP_OUTPUT_CNTL = INREG(RADEON_DISP_OUTPUT_CNTL); 639 ulOrigCRTC2_GEN_CNTL = INREG(RADEON_CRTC2_GEN_CNTL); 640 ulOrigDISP_LIN_TRANS_GRPH_A = INREG(RADEON_DISP_LIN_TRANS_GRPH_A); 641 ulOrigDISP_LIN_TRANS_GRPH_B = INREG(RADEON_DISP_LIN_TRANS_GRPH_B); 642 ulOrigDISP_LIN_TRANS_GRPH_C = INREG(RADEON_DISP_LIN_TRANS_GRPH_C); 643 ulOrigDISP_LIN_TRANS_GRPH_D = INREG(RADEON_DISP_LIN_TRANS_GRPH_D); 644 ulOrigDISP_LIN_TRANS_GRPH_E = INREG(RADEON_DISP_LIN_TRANS_GRPH_E); 645 ulOrigDISP_LIN_TRANS_GRPH_F = INREG(RADEON_DISP_LIN_TRANS_GRPH_F); 646 647 ulOrigCRTC2_H_TOTAL_DISP = INREG(RADEON_CRTC2_H_TOTAL_DISP); 648 ulOrigCRTC2_V_TOTAL_DISP = INREG(RADEON_CRTC2_V_TOTAL_DISP); 649 ulOrigCRTC2_H_SYNC_STRT_WID = INREG(RADEON_CRTC2_H_SYNC_STRT_WID); 650 ulOrigCRTC2_V_SYNC_STRT_WID = INREG(RADEON_CRTC2_V_SYNC_STRT_WID); 651 652 ulData = INREG(RADEON_GPIO_MONID); 653 ulData &= ~RADEON_GPIO_A_0; 654 OUTREG(RADEON_GPIO_MONID, ulData); 655 656 OUTREG(RADEON_FP2_GEN_CNTL, 0x0a000c0c); 657 658 OUTREG(RADEON_DISP_OUTPUT_CNTL, 0x00000012); 659 660 OUTREG(RADEON_CRTC2_GEN_CNTL, 0x06000000); 661 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); 662 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); 663 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); 664 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); 665 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); 666 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); 667 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); 668 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); 669 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); 670 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); 671 672 for (i = 0; i < 200; i++) { 673 ulData = INREG(RADEON_GPIO_MONID); 674 bConnected = (ulData & RADEON_GPIO_Y_0)?1:0; 675 if (!bConnected) break; 676 677 usleep(1000); 678 } 679 680 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, ulOrigDISP_LIN_TRANS_GRPH_A); 681 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, ulOrigDISP_LIN_TRANS_GRPH_B); 682 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, ulOrigDISP_LIN_TRANS_GRPH_C); 683 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, ulOrigDISP_LIN_TRANS_GRPH_D); 684 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, ulOrigDISP_LIN_TRANS_GRPH_E); 685 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, ulOrigDISP_LIN_TRANS_GRPH_F); 686 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, ulOrigCRTC2_H_TOTAL_DISP); 687 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, ulOrigCRTC2_V_TOTAL_DISP); 688 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, ulOrigCRTC2_H_SYNC_STRT_WID); 689 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, ulOrigCRTC2_V_SYNC_STRT_WID); 690 OUTREG(RADEON_CRTC2_GEN_CNTL, ulOrigCRTC2_GEN_CNTL); 691 OUTREG(RADEON_DISP_OUTPUT_CNTL, ulOrigDISP_OUTPUT_CNTL); 692 OUTREG(RADEON_FP2_GEN_CNTL, ulOrigFP2_GEN_CNTL); 693 OUTREG(RADEON_GPIO_MONID, ulOrigGPIO_MONID); 694 } else { 695 unsigned long ulOrigPIXCLKSDATA; 696 unsigned long ulOrigTV_MASTER_CNTL; 697 unsigned long ulOrigTV_DAC_CNTL; 698 unsigned long ulOrigTV_PRE_DAC_MUX_CNTL; 699 unsigned long ulOrigDAC_CNTL2; 700 unsigned long ulData; 701 unsigned long ulMask; 702 703 ulOrigPIXCLKSDATA = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 704 705 ulData = ulOrigPIXCLKSDATA; 706 ulData &= ~(RADEON_PIX2CLK_ALWAYS_ONb 707 | RADEON_PIX2CLK_DAC_ALWAYS_ONb); 708 ulMask = ~(RADEON_PIX2CLK_ALWAYS_ONb 709 | RADEON_PIX2CLK_DAC_ALWAYS_ONb); 710 OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask); 711 712 ulOrigTV_MASTER_CNTL = INREG(RADEON_TV_MASTER_CNTL); 713 ulData = ulOrigTV_MASTER_CNTL; 714 ulData &= ~RADEON_TVCLK_ALWAYS_ONb; 715 OUTREG(RADEON_TV_MASTER_CNTL, ulData); 716 717 ulOrigDAC_CNTL2 = INREG(RADEON_DAC_CNTL2); 718 ulData = ulOrigDAC_CNTL2; 719 ulData &= ~RADEON_DAC2_DAC2_CLK_SEL; 720 OUTREG(RADEON_DAC_CNTL2, ulData); 721 722 ulOrigTV_DAC_CNTL = INREG(RADEON_TV_DAC_CNTL); 723 724 ulData = 0x00880213; 725 OUTREG(RADEON_TV_DAC_CNTL, ulData); 726 727 ulOrigTV_PRE_DAC_MUX_CNTL = INREG(RADEON_TV_PRE_DAC_MUX_CNTL); 728 729 ulData = (RADEON_Y_RED_EN 730 | RADEON_C_GRN_EN 731 | RADEON_CMP_BLU_EN 732 | RADEON_RED_MX_FORCE_DAC_DATA 733 | RADEON_GRN_MX_FORCE_DAC_DATA 734 | RADEON_BLU_MX_FORCE_DAC_DATA); 735 if (IS_R300_VARIANT) 736 ulData |= 0x180 << RADEON_TV_FORCE_DAC_DATA_SHIFT; 737 else 738 ulData |= 0x1f5 << RADEON_TV_FORCE_DAC_DATA_SHIFT; 739 OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, ulData); 740 741 usleep(10000); 742 743 ulData = INREG(RADEON_TV_DAC_CNTL); 744 bConnected = (ulData & RADEON_TV_DAC_CMPOUT)?1:0; 745 746 ulData = ulOrigPIXCLKSDATA; 747 ulMask = 0xFFFFFFFFL; 748 OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask); 749 750 OUTREG(RADEON_TV_MASTER_CNTL, ulOrigTV_MASTER_CNTL); 751 OUTREG(RADEON_DAC_CNTL2, ulOrigDAC_CNTL2); 752 OUTREG(RADEON_TV_DAC_CNTL, ulOrigTV_DAC_CNTL); 753 OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, ulOrigTV_PRE_DAC_MUX_CNTL); 754 } 755 #endif 756 return MT_UNKNOWN; 757 } 758 759 return(bConnected ? MT_CRT : MT_NONE); 760 } 761 #endif 762 763 RADEONMonitorType 764 legacy_dac_detect(xf86OutputPtr output) 765 { 766 ScrnInfoPtr pScrn = output->scrn; 767 RADEONInfoPtr info = RADEONPTR(pScrn); 768 RADEONOutputPrivatePtr radeon_output = output->driver_private; 769 RADEONMonitorType found = MT_NONE; 770 771 if (radeon_output->devices & (ATOM_DEVICE_TV_SUPPORT)) { 772 if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { 773 if (radeon_output->ConnectorType == CONNECTOR_STV) 774 found = MT_STV; 775 else 776 found = MT_CTV; 777 } else { 778 if (radeon_output->load_detection) 779 found = radeon_detect_tv(pScrn); 780 } 781 } else if (radeon_output->devices & (ATOM_DEVICE_CRT2_SUPPORT)) { 782 if (info->encoders[ATOM_DEVICE_CRT2_INDEX] && 783 (info->encoders[ATOM_DEVICE_CRT2_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)) { 784 if (radeon_output->load_detection) 785 found = radeon_detect_primary_dac(pScrn, TRUE); 786 } else { 787 if (radeon_output->load_detection) { 788 if (info->ChipFamily == CHIP_FAMILY_R200) 789 found = radeon_detect_ext_dac(pScrn); 790 else 791 found = radeon_detect_tv_dac(pScrn, TRUE); 792 } 793 } 794 } else if (radeon_output->devices & (ATOM_DEVICE_CRT1_SUPPORT)) { 795 if (info->encoders[ATOM_DEVICE_CRT1_INDEX] && 796 (info->encoders[ATOM_DEVICE_CRT1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)) { 797 if (radeon_output->load_detection) 798 found = radeon_detect_primary_dac(pScrn, TRUE); 799 } else { 800 if (radeon_output->load_detection) { 801 if (info->ChipFamily == CHIP_FAMILY_R200) 802 found = radeon_detect_ext_dac(pScrn); 803 else 804 found = radeon_detect_tv_dac(pScrn, TRUE); 805 } 806 } 807 } 808 809 return found; 810 } 811 812 /* 813 * Powering done DAC, needed for DPMS problem with ViewSonic P817 (or its variant). 814 * 815 */ 816 static void 817 RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) 818 { 819 RADEONInfoPtr info = RADEONPTR(pScrn); 820 unsigned char *RADEONMMIO = info->MMIO; 821 822 if (IsPrimaryDAC) { 823 uint32_t dac_cntl; 824 uint32_t dac_macro_cntl = 0; 825 dac_cntl = INREG(RADEON_DAC_CNTL); 826 dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); 827 if (IsOn) { 828 dac_cntl &= ~RADEON_DAC_PDWN; 829 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | 830 RADEON_DAC_PDWN_G | 831 RADEON_DAC_PDWN_B); 832 } else { 833 dac_cntl |= RADEON_DAC_PDWN; 834 dac_macro_cntl |= (RADEON_DAC_PDWN_R | 835 RADEON_DAC_PDWN_G | 836 RADEON_DAC_PDWN_B); 837 } 838 OUTREG(RADEON_DAC_CNTL, dac_cntl); 839 OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 840 } else { 841 uint32_t tv_dac_cntl; 842 uint32_t fp2_gen_cntl; 843 844 switch(info->ChipFamily) { 845 case CHIP_FAMILY_R420: 846 case CHIP_FAMILY_RV410: 847 tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); 848 if (IsOn) { 849 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | 850 R420_TV_DAC_GDACPD | 851 R420_TV_DAC_BDACPD | 852 RADEON_TV_DAC_BGSLEEP); 853 } else { 854 tv_dac_cntl |= (R420_TV_DAC_RDACPD | 855 R420_TV_DAC_GDACPD | 856 R420_TV_DAC_BDACPD | 857 RADEON_TV_DAC_BGSLEEP); 858 } 859 OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); 860 break; 861 case CHIP_FAMILY_R200: 862 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); 863 if (IsOn) { 864 fp2_gen_cntl |= RADEON_FP2_DVO_EN; 865 } else { 866 fp2_gen_cntl &= ~RADEON_FP2_DVO_EN; 867 } 868 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 869 break; 870 default: 871 tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); 872 if (IsOn) { 873 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | 874 RADEON_TV_DAC_GDACPD | 875 RADEON_TV_DAC_BDACPD | 876 RADEON_TV_DAC_BGSLEEP); 877 } else { 878 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | 879 RADEON_TV_DAC_GDACPD | 880 RADEON_TV_DAC_BDACPD | 881 RADEON_TV_DAC_BGSLEEP); 882 } 883 OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); 884 break; 885 } 886 } 887 } 888 889 void 890 legacy_output_dpms(xf86OutputPtr output, int mode) 891 { 892 ScrnInfoPtr pScrn = output->scrn; 893 RADEONInfoPtr info = RADEONPTR(pScrn); 894 RADEONSavePtr save = info->ModeReg; 895 unsigned char * RADEONMMIO = info->MMIO; 896 unsigned long tmp; 897 RADEONOutputPrivatePtr radeon_output = output->driver_private; 898 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 899 900 if (radeon_encoder == NULL) 901 return; 902 903 switch(mode) { 904 case DPMSModeOn: 905 radeon_encoder->devices |= radeon_output->active_device; 906 switch (radeon_encoder->encoder_id) { 907 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 908 { 909 radeon_lvds_ptr lvds = (radeon_lvds_ptr)radeon_encoder->dev_priv; 910 if (lvds == NULL) 911 return; 912 ErrorF("enable LVDS\n"); 913 tmp = INREG(RADEON_LVDS_GEN_CNTL); 914 tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); 915 #if defined(__powerpc__) 916 /* not sure if this is needed on non-Macs */ 917 if (info->MacModel) 918 tmp |= RADEON_LVDS_BL_MOD_EN; 919 #endif 920 tmp &= ~(RADEON_LVDS_DISPLAY_DIS); 921 usleep (lvds->PanelPwrDly * 1000); 922 OUTREG(RADEON_LVDS_GEN_CNTL, tmp); 923 save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); 924 save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); 925 } 926 break; 927 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 928 ErrorF("enable FP1\n"); 929 tmp = INREG(RADEON_FP_GEN_CNTL); 930 tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); 931 OUTREG(RADEON_FP_GEN_CNTL, tmp); 932 save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); 933 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 934 (info->ChipFamily == CHIP_FAMILY_RS480)) { 935 tmp = INREG(RS400_FP_2ND_GEN_CNTL); 936 tmp |= (RS400_FP_2ND_ON | RS400_TMDS_2ND_EN); 937 OUTREG(RS400_FP_2ND_GEN_CNTL, tmp); 938 save->fp_2nd_gen_cntl |= (RS400_FP_2ND_ON | 939 RS400_TMDS_2ND_EN); 940 } 941 break; 942 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 943 ErrorF("enable FP2\n"); 944 tmp = INREG(RADEON_FP2_GEN_CNTL); 945 tmp &= ~RADEON_FP2_BLANK_EN; 946 tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 947 OUTREG(RADEON_FP2_GEN_CNTL, tmp); 948 save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 949 save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; 950 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 951 (info->ChipFamily == CHIP_FAMILY_RS480)) { 952 tmp = INREG(RS400_FP2_2_GEN_CNTL); 953 tmp &= ~RS400_FP2_2_BLANK_EN; 954 tmp |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); 955 OUTREG(RS400_FP2_2_GEN_CNTL, tmp); 956 save->fp2_2_gen_cntl |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); 957 save->fp2_2_gen_cntl &= ~RS400_FP2_2_BLANK_EN; 958 } 959 break; 960 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 961 ErrorF("enable primary dac\n"); 962 tmp = INREG(RADEON_CRTC_EXT_CNTL); 963 tmp |= RADEON_CRTC_CRT_ON; 964 OUTREG(RADEON_CRTC_EXT_CNTL, tmp); 965 save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; 966 RADEONDacPowerSet(pScrn, TRUE, TRUE); 967 break; 968 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 969 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 970 ErrorF("enable TV\n"); 971 tmp = INREG(RADEON_TV_MASTER_CNTL); 972 tmp |= RADEON_TV_ON; 973 OUTREG(RADEON_TV_MASTER_CNTL, tmp); 974 radeon_output->tvout.tv_on = TRUE; 975 } else { 976 ErrorF("enable TVDAC\n"); 977 if (info->ChipFamily == CHIP_FAMILY_R200) { 978 tmp = INREG(RADEON_FP2_GEN_CNTL); 979 tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 980 OUTREG(RADEON_FP2_GEN_CNTL, tmp); 981 save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 982 } else { 983 tmp = INREG(RADEON_CRTC2_GEN_CNTL); 984 tmp |= RADEON_CRTC2_CRT2_ON; 985 OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); 986 save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; 987 } 988 } 989 RADEONDacPowerSet(pScrn, TRUE, FALSE); 990 break; 991 } 992 break; 993 case DPMSModeOff: 994 case DPMSModeSuspend: 995 case DPMSModeStandby: 996 radeon_encoder->devices &= ~(radeon_output->active_device); 997 if (!radeon_encoder->devices) { 998 switch (radeon_encoder->encoder_id) { 999 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1000 { 1001 unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 1002 radeon_lvds_ptr lvds = (radeon_lvds_ptr)radeon_encoder->dev_priv; 1003 if (lvds == NULL) 1004 return; 1005 if (info->IsMobility || info->IsIGP) { 1006 /* Asic bug, when turning off LVDS_ON, we have to make sure 1007 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off 1008 */ 1009 OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 1010 } 1011 #if defined(__powerpc__) 1012 /* not sure if this is needed on non-Macs */ 1013 if (info->MacModel) { 1014 tmp = INREG(RADEON_LVDS_GEN_CNTL); 1015 tmp |= RADEON_LVDS_DISPLAY_DIS; 1016 tmp &= ~RADEON_LVDS_BL_MOD_EN; 1017 OUTREG(RADEON_LVDS_GEN_CNTL, tmp); 1018 usleep(100); 1019 tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); 1020 OUTREG(RADEON_LVDS_GEN_CNTL, tmp); 1021 } else 1022 #endif 1023 { 1024 tmp = INREG(RADEON_LVDS_GEN_CNTL); 1025 tmp |= RADEON_LVDS_DISPLAY_DIS; 1026 tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); 1027 OUTREG(RADEON_LVDS_GEN_CNTL, tmp); 1028 } 1029 save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 1030 save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); 1031 if (info->IsMobility || info->IsIGP) { 1032 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); 1033 } 1034 usleep (lvds->PanelPwrDly * 1000); 1035 } 1036 break; 1037 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1038 ErrorF("disable FP1\n"); 1039 tmp = INREG(RADEON_FP_GEN_CNTL); 1040 tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 1041 OUTREG(RADEON_FP_GEN_CNTL, tmp); 1042 save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 1043 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1044 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1045 tmp = INREG(RS400_FP_2ND_GEN_CNTL); 1046 tmp &= ~(RS400_FP_2ND_ON | RS400_TMDS_2ND_EN); 1047 OUTREG(RS400_FP_2ND_GEN_CNTL, tmp); 1048 save->fp_2nd_gen_cntl &= ~(RS400_FP_2ND_ON | 1049 RS400_TMDS_2ND_EN); 1050 } 1051 break; 1052 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1053 ErrorF("disable FP2\n"); 1054 tmp = INREG(RADEON_FP2_GEN_CNTL); 1055 tmp |= RADEON_FP2_BLANK_EN; 1056 tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1057 OUTREG(RADEON_FP2_GEN_CNTL, tmp); 1058 save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1059 save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; 1060 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1061 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1062 tmp = INREG(RS400_FP2_2_GEN_CNTL); 1063 tmp |= RS400_FP2_2_BLANK_EN; 1064 tmp &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); 1065 OUTREG(RS400_FP2_2_GEN_CNTL, tmp); 1066 save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); 1067 save->fp2_2_gen_cntl |= RS400_FP2_2_BLANK_EN; 1068 } 1069 break; 1070 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1071 ErrorF("disable primary dac\n"); 1072 tmp = INREG(RADEON_CRTC_EXT_CNTL); 1073 tmp &= ~RADEON_CRTC_CRT_ON; 1074 OUTREG(RADEON_CRTC_EXT_CNTL, tmp); 1075 save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; 1076 RADEONDacPowerSet(pScrn, FALSE, TRUE); 1077 break; 1078 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1079 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 1080 ErrorF("disable TV\n"); 1081 tmp = INREG(RADEON_TV_MASTER_CNTL); 1082 tmp &= ~RADEON_TV_ON; 1083 OUTREG(RADEON_TV_MASTER_CNTL, tmp); 1084 radeon_output->tvout.tv_on = FALSE; 1085 } else { 1086 ErrorF("disable TVDAC\n"); 1087 if (info->ChipFamily == CHIP_FAMILY_R200) { 1088 tmp = INREG(RADEON_FP2_GEN_CNTL); 1089 tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1090 OUTREG(RADEON_FP2_GEN_CNTL, tmp); 1091 save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1092 } else { 1093 tmp = INREG(RADEON_CRTC2_GEN_CNTL); 1094 tmp &= ~RADEON_CRTC2_CRT2_ON; 1095 OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); 1096 save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; 1097 } 1098 } 1099 RADEONDacPowerSet(pScrn, FALSE, FALSE); 1100 break; 1101 } 1102 } 1103 break; 1104 } 1105 } 1106 1107 static void 1108 RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, 1109 DisplayModePtr mode, BOOL IsPrimary) 1110 { 1111 ScrnInfoPtr pScrn = output->scrn; 1112 RADEONInfoPtr info = RADEONPTR(pScrn); 1113 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1114 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1115 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1116 radeon_tmds_ptr tmds = NULL; 1117 int i; 1118 uint32_t tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; 1119 1120 if (radeon_encoder == NULL) 1121 return; 1122 1123 tmds = (radeon_tmds_ptr)radeon_encoder->dev_priv; 1124 1125 if (tmds == NULL) 1126 return; 1127 1128 for (i = 0; i < 4; i++) { 1129 if (tmds->tmds_pll[i].freq == 0) 1130 break; 1131 if ((uint32_t)(mode->Clock / 10) < tmds->tmds_pll[i].freq) { 1132 tmp = tmds->tmds_pll[i].value ; 1133 break; 1134 } 1135 } 1136 1137 if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RV280)) { 1138 if (tmp & 0xfff00000) 1139 save->tmds_pll_cntl = tmp; 1140 else { 1141 save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000; 1142 save->tmds_pll_cntl |= tmp; 1143 } 1144 } else save->tmds_pll_cntl = tmp; 1145 1146 save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl & 1147 ~(RADEON_TMDS_TRANSMITTER_PLLRST); 1148 1149 if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !pRADEONEnt->HasCRTC2) 1150 save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); 1151 else /* weird, RV chips got this bit reversed? */ 1152 save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN); 1153 1154 save->fp_gen_cntl = info->SavedReg->fp_gen_cntl | 1155 (RADEON_FP_CRTC_DONT_SHADOW_VPAR | 1156 RADEON_FP_CRTC_DONT_SHADOW_HEND ); 1157 1158 save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 1159 1160 save->fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | 1161 RADEON_FP_DFP_SYNC_SEL | 1162 RADEON_FP_CRT_SYNC_SEL | 1163 RADEON_FP_CRTC_LOCK_8DOT | 1164 RADEON_FP_USE_SHADOW_EN | 1165 RADEON_FP_CRTC_USE_SHADOW_VEND | 1166 RADEON_FP_CRT_SYNC_ALT); 1167 1168 if (pScrn->rgbBits == 8) 1169 save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ 1170 else 1171 save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ 1172 1173 if (IsPrimary) { 1174 if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) { 1175 save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 1176 if (radeon_output->Flags & RADEON_USE_RMX) 1177 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; 1178 else 1179 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 1180 } else 1181 save->fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; 1182 } else { 1183 if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) { 1184 save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 1185 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; 1186 } else 1187 save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2; 1188 } 1189 1190 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1191 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1192 save->tmds2_transmitter_cntl = info->SavedReg->tmds2_transmitter_cntl & 1193 ~(RS400_TMDS2_PLLRST); 1194 save->tmds2_transmitter_cntl &= ~(RS400_TMDS2_PLLEN); 1195 1196 save->fp_2nd_gen_cntl = info->SavedReg->fp_2nd_gen_cntl; 1197 1198 if (pScrn->rgbBits == 8) 1199 save->fp_2nd_gen_cntl |= RS400_PANEL_FORMAT_2ND; /* 24 bit format */ 1200 else 1201 save->fp_2nd_gen_cntl &= ~RS400_PANEL_FORMAT_2ND;/* 18 bit format */ 1202 1203 save->fp_2nd_gen_cntl &= ~RS400_FP_2ND_SOURCE_SEL_MASK; 1204 1205 if (IsPrimary) { 1206 if (radeon_output->Flags & RADEON_USE_RMX) 1207 save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_RMX; 1208 else 1209 save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC1; 1210 } else 1211 save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC2; 1212 } 1213 1214 } 1215 1216 static void 1217 RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, 1218 DisplayModePtr mode, BOOL IsPrimary) 1219 { 1220 ScrnInfoPtr pScrn = output->scrn; 1221 RADEONInfoPtr info = RADEONPTR(pScrn); 1222 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1223 1224 if (pScrn->rgbBits == 8) 1225 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl | 1226 RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ 1227 else 1228 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & 1229 ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ 1230 1231 save->fp2_gen_cntl &= ~(RADEON_FP2_ON | 1232 RADEON_FP2_DVO_EN | 1233 RADEON_FP2_DVO_RATE_SEL_SDR); 1234 1235 1236 /* XXX: these are oem specific */ 1237 if (IS_R300_VARIANT) { 1238 if ((info->Chipset == PCI_CHIP_RV350_NP) && 1239 (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1028) && 1240 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x2001)) 1241 save->fp2_gen_cntl |= R200_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */ 1242 else 1243 save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R200_FP2_DVO_CLOCK_MODE_SINGLE; 1244 } 1245 1246 #if 0 1247 /* DVO configurations: 1248 * SDR single channel (data rate 165 Mhz, port width 12 bits) 1249 * DDR single channel (data rate 330 Mhz, port width 12 bits) 1250 * SDR dual channel (data rate 330 Mhz, port width 24 bits) 1251 * - dual channel is only available on r3xx+ 1252 */ 1253 if (info->ChipFamily >= CHIP_FAMILY_R200) { 1254 if (sdr) 1255 save->fp2_gen_cntl |= R200_FP2_DVO_RATE_SEL_SDR; 1256 if (IS_R300_VARIANT && dual channel) 1257 save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN; 1258 } 1259 #endif 1260 1261 if (IsPrimary) { 1262 if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { 1263 save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 1264 if (radeon_output->Flags & RADEON_USE_RMX) 1265 save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; 1266 else 1267 save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; 1268 } else 1269 save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; 1270 } else { 1271 if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { 1272 save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 1273 save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1274 } else 1275 save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; 1276 } 1277 1278 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1279 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1280 if (pScrn->rgbBits == 8) 1281 save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl | 1282 RS400_FP2_2_PANEL_FORMAT; /* 24 bit format, */ 1283 else 1284 save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl & 1285 ~RS400_FP2_2_PANEL_FORMAT;/* 18 bit format, */ 1286 1287 save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | 1288 RS400_FP2_2_DVO2_EN | 1289 RS400_FP2_2_SOURCE_SEL_MASK); 1290 1291 if (IsPrimary) { 1292 if (radeon_output->Flags & RADEON_USE_RMX) 1293 save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_RMX; 1294 else 1295 save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC1; 1296 } else 1297 save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC2; 1298 } 1299 1300 } 1301 1302 static void 1303 RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save, 1304 DisplayModePtr mode, BOOL IsPrimary) 1305 { 1306 ScrnInfoPtr pScrn = output->scrn; 1307 RADEONInfoPtr info = RADEONPTR(pScrn); 1308 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1309 1310 save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl | 1311 RADEON_LVDS_PLL_EN); 1312 1313 save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; 1314 1315 save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl; 1316 save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 1317 save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | 1318 RADEON_LVDS_BLON | 1319 RADEON_LVDS_EN | 1320 RADEON_LVDS_RST_FM); 1321 1322 if (IS_R300_VARIANT) 1323 save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); 1324 1325 if (IsPrimary) { 1326 if (IS_R300_VARIANT) { 1327 if (radeon_output->Flags & RADEON_USE_RMX) 1328 save->lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; 1329 } else 1330 save->lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; 1331 } else { 1332 if (IS_R300_VARIANT) { 1333 save->lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; 1334 } else 1335 save->lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; 1336 } 1337 1338 } 1339 1340 static void 1341 RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, 1342 DisplayModePtr mode) 1343 { 1344 ScrnInfoPtr pScrn = output->scrn; 1345 RADEONInfoPtr info = RADEONPTR(pScrn); 1346 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1347 radeon_native_mode_ptr native_mode = &radeon_output->native_mode; 1348 int xres = mode->HDisplay; 1349 int yres = mode->VDisplay; 1350 Bool Hscale = TRUE, Vscale = TRUE; 1351 int hsync_wid; 1352 int vsync_wid; 1353 int hsync_start; 1354 1355 1356 save->fp_vert_stretch = info->SavedReg->fp_vert_stretch & 1357 (RADEON_VERT_STRETCH_RESERVED | 1358 RADEON_VERT_AUTO_RATIO_INC); 1359 save->fp_horz_stretch = info->SavedReg->fp_horz_stretch & 1360 (RADEON_HORZ_FP_LOOP_STRETCH | 1361 RADEON_HORZ_AUTO_RATIO_INC); 1362 1363 save->crtc_more_cntl = 0; 1364 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 1365 (info->ChipFamily == CHIP_FAMILY_RS200)) { 1366 /* This is to workaround the asic bug for RMX, some versions 1367 of BIOS dosen't have this register initialized correctly. 1368 */ 1369 save->crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 1370 } 1371 1372 1373 save->fp_crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) 1374 | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) 1375 << 16)); 1376 1377 hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; 1378 if (!hsync_wid) hsync_wid = 1; 1379 hsync_start = mode->CrtcHSyncStart - 8; 1380 1381 save->fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 1382 | ((hsync_wid & 0x3f) << 16) 1383 | ((mode->Flags & V_NHSYNC) 1384 ? RADEON_CRTC_H_SYNC_POL 1385 : 0)); 1386 1387 save->fp_crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) 1388 | ((mode->CrtcVDisplay - 1) << 16)); 1389 1390 vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; 1391 if (!vsync_wid) vsync_wid = 1; 1392 1393 save->fp_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) 1394 | ((vsync_wid & 0x1f) << 16) 1395 | ((mode->Flags & V_NVSYNC) 1396 ? RADEON_CRTC_V_SYNC_POL 1397 : 0)); 1398 1399 save->fp_horz_vert_active = 0; 1400 1401 if ((radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) || 1402 (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT))) { 1403 1404 if (native_mode->PanelXRes == 0 || native_mode->PanelYRes == 0) { 1405 Hscale = FALSE; 1406 Vscale = FALSE; 1407 } else { 1408 if (xres > native_mode->PanelXRes) 1409 xres = native_mode->PanelXRes; 1410 if (yres > native_mode->PanelYRes) 1411 yres = native_mode->PanelYRes; 1412 1413 if (xres == native_mode->PanelXRes) 1414 Hscale = FALSE; 1415 if (yres == native_mode->PanelYRes) 1416 Vscale = FALSE; 1417 } 1418 1419 if ((!Hscale) || (!(radeon_output->Flags & RADEON_USE_RMX)) || 1420 (radeon_output->rmx_type == RMX_CENTER)) { 1421 save->fp_horz_stretch |= ((xres/8-1)<<16); 1422 } else { 1423 uint32_t scale, inc; 1424 inc = (save->fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 1425 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 1426 / native_mode->PanelXRes + 1; 1427 save->fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 1428 RADEON_HORZ_STRETCH_BLEND | 1429 RADEON_HORZ_STRETCH_ENABLE | 1430 ((native_mode->PanelXRes/8-1)<<16)); 1431 } 1432 1433 if ((!Vscale) || (!(radeon_output->Flags & RADEON_USE_RMX)) || 1434 (radeon_output->rmx_type == RMX_CENTER)) { 1435 save->fp_vert_stretch |= ((yres-1)<<12); 1436 } else { 1437 uint32_t scale, inc; 1438 inc = (save->fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 1439 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 1440 / native_mode->PanelYRes + 1; 1441 save->fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 1442 RADEON_VERT_STRETCH_ENABLE | 1443 RADEON_VERT_STRETCH_BLEND | 1444 ((native_mode->PanelYRes-1)<<12)); 1445 } 1446 1447 if ((radeon_output->rmx_type == RMX_CENTER) && 1448 (radeon_output->Flags & RADEON_USE_RMX)) { 1449 int blank_width; 1450 1451 save->crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 1452 RADEON_CRTC_AUTO_VERT_CENTER_EN); 1453 1454 blank_width = (mode->CrtcHBlankEnd - mode->CrtcHBlankStart) / 8; 1455 if (blank_width > 110) 1456 blank_width = 110; 1457 1458 save->fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 1459 | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) 1460 << 16)); 1461 1462 hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; 1463 if (!hsync_wid) 1464 hsync_wid = 1; 1465 1466 save->fp_h_sync_strt_wid = ((((mode->CrtcHSyncStart - mode->CrtcHBlankStart) / 8) & 0x1fff) 1467 | ((hsync_wid & 0x3f) << 16) 1468 | ((mode->Flags & V_NHSYNC) 1469 ? RADEON_CRTC_H_SYNC_POL 1470 : 0)); 1471 1472 save->fp_crtc_v_total_disp = (((mode->CrtcVBlankEnd - mode->CrtcVBlankStart) & 0xffff) 1473 | ((mode->CrtcVDisplay - 1) << 16)); 1474 1475 vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; 1476 if (!vsync_wid) 1477 vsync_wid = 1; 1478 1479 save->fp_v_sync_strt_wid = ((((mode->CrtcVSyncStart - mode->CrtcVBlankStart) & 0xfff) 1480 | ((vsync_wid & 0x1f) << 16) 1481 | ((mode->Flags & V_NVSYNC) 1482 ? RADEON_CRTC_V_SYNC_POL 1483 : 0))); 1484 1485 save->fp_horz_vert_active = (((native_mode->PanelYRes) & 0xfff) | 1486 (((native_mode->PanelXRes / 8) & 0x1ff) << 16)); 1487 1488 } 1489 } 1490 } 1491 1492 static void 1493 RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save, 1494 DisplayModePtr mode, BOOL IsPrimary) 1495 { 1496 ScrnInfoPtr pScrn = output->scrn; 1497 RADEONInfoPtr info = RADEONPTR(pScrn); 1498 1499 if (IsPrimary) { 1500 if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { 1501 save->disp_output_cntl = info->SavedReg->disp_output_cntl & 1502 ~RADEON_DISP_DAC_SOURCE_MASK; 1503 } else { 1504 save->dac2_cntl = info->SavedReg->dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL); 1505 } 1506 } else { 1507 if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { 1508 save->disp_output_cntl = info->SavedReg->disp_output_cntl & 1509 ~RADEON_DISP_DAC_SOURCE_MASK; 1510 save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; 1511 } else { 1512 save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC_CLK_SEL; 1513 } 1514 } 1515 save->dac_cntl = (RADEON_DAC_MASK_ALL 1516 | RADEON_DAC_VGA_ADR_EN 1517 | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN)); 1518 1519 save->dac_macro_cntl = info->SavedReg->dac_macro_cntl; 1520 } 1521 1522 static void 1523 RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save) 1524 { 1525 ScrnInfoPtr pScrn = output->scrn; 1526 RADEONInfoPtr info = RADEONPTR(pScrn); 1527 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1528 radeon_tvdac_ptr tvdac = NULL; 1529 1530 if (radeon_encoder == NULL) 1531 return; 1532 1533 tvdac = (radeon_tvdac_ptr)radeon_encoder->dev_priv; 1534 1535 if (tvdac == NULL) 1536 return; 1537 1538 if (info->ChipFamily == CHIP_FAMILY_R420 || 1539 info->ChipFamily == CHIP_FAMILY_RV410) { 1540 save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & 1541 ~(RADEON_TV_DAC_STD_MASK | 1542 RADEON_TV_DAC_BGADJ_MASK | 1543 R420_TV_DAC_DACADJ_MASK | 1544 R420_TV_DAC_RDACPD | 1545 R420_TV_DAC_GDACPD | 1546 R420_TV_DAC_BDACPD | 1547 R420_TV_DAC_TVENABLE); 1548 } else { 1549 save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & 1550 ~(RADEON_TV_DAC_STD_MASK | 1551 RADEON_TV_DAC_BGADJ_MASK | 1552 RADEON_TV_DAC_DACADJ_MASK | 1553 RADEON_TV_DAC_RDACPD | 1554 RADEON_TV_DAC_GDACPD | 1555 RADEON_TV_DAC_BDACPD); 1556 } 1557 1558 save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 1559 RADEON_TV_DAC_NHOLD | 1560 RADEON_TV_DAC_STD_PS2 | 1561 tvdac->ps2_tvdac_adj); 1562 1563 } 1564 1565 static void 1566 RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save, 1567 DisplayModePtr mode, BOOL IsPrimary) 1568 { 1569 ScrnInfoPtr pScrn = output->scrn; 1570 RADEONInfoPtr info = RADEONPTR(pScrn); 1571 1572 /*0x0028023;*/ 1573 RADEONInitTvDacCntl(output, save); 1574 1575 if (IS_R300_VARIANT) 1576 save->gpiopad_a = info->SavedReg->gpiopad_a | 1; 1577 1578 save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL; 1579 1580 if (IsPrimary) { 1581 if (IS_R300_VARIANT) { 1582 save->disp_output_cntl = info->SavedReg->disp_output_cntl & 1583 ~RADEON_DISP_TVDAC_SOURCE_MASK; 1584 save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; 1585 } else if (info->ChipFamily == CHIP_FAMILY_R200) { 1586 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & 1587 ~(R200_FP2_SOURCE_SEL_MASK | 1588 RADEON_FP2_DVO_RATE_SEL_SDR); 1589 } else { 1590 save->disp_hw_debug = info->SavedReg->disp_hw_debug | RADEON_CRT2_DISP1_SEL; 1591 } 1592 } else { 1593 if (IS_R300_VARIANT) { 1594 save->disp_output_cntl = info->SavedReg->disp_output_cntl & 1595 ~RADEON_DISP_TVDAC_SOURCE_MASK; 1596 save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1597 } else if (info->ChipFamily == CHIP_FAMILY_R200) { 1598 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & 1599 ~(R200_FP2_SOURCE_SEL_MASK | 1600 RADEON_FP2_DVO_RATE_SEL_SDR); 1601 save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1602 } else { 1603 save->disp_hw_debug = info->SavedReg->disp_hw_debug & 1604 ~RADEON_CRT2_DISP1_SEL; 1605 } 1606 } 1607 } 1608 1609 void 1610 legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, 1611 DisplayModePtr adjusted_mode) 1612 { 1613 ScrnInfoPtr pScrn = output->scrn; 1614 RADEONInfoPtr info = RADEONPTR(pScrn); 1615 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1616 xf86CrtcPtr crtc = output->crtc; 1617 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 1618 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1619 Bool is_primary = FALSE; 1620 1621 if (radeon_encoder == NULL) 1622 return; 1623 1624 radeon_output->pixel_clock = adjusted_mode->Clock; 1625 if (radeon_crtc->crtc_id == 0) { 1626 ErrorF("set RMX\n"); 1627 is_primary = TRUE; 1628 RADEONInitRMXRegisters(output, info->ModeReg, adjusted_mode); 1629 RADEONRestoreRMXRegisters(pScrn, info->ModeReg); 1630 } 1631 1632 switch (radeon_encoder->encoder_id) { 1633 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1634 ErrorF("set LVDS\n"); 1635 RADEONInitLVDSRegisters(output, info->ModeReg, adjusted_mode, is_primary); 1636 RADEONRestoreLVDSRegisters(pScrn, info->ModeReg); 1637 break; 1638 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1639 ErrorF("set FP1\n"); 1640 RADEONInitFPRegisters(output, info->ModeReg, adjusted_mode, is_primary); 1641 RADEONRestoreFPRegisters(pScrn, info->ModeReg); 1642 break; 1643 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1644 ErrorF("set FP2\n"); 1645 RADEONInitFP2Registers(output, info->ModeReg, adjusted_mode, is_primary); 1646 if (info->IsAtomBios) { 1647 unsigned char *RADEONMMIO = info->MMIO; 1648 uint32_t fp2_gen_cntl; 1649 1650 atombios_external_tmds_setup(output, ATOM_ENABLE); 1651 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL) & ~R200_FP2_SOURCE_SEL_MASK; 1652 if (radeon_crtc->crtc_id == 1) 1653 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1654 else { 1655 if (radeon_output->Flags & RADEON_USE_RMX) 1656 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; 1657 else 1658 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; 1659 } 1660 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1661 } else { 1662 RADEONRestoreFP2Registers(pScrn, info->ModeReg); 1663 RADEONRestoreDVOChip(pScrn, output); 1664 } 1665 break; 1666 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1667 ErrorF("set primary dac\n"); 1668 RADEONInitDACRegisters(output, info->ModeReg, adjusted_mode, is_primary); 1669 RADEONRestoreDACRegisters(pScrn, info->ModeReg); 1670 break; 1671 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1672 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 1673 ErrorF("set TV\n"); 1674 RADEONInitTVRegisters(output, info->ModeReg, adjusted_mode, is_primary); 1675 RADEONRestoreDACRegisters(pScrn, info->ModeReg); 1676 RADEONRestoreTVRegisters(pScrn, info->ModeReg); 1677 } else { 1678 ErrorF("set TVDAC\n"); 1679 RADEONInitDAC2Registers(output, info->ModeReg, adjusted_mode, is_primary); 1680 RADEONRestoreDACRegisters(pScrn, info->ModeReg); 1681 } 1682 break; 1683 } 1684 1685 } 1686 1687 /* the following functions are based on the load detection code 1688 * in the beos radeon driver by Thomas Kurschel and the existing 1689 * load detection code in this driver. 1690 */ 1691 static RADEONMonitorType 1692 radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color) 1693 { 1694 RADEONInfoPtr info = RADEONPTR(pScrn); 1695 unsigned char *RADEONMMIO = info->MMIO; 1696 uint32_t vclk_ecp_cntl, crtc_ext_cntl; 1697 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; 1698 RADEONMonitorType found = MT_NONE; 1699 1700 /* save the regs we need */ 1701 vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 1702 crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 1703 dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL); 1704 dac_cntl = INREG(RADEON_DAC_CNTL); 1705 dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); 1706 1707 tmp = vclk_ecp_cntl & 1708 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); 1709 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 1710 1711 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 1712 OUTREG(RADEON_CRTC_EXT_CNTL, tmp); 1713 1714 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | 1715 RADEON_DAC_FORCE_DATA_EN; 1716 1717 if (color) 1718 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 1719 else 1720 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 1721 1722 if (IS_R300_VARIANT) 1723 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 1724 else 1725 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 1726 1727 OUTREG(RADEON_DAC_EXT_CNTL, tmp); 1728 1729 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); 1730 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; 1731 OUTREG(RADEON_DAC_CNTL, tmp); 1732 1733 tmp &= ~(RADEON_DAC_PDWN_R | 1734 RADEON_DAC_PDWN_G | 1735 RADEON_DAC_PDWN_B); 1736 1737 OUTREG(RADEON_DAC_MACRO_CNTL, tmp); 1738 1739 usleep(2000); 1740 1741 if (INREG(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) { 1742 found = MT_CRT; 1743 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 1744 "Found %s CRT connected to primary DAC\n", 1745 color ? "color" : "bw"); 1746 } 1747 1748 /* restore the regs we used */ 1749 OUTREG(RADEON_DAC_CNTL, dac_cntl); 1750 OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 1751 OUTREG(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1752 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 1753 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); 1754 1755 return found; 1756 } 1757 1758 static RADEONMonitorType 1759 radeon_detect_ext_dac(ScrnInfoPtr pScrn) 1760 { 1761 RADEONInfoPtr info = RADEONPTR(pScrn); 1762 unsigned char *RADEONMMIO = info->MMIO; 1763 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; 1764 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; 1765 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; 1766 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; 1767 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; 1768 RADEONMonitorType found = MT_NONE; 1769 int connected = 0; 1770 int i = 0; 1771 1772 /* save the regs we need */ 1773 gpio_monid = INREG(RADEON_GPIO_MONID); 1774 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); 1775 disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL); 1776 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 1777 disp_lin_trans_grph_a = INREG(RADEON_DISP_LIN_TRANS_GRPH_A); 1778 disp_lin_trans_grph_b = INREG(RADEON_DISP_LIN_TRANS_GRPH_B); 1779 disp_lin_trans_grph_c = INREG(RADEON_DISP_LIN_TRANS_GRPH_C); 1780 disp_lin_trans_grph_d = INREG(RADEON_DISP_LIN_TRANS_GRPH_D); 1781 disp_lin_trans_grph_e = INREG(RADEON_DISP_LIN_TRANS_GRPH_E); 1782 disp_lin_trans_grph_f = INREG(RADEON_DISP_LIN_TRANS_GRPH_F); 1783 crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP); 1784 crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP); 1785 crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID); 1786 crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID); 1787 1788 tmp = INREG(RADEON_GPIO_MONID); 1789 tmp &= ~RADEON_GPIO_A_0; 1790 OUTREG(RADEON_GPIO_MONID, tmp); 1791 1792 OUTREG(RADEON_FP2_GEN_CNTL, 1793 RADEON_FP2_ON | 1794 RADEON_FP2_PANEL_FORMAT | 1795 R200_FP2_SOURCE_SEL_TRANS_UNIT | 1796 RADEON_FP2_DVO_EN | 1797 R200_FP2_DVO_RATE_SEL_SDR); 1798 1799 OUTREG(RADEON_DISP_OUTPUT_CNTL, 1800 RADEON_DISP_DAC_SOURCE_RMX | 1801 RADEON_DISP_TRANS_MATRIX_GRAPHICS); 1802 1803 OUTREG(RADEON_CRTC2_GEN_CNTL, 1804 RADEON_CRTC2_EN | 1805 RADEON_CRTC2_DISP_REQ_EN_B); 1806 1807 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); 1808 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); 1809 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); 1810 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); 1811 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); 1812 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); 1813 1814 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); 1815 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); 1816 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); 1817 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); 1818 1819 for (i = 0; i < 200; i++) { 1820 tmp = INREG(RADEON_GPIO_MONID); 1821 if (tmp & RADEON_GPIO_Y_0) 1822 connected = 1; 1823 else 1824 connected = 0; 1825 1826 if (!connected) 1827 break; 1828 1829 usleep(1000); 1830 } 1831 1832 if (connected) 1833 found = MT_CRT; 1834 1835 /* restore the regs we used */ 1836 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a); 1837 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b); 1838 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c); 1839 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d); 1840 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e); 1841 OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f); 1842 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp); 1843 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp); 1844 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid); 1845 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid); 1846 OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1847 OUTREG(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1848 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1849 OUTREG(RADEON_GPIO_MONID, gpio_monid); 1850 1851 return found; 1852 } 1853 1854 static RADEONMonitorType 1855 radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color) 1856 { 1857 RADEONInfoPtr info = RADEONPTR(pScrn); 1858 unsigned char *RADEONMMIO = info->MMIO; 1859 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1860 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; 1861 RADEONMonitorType found = MT_NONE; 1862 1863 /* save the regs we need */ 1864 pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 1865 gpiopad_a = IS_R300_VARIANT ? INREG(RADEON_GPIOPAD_A) : 0; 1866 disp_output_cntl = IS_R300_VARIANT ? INREG(RADEON_DISP_OUTPUT_CNTL) : 0; 1867 disp_hw_debug = !IS_R300_VARIANT ? INREG(RADEON_DISP_HW_DEBUG) : 0; 1868 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 1869 tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); 1870 dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL); 1871 dac_cntl2 = INREG(RADEON_DAC_CNTL2); 1872 1873 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb 1874 | RADEON_PIX2CLK_DAC_ALWAYS_ONb); 1875 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 1876 1877 if (IS_R300_VARIANT) { 1878 OUTREGP(RADEON_GPIOPAD_A, 1, ~1 ); 1879 } 1880 1881 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; 1882 tmp |= RADEON_CRTC2_CRT2_ON | 1883 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); 1884 1885 OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); 1886 1887 if (IS_R300_VARIANT) { 1888 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1889 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1890 OUTREG(RADEON_DISP_OUTPUT_CNTL, tmp); 1891 } else { 1892 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; 1893 OUTREG(RADEON_DISP_HW_DEBUG, tmp); 1894 } 1895 1896 tmp = RADEON_TV_DAC_NBLANK | 1897 RADEON_TV_DAC_NHOLD | 1898 RADEON_TV_MONITOR_DETECT_EN | 1899 RADEON_TV_DAC_STD_PS2; 1900 1901 OUTREG(RADEON_TV_DAC_CNTL, tmp); 1902 1903 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | 1904 RADEON_DAC2_FORCE_DATA_EN; 1905 1906 if (color) 1907 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 1908 else 1909 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 1910 1911 if (IS_R300_VARIANT) 1912 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 1913 else 1914 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 1915 1916 OUTREG(RADEON_DAC_EXT_CNTL, tmp); 1917 1918 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; 1919 OUTREG(RADEON_DAC_CNTL2, tmp); 1920 1921 usleep(10000); 1922 1923 if (IS_R300_VARIANT) { 1924 if (INREG(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) { 1925 found = MT_CRT; 1926 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 1927 "Found %s CRT connected to TV DAC\n", 1928 color ? "color" : "bw"); 1929 } 1930 } else { 1931 if (INREG(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) { 1932 found = MT_CRT; 1933 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 1934 "Found %s CRT connected to TV DAC\n", 1935 color ? "color" : "bw"); 1936 } 1937 } 1938 1939 /* restore regs we used */ 1940 OUTREG(RADEON_DAC_CNTL2, dac_cntl2); 1941 OUTREG(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1942 OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1943 OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1944 1945 if (IS_R300_VARIANT) { 1946 OUTREG(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1947 OUTREGP(RADEON_GPIOPAD_A, gpiopad_a, ~1 ); 1948 } else { 1949 OUTREG(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1950 } 1951 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, pixclks_cntl); 1952 1953 return found; 1954 } 1955 1956 static RADEONMonitorType 1957 r300_detect_tv(ScrnInfoPtr pScrn) 1958 { 1959 RADEONInfoPtr info = RADEONPTR(pScrn); 1960 unsigned char *RADEONMMIO = info->MMIO; 1961 uint32_t tmp, dac_cntl2, crtc2_gen_cntl, dac_ext_cntl, tv_dac_cntl; 1962 uint32_t gpiopad_a, disp_output_cntl; 1963 RADEONMonitorType found = MT_NONE; 1964 1965 /* save the regs we need */ 1966 gpiopad_a = INREG(RADEON_GPIOPAD_A); 1967 dac_cntl2 = INREG(RADEON_DAC_CNTL2); 1968 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 1969 dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL); 1970 tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); 1971 disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL); 1972 1973 OUTREGP(RADEON_GPIOPAD_A, 0, ~1 ); 1974 1975 OUTREG(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL ); 1976 1977 OUTREG(RADEON_CRTC2_GEN_CNTL, 1978 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT ); 1979 1980 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1981 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1982 OUTREG(RADEON_DISP_OUTPUT_CNTL, tmp); 1983 1984 OUTREG(RADEON_DAC_EXT_CNTL, 1985 RADEON_DAC2_FORCE_BLANK_OFF_EN | 1986 RADEON_DAC2_FORCE_DATA_EN | 1987 RADEON_DAC_FORCE_DATA_SEL_RGB | 1988 (0xec << RADEON_DAC_FORCE_DATA_SHIFT )); 1989 1990 OUTREG(RADEON_TV_DAC_CNTL, 1991 RADEON_TV_DAC_STD_NTSC | 1992 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1993 (6 << RADEON_TV_DAC_DACADJ_SHIFT )); 1994 1995 INREG(RADEON_TV_DAC_CNTL); 1996 1997 usleep(4000); 1998 1999 OUTREG(RADEON_TV_DAC_CNTL, 2000 RADEON_TV_DAC_NBLANK | 2001 RADEON_TV_DAC_NHOLD | 2002 RADEON_TV_MONITOR_DETECT_EN | 2003 RADEON_TV_DAC_STD_NTSC | 2004 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 2005 (6 << RADEON_TV_DAC_DACADJ_SHIFT )); 2006 2007 INREG(RADEON_TV_DAC_CNTL); 2008 2009 usleep(6000); 2010 2011 tmp = INREG(RADEON_TV_DAC_CNTL); 2012 if ( (tmp & RADEON_TV_DAC_GDACDET) != 0 ) { 2013 found = MT_STV; 2014 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 2015 "S-Video TV connection detected\n"); 2016 } else if ( (tmp & RADEON_TV_DAC_BDACDET) != 0 ) { 2017 found = MT_CTV; 2018 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 2019 "Composite TV connection detected\n" ); 2020 } 2021 2022 OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl ); 2023 OUTREG(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 2024 OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 2025 OUTREG(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 2026 OUTREG(RADEON_DAC_CNTL2, dac_cntl2); 2027 OUTREGP(RADEON_GPIOPAD_A, gpiopad_a, ~1); 2028 2029 return found; 2030 } 2031 2032 static RADEONMonitorType 2033 radeon_detect_tv(ScrnInfoPtr pScrn) 2034 { 2035 RADEONInfoPtr info = RADEONPTR(pScrn); 2036 unsigned char *RADEONMMIO = info->MMIO; 2037 uint32_t tmp, dac_cntl2, tv_master_cntl; 2038 uint32_t tv_dac_cntl, tv_pre_dac_mux_cntl, config_cntl; 2039 RADEONMonitorType found = MT_NONE; 2040 2041 if (IS_R300_VARIANT) 2042 return r300_detect_tv(pScrn); 2043 2044 /* save the regs we need */ 2045 dac_cntl2 = INREG(RADEON_DAC_CNTL2); 2046 tv_master_cntl = INREG(RADEON_TV_MASTER_CNTL); 2047 tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); 2048 config_cntl = INREG(RADEON_CONFIG_CNTL); 2049 tv_pre_dac_mux_cntl = INREG(RADEON_TV_PRE_DAC_MUX_CNTL); 2050 2051 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; 2052 OUTREG(RADEON_DAC_CNTL2, tmp); 2053 2054 tmp = tv_master_cntl | RADEON_TV_ON; 2055 tmp &= ~(RADEON_TV_ASYNC_RST | 2056 RADEON_RESTART_PHASE_FIX | 2057 RADEON_CRT_FIFO_CE_EN | 2058 RADEON_TV_FIFO_CE_EN | 2059 RADEON_RE_SYNC_NOW_SEL_MASK); 2060 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; 2061 2062 OUTREG(RADEON_TV_MASTER_CNTL, tmp); 2063 2064 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | 2065 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | 2066 (8 << RADEON_TV_DAC_BGADJ_SHIFT); 2067 2068 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) 2069 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); 2070 else 2071 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); 2072 2073 OUTREG(RADEON_TV_DAC_CNTL, tmp); 2074 2075 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | 2076 RADEON_RED_MX_FORCE_DAC_DATA | 2077 RADEON_GRN_MX_FORCE_DAC_DATA | 2078 RADEON_BLU_MX_FORCE_DAC_DATA | 2079 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); 2080 2081 OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); 2082 2083 usleep(3000); 2084 2085 tmp = INREG(RADEON_TV_DAC_CNTL); 2086 if (tmp & RADEON_TV_DAC_GDACDET) { 2087 found = MT_STV; 2088 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 2089 "S-Video TV connection detected\n"); 2090 } else if (tmp & RADEON_TV_DAC_BDACDET) { 2091 found = MT_CTV; 2092 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 2093 "Composite TV connection detected\n" ); 2094 } 2095 2096 OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); 2097 OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2098 OUTREG(RADEON_TV_MASTER_CNTL, tv_master_cntl); 2099 OUTREG(RADEON_DAC_CNTL2, dac_cntl2); 2100 2101 return found; 2102 } 2103
Indexes created Sun Jul 19 00:25:04 UTC 2026