1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29 #ifdef HAVE_CONFIG_H 30 #include "config.h" 31 #endif 32 33 /* 34 * Authors: 35 * Kevin E. Martin <martin (at) xfree86.org> 36 * Rickard E. Faith <faith (at) valinux.com> 37 * Alan Hourihane <alanh (at) fairlite.demon.co.uk> 38 * 39 * Credits: 40 * 41 * Thanks to Ani Joshi <ajoshi (at) shell.unixbox.com> for providing source 42 * code to his Radeon driver. Portions of this file are based on the 43 * initialization code for that driver. 44 * 45 * References: 46 * 47 * !!!! FIXME !!!! 48 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 49 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 50 * 1999. 51 * 52 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 53 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 54 * 55 * This server does not yet support these XFree86 4.0 features: 56 * !!!! FIXME !!!! 57 * DDC1 & DDC2 58 * shadowfb 59 * overlay planes 60 * 61 * Modified by Marc Aurele La France (tsi (at) xfree86.org) for ATI driver merge. 62 * 63 * Mergedfb and pseudo xinerama support added by Alex Deucher (agd5f (at) yahoo.com) 64 * based on the sis driver by Thomas Winischhofer. 65 * 66 */ 67 68 #include <string.h> 69 #include <stdio.h> 70 71 /* Driver data structures */ 72 #include "radeon.h" 73 #include "radeon_reg.h" 74 #include "radeon_macros.h" 75 #include "radeon_probe.h" 76 #include "radeon_version.h" 77 #include "radeon_atombios.h" 78 79 #ifdef XF86DRI 80 #define _XF86DRI_SERVER_ 81 #include "radeon_dri.h" 82 #include "radeon_drm.h" 83 #include "sarea.h" 84 #endif 85 86 #include "fb.h" 87 88 /* colormap initialization */ 89 #include "micmap.h" 90 #include "dixstruct.h" 91 92 /* X and server generic header files */ 93 #include "xf86.h" 94 #include "xf86_OSproc.h" 95 #include "xf86RandR12.h" 96 #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 6 97 #include "xf86RAC.h" 98 #include "xf86Resources.h" 99 #endif 100 #include "xf86cmap.h" 101 #include "vbe.h" 102 103 #include "shadow.h" 104 /* vgaHW definitions */ 105 #ifdef WITH_VGAHW 106 #include "vgaHW.h" 107 #endif 108 109 #ifdef HAVE_XEXTPROTO_71 110 #include <X11/extensions/dpmsconst.h> 111 #else 112 #define DPMS_SERVER 113 #include <X11/extensions/dpms.h> 114 #endif 115 116 117 #include "atipciids.h" 118 #include "radeon_chipset_gen.h" 119 120 121 #include "radeon_chipinfo_gen.h" 122 123 /* Forward definitions for driver functions */ 124 static Bool RADEONCloseScreen(CLOSE_SCREEN_ARGS_DECL); 125 static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode); 126 static void RADEONSave(ScrnInfoPtr pScrn); 127 128 static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 129 130 static void 131 RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 132 133 #ifdef XF86DRI 134 static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 135 #endif 136 137 static const OptionInfoRec RADEONOptions[] = { 138 { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE }, 139 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 140 { OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE }, 141 { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE }, 142 #ifdef XF86DRI 143 { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE }, 144 { OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE }, 145 { OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE }, 146 { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE }, 147 { OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE }, 148 { OPTION_GART_SIZE_OLD, "AGPSize", OPTV_INTEGER, {0}, FALSE }, 149 { OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE }, 150 { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE }, 151 { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE }, 152 { OPTION_DEPTH_MOVE, "EnableDepthMoves", OPTV_BOOLEAN, {0}, FALSE }, 153 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 154 { OPTION_NO_BACKBUFFER, "NoBackBuffer", OPTV_BOOLEAN, {0}, FALSE }, 155 { OPTION_XV_DMA, "DMAForXv", OPTV_BOOLEAN, {0}, FALSE }, 156 { OPTION_FBTEX_PERCENT, "FBTexPercent", OPTV_INTEGER, {0}, FALSE }, 157 { OPTION_DEPTH_BITS, "DepthBits", OPTV_INTEGER, {0}, FALSE }, 158 { OPTION_PCIAPER_SIZE, "PCIAPERSize", OPTV_INTEGER, {0}, FALSE }, 159 #ifdef USE_EXA 160 { OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE }, 161 #endif 162 #endif 163 { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE }, 164 { OPTION_CUSTOM_EDID, "CustomEDID", OPTV_ANYSTR, {0}, FALSE }, 165 { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, 166 { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, 167 { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, 168 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 169 #ifdef XvExtension 170 { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, 171 { OPTION_RAGE_THEATRE_CRYSTAL, "RageTheatreCrystal", OPTV_INTEGER, {0}, FALSE }, 172 { OPTION_RAGE_THEATRE_TUNER_PORT, "RageTheatreTunerPort", OPTV_INTEGER, {0}, FALSE }, 173 { OPTION_RAGE_THEATRE_COMPOSITE_PORT, "RageTheatreCompositePort", OPTV_INTEGER, {0}, FALSE }, 174 { OPTION_RAGE_THEATRE_SVIDEO_PORT, "RageTheatreSVideoPort", OPTV_INTEGER, {0}, FALSE }, 175 { OPTION_TUNER_TYPE, "TunerType", OPTV_INTEGER, {0}, FALSE }, 176 { OPTION_RAGE_THEATRE_MICROC_PATH, "RageTheatreMicrocPath", OPTV_STRING, {0}, FALSE }, 177 { OPTION_RAGE_THEATRE_MICROC_TYPE, "RageTheatreMicrocType", OPTV_STRING, {0}, FALSE }, 178 { OPTION_SCALER_WIDTH, "ScalerWidth", OPTV_INTEGER, {0}, FALSE }, 179 #endif 180 #ifdef RENDER 181 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, TRUE }, 182 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 183 #endif 184 { OPTION_CLOCK_GATING, "ClockGating", OPTV_BOOLEAN, {0}, FALSE }, 185 { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE }, 186 { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE }, 187 { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE }, 188 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 189 { OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, FALSE }, 190 { OPTION_CONNECTORTABLE, "ConnectorTable", OPTV_STRING, {0}, FALSE }, 191 { OPTION_DEFAULT_CONNECTOR_TABLE, "DefaultConnectorTable", OPTV_BOOLEAN, {0}, FALSE }, 192 { OPTION_DEFAULT_TMDS_PLL, "DefaultTMDSPLL", OPTV_BOOLEAN, {0}, FALSE }, 193 #if defined(__powerpc__) 194 { OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE }, 195 #endif 196 { OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE }, 197 { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, 198 { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, 199 { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, 200 { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, 201 { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, 202 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, 203 { OPTION_ATOM_TVOUT, "ATOMTVOut", OPTV_BOOLEAN, {0}, FALSE }, 204 { OPTION_R4XX_ATOM, "R4xxATOM", OPTV_BOOLEAN, {0}, FALSE }, 205 { OPTION_FORCE_LOW_POWER, "ForceLowPowerMode", OPTV_BOOLEAN, {0}, FALSE }, 206 { OPTION_DYNAMIC_PM, "DynamicPM", OPTV_BOOLEAN, {0}, FALSE }, 207 { OPTION_NEW_PLL, "NewPLL", OPTV_BOOLEAN, {0}, FALSE }, 208 { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, 209 { -1, NULL, OPTV_NONE, {0}, FALSE } 210 }; 211 212 const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; } 213 214 extern _X_EXPORT int gRADEONEntityIndex; 215 216 static int getRADEONEntityIndex(void) 217 { 218 return gRADEONEntityIndex; 219 } 220 221 struct RADEONInt10Save { 222 uint32_t MEM_CNTL; 223 uint32_t MEMSIZE; 224 uint32_t MPP_TB_CONFIG; 225 }; 226 227 static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); 228 static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); 229 230 static void 231 radeonUpdatePacked(ScreenPtr pScreen, shadowBufPtr pBuf) 232 { 233 shadowUpdatePacked(pScreen, pBuf); 234 } 235 236 static void * 237 radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 238 CARD32 *size, void *closure) 239 { 240 ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); 241 RADEONInfoPtr info = RADEONPTR(pScrn); 242 int stride; 243 244 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 245 *size = stride; 246 247 return ((uint8_t *)info->FB + pScrn->fbOffset + row * stride + offset); 248 } 249 static Bool 250 RADEONCreateScreenResources (ScreenPtr pScreen) 251 { 252 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 253 RADEONInfoPtr info = RADEONPTR(pScrn); 254 PixmapPtr pixmap; 255 256 pScreen->CreateScreenResources = info->CreateScreenResources; 257 if (!(*pScreen->CreateScreenResources)(pScreen)) 258 return FALSE; 259 pScreen->CreateScreenResources = RADEONCreateScreenResources; 260 261 if (info->r600_shadow_fb) { 262 pixmap = pScreen->GetScreenPixmap(pScreen); 263 264 if (!shadowAdd(pScreen, pixmap, radeonUpdatePacked, 265 radeonShadowWindow, 0, NULL)) 266 return FALSE; 267 } 268 return TRUE; 269 } 270 271 RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 272 { 273 DevUnion *pPriv; 274 RADEONInfoPtr info = RADEONPTR(pScrn); 275 pPriv = xf86GetEntityPrivate(info->pEnt->index, 276 getRADEONEntityIndex()); 277 return pPriv->ptr; 278 } 279 280 static void 281 RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) 282 { 283 RADEONInfoPtr info = RADEONPTR(pScrn); 284 unsigned char *RADEONMMIO = info->MMIO; 285 uint32_t CardTmp; 286 static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; 287 288 if (!IS_AVIVO_VARIANT) { 289 /* Save the values and zap MEM_CNTL */ 290 SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL); 291 SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE); 292 SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG); 293 294 /* 295 * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4 296 */ 297 OUTREG(RADEON_MEM_CNTL, 0); 298 CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu; 299 CardTmp |= 0x04 << 24; 300 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 301 } 302 303 *pPtr = (void *)&SaveStruct; 304 } 305 306 static void 307 RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) 308 { 309 RADEONInfoPtr info = RADEONPTR(pScrn); 310 unsigned char *RADEONMMIO = info->MMIO; 311 struct RADEONInt10Save *pSave = ptr; 312 uint32_t CardTmp; 313 314 /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */ 315 if (!pSave || !pSave->MEM_CNTL) 316 return; 317 318 if (IS_AVIVO_VARIANT) 319 return; 320 321 /* 322 * If either MEM_CNTL is currently zero or inconistent (configured for 323 * two channels with the two channels configured differently), restore 324 * the saved registers. 325 */ 326 CardTmp = INREG(RADEON_MEM_CNTL); 327 if (!CardTmp || 328 ((CardTmp & 1) && 329 (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) { 330 /* Restore the saved registers */ 331 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 332 "Restoring MEM_CNTL (%08lx), setting to %08lx\n", 333 (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL); 334 OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL); 335 336 CardTmp = INREG(RADEON_CONFIG_MEMSIZE); 337 if (CardTmp != pSave->MEMSIZE) { 338 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 339 "Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n", 340 (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE); 341 OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE); 342 } 343 } 344 345 CardTmp = INREG(RADEON_MPP_TB_CONFIG); 346 if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) { 347 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 348 "Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n", 349 (unsigned long)CardTmp >> 24, 350 (unsigned long)pSave->MPP_TB_CONFIG >> 24); 351 CardTmp &= 0x00ffffffu; 352 CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u); 353 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 354 } 355 } 356 357 /* Allocate our private RADEONInfoRec */ 358 Bool RADEONGetRec(ScrnInfoPtr pScrn) 359 { 360 if (pScrn->driverPrivate) return TRUE; 361 362 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 363 return TRUE; 364 } 365 366 /* Free our private RADEONInfoRec */ 367 void RADEONFreeRec(ScrnInfoPtr pScrn) 368 { 369 RADEONInfoPtr info; 370 int i; 371 372 if (!pScrn || !pScrn->driverPrivate) return; 373 374 info = RADEONPTR(pScrn); 375 376 if (info->cp) { 377 free(info->cp); 378 info->cp = NULL; 379 } 380 381 if (info->dri) { 382 free(info->dri); 383 info->dri = NULL; 384 } 385 386 if (info->accel_state) { 387 free(info->accel_state); 388 info->accel_state = NULL; 389 } 390 391 for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { 392 if (info->encoders[i]) { 393 if (info->encoders[i]->dev_priv) { 394 free(info->encoders[i]->dev_priv); 395 info->encoders[i]->dev_priv = NULL; 396 } 397 free(info->encoders[i]); 398 info->encoders[i]= NULL; 399 } 400 } 401 402 free(pScrn->driverPrivate); 403 pScrn->driverPrivate = NULL; 404 } 405 406 /* Memory map the MMIO region. Used during pre-init and by RADEONMapMem, 407 * below 408 */ 409 static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) 410 { 411 #ifdef XSERVER_LIBPCIACCESS 412 int err; 413 #endif 414 RADEONInfoPtr info = RADEONPTR(pScrn); 415 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 416 417 if (pRADEONEnt->MMIO) { 418 pRADEONEnt->MMIO_cnt++; 419 info->MMIO = pRADEONEnt->MMIO; 420 return TRUE; 421 } 422 423 #ifndef XSERVER_LIBPCIACCESS 424 425 info->MMIO = xf86MapPciMem(pScrn->scrnIndex, 426 VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, 427 info->PciTag, 428 info->MMIOAddr, 429 info->MMIOSize); 430 431 if (!info->MMIO) 432 return FALSE; 433 #else 434 435 err = pci_device_map_range(info->PciInfo, 436 info->MMIOAddr, 437 info->MMIOSize, 438 PCI_DEV_MAP_FLAG_WRITABLE, 439 &info->MMIO); 440 441 if (err) { 442 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 443 "Unable to map MMIO aperture. %s (%d)\n", 444 strerror (err), err); 445 return FALSE; 446 } 447 448 #endif 449 450 pRADEONEnt->MMIO = info->MMIO; 451 pRADEONEnt->MMIO_cnt = 1; 452 return TRUE; 453 } 454 455 /* Unmap the MMIO region. Used during pre-init and by RADEONUnmapMem, 456 * below 457 */ 458 static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) 459 { 460 RADEONInfoPtr info = RADEONPTR(pScrn); 461 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 462 463 /* refcount for zaphod */ 464 if (--pRADEONEnt->MMIO_cnt != 0) { 465 info->MMIO = NULL; 466 return TRUE; 467 } 468 469 #ifndef XSERVER_LIBPCIACCESS 470 xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); 471 #else 472 pci_device_unmap_range(info->PciInfo, info->MMIO, info->MMIOSize); 473 #endif 474 475 pRADEONEnt->MMIO = NULL; 476 info->MMIO = NULL; 477 return TRUE; 478 } 479 480 /* Memory map the frame buffer. Used by RADEONMapMem, below. */ 481 static Bool RADEONMapFB(ScrnInfoPtr pScrn) 482 { 483 #ifdef XSERVER_LIBPCIACCESS 484 int err; 485 #endif 486 RADEONInfoPtr info = RADEONPTR(pScrn); 487 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 488 489 if (pRADEONEnt->FB) { 490 pRADEONEnt->FB_cnt++; 491 info->FB = pRADEONEnt->FB; 492 return TRUE; 493 } 494 495 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 496 "Map: 0x%016llx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); 497 498 #ifndef XSERVER_LIBPCIACCESS 499 500 info->FB = xf86MapPciMem(pScrn->scrnIndex, 501 VIDMEM_FRAMEBUFFER, 502 info->PciTag, 503 info->LinearAddr, 504 info->FbMapSize); 505 506 if (!info->FB) return FALSE; 507 508 #else 509 510 err = pci_device_map_range(info->PciInfo, 511 info->LinearAddr, 512 info->FbMapSize, 513 PCI_DEV_MAP_FLAG_WRITABLE | 514 PCI_DEV_MAP_FLAG_WRITE_COMBINE, 515 &info->FB); 516 517 if (err) { 518 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 519 "Unable to map FB aperture. %s (%d)\n", 520 strerror (err), err); 521 return FALSE; 522 } 523 524 #endif 525 526 pRADEONEnt->FB = info->FB; 527 pRADEONEnt->FB_cnt = 1; 528 return TRUE; 529 } 530 531 /* Unmap the frame buffer. Used by RADEONUnmapMem, below. */ 532 static Bool RADEONUnmapFB(ScrnInfoPtr pScrn) 533 { 534 RADEONInfoPtr info = RADEONPTR(pScrn); 535 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 536 537 /* refcount for zaphod */ 538 if (--pRADEONEnt->FB_cnt != 0) { 539 info->FB = NULL; 540 return TRUE; 541 } 542 543 #ifndef XSERVER_LIBPCIACCESS 544 xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize); 545 #else 546 pci_device_unmap_range(info->PciInfo, info->FB, info->FbMapSize); 547 #endif 548 549 pRADEONEnt->FB = NULL; 550 info->FB = NULL; 551 return TRUE; 552 } 553 554 /* Memory map the MMIO region and the frame buffer */ 555 static Bool RADEONMapMem(ScrnInfoPtr pScrn) 556 { 557 if (!RADEONMapMMIO(pScrn)) return FALSE; 558 if (!RADEONMapFB(pScrn)) { 559 RADEONUnmapMMIO(pScrn); 560 return FALSE; 561 } 562 return TRUE; 563 } 564 565 /* Unmap the MMIO region and the frame buffer */ 566 static Bool RADEONUnmapMem(ScrnInfoPtr pScrn) 567 { 568 if (!RADEONUnmapMMIO(pScrn) || !RADEONUnmapFB(pScrn)) return FALSE; 569 return TRUE; 570 } 571 572 void RADEONPllErrataAfterIndex(RADEONInfoPtr info) 573 { 574 unsigned char *RADEONMMIO = info->MMIO; 575 576 if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) 577 return; 578 579 /* This workaround is necessary on rv200 and RS200 or PLL 580 * reads may return garbage (among others...) 581 */ 582 (void)INREG(RADEON_CLOCK_CNTL_DATA); 583 (void)INREG(RADEON_CRTC_GEN_CNTL); 584 } 585 586 void RADEONPllErrataAfterData(RADEONInfoPtr info) 587 { 588 unsigned char *RADEONMMIO = info->MMIO; 589 590 /* This workarounds is necessary on RV100, RS100 and RS200 chips 591 * or the chip could hang on a subsequent access 592 */ 593 if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) { 594 /* we can't deal with posted writes here ... */ 595 usleep(5000); 596 } 597 598 /* This function is required to workaround a hardware bug in some (all?) 599 * revisions of the R300. This workaround should be called after every 600 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 601 * may not be correct. 602 */ 603 if (info->ChipErrata & CHIP_ERRATA_R300_CG) { 604 uint32_t save, tmp; 605 606 save = INREG(RADEON_CLOCK_CNTL_INDEX); 607 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 608 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); 609 tmp = INREG(RADEON_CLOCK_CNTL_DATA); 610 OUTREG(RADEON_CLOCK_CNTL_INDEX, save); 611 } 612 } 613 614 /* Read PLL register */ 615 unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) 616 { 617 RADEONInfoPtr info = RADEONPTR(pScrn); 618 unsigned char *RADEONMMIO = info->MMIO; 619 uint32_t data; 620 621 OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); 622 RADEONPllErrataAfterIndex(info); 623 data = INREG(RADEON_CLOCK_CNTL_DATA); 624 RADEONPllErrataAfterData(info); 625 626 return data; 627 } 628 629 /* Write PLL information */ 630 void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data) 631 { 632 RADEONInfoPtr info = RADEONPTR(pScrn); 633 unsigned char *RADEONMMIO = info->MMIO; 634 635 OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | 636 RADEON_PLL_WR_EN)); 637 RADEONPllErrataAfterIndex(info); 638 OUTREG(RADEON_CLOCK_CNTL_DATA, data); 639 RADEONPllErrataAfterData(info); 640 } 641 642 /* Read MC register */ 643 unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) 644 { 645 RADEONInfoPtr info = RADEONPTR(pScrn); 646 unsigned char *RADEONMMIO = info->MMIO; 647 uint32_t data; 648 649 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 650 (info->ChipFamily == CHIP_FAMILY_RS740)) { 651 OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 652 data = INREG(RS690_MC_DATA); 653 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 654 OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0)); 655 data = INREG(RS600_MC_DATA); 656 } else if ((info->ChipFamily == CHIP_FAMILY_RS780) || 657 (info->ChipFamily == CHIP_FAMILY_RS880)) { 658 OUTREG(RS780_MC_INDEX, (addr & RS780_MC_INDEX_MASK)); 659 data = INREG(RS780_MC_DATA); 660 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 661 data = 0; 662 } else if (IS_AVIVO_VARIANT) { 663 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 664 (void)INREG(AVIVO_MC_INDEX); 665 data = INREG(AVIVO_MC_DATA); 666 667 OUTREG(AVIVO_MC_INDEX, 0); 668 (void)INREG(AVIVO_MC_INDEX); 669 } else { 670 OUTREG(R300_MC_IND_INDEX, addr & 0x3f); 671 (void)INREG(R300_MC_IND_INDEX); 672 data = INREG(R300_MC_IND_DATA); 673 674 OUTREG(R300_MC_IND_INDEX, 0); 675 (void)INREG(R300_MC_IND_INDEX); 676 } 677 678 return data; 679 } 680 681 /* Write MC information */ 682 void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) 683 { 684 RADEONInfoPtr info = RADEONPTR(pScrn); 685 unsigned char *RADEONMMIO = info->MMIO; 686 687 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 688 (info->ChipFamily == CHIP_FAMILY_RS740)) { 689 OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | 690 RS690_MC_INDEX_WR_EN)); 691 OUTREG(RS690_MC_DATA, data); 692 OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); 693 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 694 OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | 695 RS600_MC_IND_CITF_ARB0 | 696 RS600_MC_IND_WR_EN)); 697 OUTREG(RS600_MC_DATA, data); 698 } else if ((info->ChipFamily == CHIP_FAMILY_RS780) || 699 (info->ChipFamily == CHIP_FAMILY_RS880)) { 700 OUTREG(RS780_MC_INDEX, ((addr & RS780_MC_INDEX_MASK) | 701 RS780_MC_INDEX_WR_EN)); 702 OUTREG(RS780_MC_DATA, data); 703 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 704 // do nothing 705 } else if (IS_AVIVO_VARIANT) { 706 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); 707 (void)INREG(AVIVO_MC_INDEX); 708 OUTREG(AVIVO_MC_DATA, data); 709 OUTREG(AVIVO_MC_INDEX, 0); 710 (void)INREG(AVIVO_MC_INDEX); 711 } else { 712 OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | 713 R300_MC_IND_WR_EN)); 714 (void)INREG(R300_MC_IND_INDEX); 715 OUTREG(R300_MC_IND_DATA, data); 716 OUTREG(R300_MC_IND_INDEX, 0); 717 (void)INREG(R300_MC_IND_INDEX); 718 } 719 } 720 721 /* Read PCIE register */ 722 unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr) 723 { 724 RADEONInfoPtr info = RADEONPTR(pScrn); 725 unsigned char *RADEONMMIO = info->MMIO; 726 CARD32 data; 727 728 OUTREG(RADEON_PCIE_INDEX, addr & 0xff); 729 data = INREG(RADEON_PCIE_DATA); 730 731 return data; 732 } 733 734 /* Write PCIE register */ 735 void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data) 736 { 737 RADEONInfoPtr info = RADEONPTR(pScrn); 738 unsigned char *RADEONMMIO = info->MMIO; 739 740 OUTREG(RADEON_PCIE_INDEX, ((addr) & 0xff)); 741 OUTREG(RADEON_PCIE_DATA, data); 742 } 743 744 /* Read PCIE PORT register */ 745 unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr) 746 { 747 RADEONInfoPtr info = RADEONPTR(pScrn); 748 unsigned char *RADEONMMIO = info->MMIO; 749 CARD32 data; 750 751 OUTREG(R600_PCIE_PORT_INDEX, addr & 0xff); 752 data = INREG(R600_PCIE_PORT_DATA); 753 754 return data; 755 } 756 757 /* Write PCIE PORT register */ 758 void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data) 759 { 760 RADEONInfoPtr info = RADEONPTR(pScrn); 761 unsigned char *RADEONMMIO = info->MMIO; 762 763 OUTREG(R600_PCIE_PORT_INDEX, ((addr) & 0xff)); 764 OUTREG(R600_PCIE_PORT_DATA, data); 765 } 766 767 static Bool radeon_get_mc_idle(ScrnInfoPtr pScrn) 768 { 769 RADEONInfoPtr info = RADEONPTR(pScrn); 770 unsigned char *RADEONMMIO = info->MMIO; 771 772 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 773 if (INREG(R600_SRBM_STATUS) & 0x1f00) 774 return FALSE; 775 else 776 return TRUE; 777 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 778 if (INREG(R600_SRBM_STATUS) & 0x3f00) 779 return FALSE; 780 else 781 return TRUE; 782 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 783 if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) 784 return TRUE; 785 else 786 return FALSE; 787 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 788 if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_IDLE) 789 return TRUE; 790 else 791 return FALSE; 792 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 793 (info->ChipFamily == CHIP_FAMILY_RS740)) { 794 if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) 795 return TRUE; 796 else 797 return FALSE; 798 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 799 if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE) 800 return TRUE; 801 else 802 return FALSE; 803 } else if ((info->ChipFamily == CHIP_FAMILY_RS400) || 804 (info->ChipFamily == CHIP_FAMILY_RS480)) { 805 if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) 806 return TRUE; 807 else 808 return FALSE; 809 } else if (IS_R300_VARIANT) { 810 if (INREG(RADEON_MC_STATUS) & R300_MC_IDLE) 811 return TRUE; 812 else 813 return FALSE; 814 } else { 815 if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) 816 return TRUE; 817 else 818 return FALSE; 819 } 820 } 821 822 #define LOC_FB 0x1 823 #define LOC_AGP 0x2 824 static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t fb_loc, uint32_t agp_loc, uint32_t agp_loc_hi) 825 { 826 RADEONInfoPtr info = RADEONPTR(pScrn); 827 unsigned char *RADEONMMIO = info->MMIO; 828 829 /* evergreen is same as r7xx */ 830 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 831 if (mask & LOC_FB) 832 OUTREG(R700_MC_VM_FB_LOCATION, fb_loc); 833 if (mask & LOC_AGP) { 834 OUTREG(R700_MC_VM_AGP_BOT, agp_loc); 835 OUTREG(R700_MC_VM_AGP_TOP, agp_loc_hi); 836 } 837 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 838 if (mask & LOC_FB) 839 OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); 840 if (mask & LOC_AGP) { 841 OUTREG(R600_MC_VM_AGP_BOT, agp_loc); 842 OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); 843 } 844 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 845 if (mask & LOC_FB) 846 OUTMC(pScrn, RV515_MC_FB_LOCATION, fb_loc); 847 if (mask & LOC_AGP) 848 OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc); 849 (void)INMC(pScrn, RV515_MC_AGP_LOCATION); 850 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 851 if (mask & LOC_FB) 852 OUTMC(pScrn, RS600_MC_FB_LOCATION, fb_loc); 853 if (mask & LOC_AGP) 854 OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc); 855 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 856 (info->ChipFamily == CHIP_FAMILY_RS740)) { 857 if (mask & LOC_FB) 858 OUTMC(pScrn, RS690_MC_FB_LOCATION, fb_loc); 859 if (mask & LOC_AGP) 860 OUTMC(pScrn, RS690_MC_AGP_LOCATION, agp_loc); 861 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 862 if (mask & LOC_FB) 863 OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc); 864 if (mask & LOC_AGP) 865 OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc); 866 (void)INMC(pScrn, R520_MC_FB_LOCATION); 867 } else { 868 if (mask & LOC_FB) 869 OUTREG(RADEON_MC_FB_LOCATION, fb_loc); 870 if (mask & LOC_AGP) 871 OUTREG(RADEON_MC_AGP_LOCATION, agp_loc); 872 } 873 } 874 875 static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t *fb_loc, uint32_t *agp_loc, uint32_t *agp_loc_hi) 876 { 877 RADEONInfoPtr info = RADEONPTR(pScrn); 878 unsigned char *RADEONMMIO = info->MMIO; 879 880 /* evergreen is same as r7xx */ 881 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 882 if (mask & LOC_FB) 883 *fb_loc = INREG(R700_MC_VM_FB_LOCATION); 884 if (mask & LOC_AGP) { 885 *agp_loc = INREG(R700_MC_VM_AGP_BOT); 886 *agp_loc_hi = INREG(R700_MC_VM_AGP_TOP); 887 } 888 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 889 if (mask & LOC_FB) 890 *fb_loc = INREG(R600_MC_VM_FB_LOCATION); 891 if (mask & LOC_AGP) { 892 *agp_loc = INREG(R600_MC_VM_AGP_BOT); 893 *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); 894 } 895 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 896 if (mask & LOC_FB) 897 *fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION); 898 if (mask & LOC_AGP) { 899 *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); 900 *agp_loc_hi = 0; 901 } 902 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 903 if (mask & LOC_FB) 904 *fb_loc = INMC(pScrn, RS600_MC_FB_LOCATION); 905 if (mask & LOC_AGP) { 906 *agp_loc = INMC(pScrn, RS600_MC_AGP_LOCATION); 907 *agp_loc_hi = 0; 908 } 909 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 910 (info->ChipFamily == CHIP_FAMILY_RS740)) { 911 if (mask & LOC_FB) 912 *fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION); 913 if (mask & LOC_AGP) { 914 *agp_loc = INMC(pScrn, RS690_MC_AGP_LOCATION); 915 *agp_loc_hi = 0; 916 } 917 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 918 if (mask & LOC_FB) 919 *fb_loc = INMC(pScrn, R520_MC_FB_LOCATION); 920 if (mask & LOC_AGP) { 921 *agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION); 922 *agp_loc_hi = 0; 923 } 924 } else { 925 if (mask & LOC_FB) 926 *fb_loc = INREG(RADEON_MC_FB_LOCATION); 927 if (mask & LOC_AGP) 928 *agp_loc = INREG(RADEON_MC_AGP_LOCATION); 929 } 930 } 931 932 #if 0 933 /* Read PAL information (only used for debugging) */ 934 static int RADEONINPAL(int idx) 935 { 936 RADEONInfoPtr info = RADEONPTR(pScrn); 937 unsigned char *RADEONMMIO = info->MMIO; 938 939 OUTREG(RADEON_PALETTE_INDEX, idx << 16); 940 return INREG(RADEON_PALETTE_DATA); 941 } 942 #endif 943 944 /* Wait for vertical sync on primary CRTC */ 945 void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) 946 { 947 RADEONInfoPtr info = RADEONPTR(pScrn); 948 unsigned char *RADEONMMIO = info->MMIO; 949 uint32_t crtc_gen_cntl; 950 struct timeval timeout; 951 952 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 953 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 954 !(crtc_gen_cntl & RADEON_CRTC_EN)) 955 return; 956 957 /* Clear the CRTC_VBLANK_SAVE bit */ 958 OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 959 960 /* Wait for it to go back up */ 961 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 962 while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) && 963 !radeon_timedout(&timeout)) 964 usleep(100); 965 } 966 967 /* Wait for vertical sync on secondary CRTC */ 968 void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) 969 { 970 RADEONInfoPtr info = RADEONPTR(pScrn); 971 unsigned char *RADEONMMIO = info->MMIO; 972 uint32_t crtc2_gen_cntl; 973 struct timeval timeout; 974 975 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 976 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 977 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 978 return; 979 980 /* Clear the CRTC2_VBLANK_SAVE bit */ 981 OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 982 983 /* Wait for it to go back up */ 984 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 985 while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) && 986 !radeon_timedout(&timeout)) 987 usleep(100); 988 } 989 990 991 /* Compute log base 2 of val */ 992 int RADEONMinBits(int val) 993 { 994 int bits; 995 996 if (!val) return 1; 997 for (bits = 0; val; val >>= 1, ++bits); 998 return bits; 999 } 1000 1001 /* Compute n/d with rounding */ 1002 static int RADEONDiv(int n, int d) 1003 { 1004 return (n + (d / 2)) / d; 1005 } 1006 1007 static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) 1008 { 1009 RADEONInfoPtr info = RADEONPTR(pScrn); 1010 RADEONPLLPtr pll = &info->pll; 1011 unsigned char *RADEONMMIO = info->MMIO; 1012 unsigned char ppll_div_sel; 1013 unsigned mpll_fb_div, spll_fb_div, M; 1014 unsigned xclk, tmp, ref_div; 1015 int hTotal, vTotal, num, denom, m, n; 1016 float hz, prev_xtal, vclk, xtal, mpll, spll; 1017 long total_usecs; 1018 struct timeval start, stop, to1, to2; 1019 unsigned int f1, f2, f3; 1020 int tries = 0; 1021 1022 prev_xtal = 0; 1023 again: 1024 xtal = 0; 1025 if (++tries > 10) 1026 goto failed; 1027 1028 gettimeofday(&to1, NULL); 1029 f1 = INREG(RADEON_CRTC_CRNT_FRAME); 1030 for (;;) { 1031 f2 = INREG(RADEON_CRTC_CRNT_FRAME); 1032 if (f1 != f2) 1033 break; 1034 gettimeofday(&to2, NULL); 1035 if ((to2.tv_sec - to1.tv_sec) > 1) { 1036 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n"); 1037 goto failed; 1038 } 1039 } 1040 gettimeofday(&start, NULL); 1041 for(;;) { 1042 f3 = INREG(RADEON_CRTC_CRNT_FRAME); 1043 if (f3 != f2) 1044 break; 1045 gettimeofday(&to2, NULL); 1046 if ((to2.tv_sec - start.tv_sec) > 1) 1047 goto failed; 1048 } 1049 gettimeofday(&stop, NULL); 1050 1051 if ((stop.tv_sec - start.tv_sec) != 0) 1052 goto again; 1053 total_usecs = abs(stop.tv_usec - start.tv_usec); 1054 if (total_usecs == 0) 1055 goto again; 1056 hz = 1000000.0/(float)total_usecs; 1057 1058 hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8; 1059 vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1); 1060 vclk = (float)(hTotal * (float)(vTotal * hz)); 1061 1062 switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) { 1063 case 0: 1064 default: 1065 num = 1; 1066 denom = 1; 1067 break; 1068 case 1: 1069 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff); 1070 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 1071 num = 2*n; 1072 denom = 2*m; 1073 break; 1074 case 2: 1075 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff); 1076 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 1077 num = 2*n; 1078 denom = 2*m; 1079 break; 1080 } 1081 1082 ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1083 RADEONPllErrataAfterIndex(info); 1084 1085 n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff); 1086 m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff); 1087 1088 num *= n; 1089 denom *= m; 1090 1091 switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { 1092 case 1: 1093 denom *= 2; 1094 break; 1095 case 2: 1096 denom *= 4; 1097 break; 1098 case 3: 1099 denom *= 8; 1100 break; 1101 case 4: 1102 denom *= 3; 1103 break; 1104 case 6: 1105 denom *= 6; 1106 break; 1107 case 7: 1108 denom *= 12; 1109 break; 1110 } 1111 1112 xtal = (int)(vclk *(float)denom/(float)num); 1113 1114 if ((xtal > 26900000) && (xtal < 27100000)) 1115 xtal = 2700; 1116 else if ((xtal > 14200000) && (xtal < 14400000)) 1117 xtal = 1432; 1118 else if ((xtal > 29400000) && (xtal < 29600000)) 1119 xtal = 2950; 1120 else 1121 goto again; 1122 failed: 1123 if (xtal == 0) { 1124 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! " 1125 "Using default 27Mhz\n"); 1126 xtal = 2700; 1127 } else { 1128 if (prev_xtal == 0) { 1129 prev_xtal = xtal; 1130 tries = 0; 1131 goto again; 1132 } else if (prev_xtal != xtal) { 1133 prev_xtal = 0; 1134 goto again; 1135 } 1136 } 1137 1138 tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV); 1139 ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff; 1140 1141 /* Some sanity check based on the BIOS code .... */ 1142 if (ref_div < 2) { 1143 uint32_t tmp; 1144 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 1145 if (IS_R300_VARIANT 1146 || (info->ChipFamily == CHIP_FAMILY_RS300) 1147 || (info->ChipFamily == CHIP_FAMILY_RS400) 1148 || (info->ChipFamily == CHIP_FAMILY_RS480)) 1149 ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1150 R300_PPLL_REF_DIV_ACC_SHIFT; 1151 else 1152 ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; 1153 if (ref_div < 2) 1154 ref_div = 12; 1155 } 1156 1157 /* Calculate "base" xclk straight from MPLL, though that isn't 1158 * really useful (hopefully). This isn't called XCLK anymore on 1159 * radeon's... 1160 */ 1161 mpll_fb_div = (tmp & 0xff00) >> 8; 1162 spll_fb_div = (tmp & 0xff0000) >> 16; 1163 M = (tmp & 0xff); 1164 xclk = RADEONDiv((2 * mpll_fb_div * xtal), (M)); 1165 1166 /* 1167 * Calculate MCLK based on MCLK-A 1168 */ 1169 mpll = (2.0 * (float)mpll_fb_div * (xtal / 100.0)) / (float)M; 1170 spll = (2.0 * (float)spll_fb_div * (xtal / 100.0)) / (float)M; 1171 1172 tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7; 1173 switch(tmp) { 1174 case 1: info->mclk = mpll; break; 1175 case 2: info->mclk = mpll / 2.0; break; 1176 case 3: info->mclk = mpll / 4.0; break; 1177 case 4: info->mclk = mpll / 8.0; break; 1178 case 7: info->mclk = spll; break; 1179 default: 1180 info->mclk = 200.00; 1181 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source" 1182 " setting %d, can't probe MCLK value !\n", tmp); 1183 } 1184 1185 /* 1186 * Calculate SCLK 1187 */ 1188 tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7; 1189 switch(tmp) { 1190 case 1: info->sclk = spll; break; 1191 case 2: info->sclk = spll / 2.0; break; 1192 case 3: info->sclk = spll / 4.0; break; 1193 case 4: info->sclk = spll / 8.0; break; 1194 case 7: info->sclk = mpll; break; 1195 default: 1196 info->sclk = 200.00; 1197 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source" 1198 " setting %d, can't probe SCLK value !\n", tmp); 1199 } 1200 1201 /* we're done, hopefully these are sane values */ 1202 pll->reference_div = ref_div; 1203 pll->xclk = xclk; 1204 pll->reference_freq = xtal; 1205 1206 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, " 1207 "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk); 1208 1209 return TRUE; 1210 } 1211 1212 static void RADEONGetClockInfo(ScrnInfoPtr pScrn) 1213 { 1214 RADEONInfoPtr info = RADEONPTR (pScrn); 1215 RADEONPLLPtr pll = &info->pll; 1216 double min_dotclock; 1217 1218 if (RADEONGetClockInfoFromBIOS(pScrn)) { 1219 if (pll->reference_div < 2) { 1220 /* retrive it from register setting for fitting into current PLL algorithm. 1221 We'll probably need a new routine to calculate the best ref_div from BIOS 1222 provided min_input_pll and max_input_pll 1223 */ 1224 if (!IS_AVIVO_VARIANT) { 1225 uint32_t tmp; 1226 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 1227 if (IS_R300_VARIANT || 1228 (info->ChipFamily == CHIP_FAMILY_RS300) || 1229 (info->ChipFamily == CHIP_FAMILY_RS400) || 1230 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1231 pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; 1232 } else { 1233 pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; 1234 } 1235 } 1236 if (pll->reference_div < 2) pll->reference_div = 12; 1237 } 1238 } else { 1239 xf86DrvMsg (pScrn->scrnIndex, X_WARNING, 1240 "Video BIOS not detected, using default clock settings!\n"); 1241 1242 /* Default min/max PLL values */ 1243 if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { 1244 pll->pll_in_min = 100; 1245 pll->pll_in_max = 1350; 1246 pll->pll_out_min = 20000; 1247 pll->pll_out_max = 50000; 1248 } else { 1249 pll->pll_in_min = 40; 1250 pll->pll_in_max = 500; 1251 pll->pll_out_min = 12500; 1252 pll->pll_out_max = 35000; 1253 } 1254 1255 if (!RADEONProbePLLParameters(pScrn)) { 1256 if (info->IsIGP) 1257 pll->reference_freq = 1432; 1258 else 1259 pll->reference_freq = 2700; 1260 1261 pll->reference_div = 12; 1262 pll->xclk = 10300; 1263 1264 info->sclk = 200.00; 1265 info->mclk = 200.00; 1266 } 1267 } 1268 1269 /* card limits for computing PLLs */ 1270 if (IS_AVIVO_VARIANT) { 1271 pll->min_post_div = 2; 1272 pll->max_post_div = 0x7f; 1273 pll->min_frac_feedback_div = 0; 1274 pll->max_frac_feedback_div = 9; 1275 } else { 1276 pll->min_post_div = 1; 1277 pll->max_post_div = 12; //16 on crtc0 1278 pll->min_frac_feedback_div = 0; 1279 pll->max_frac_feedback_div = 0; 1280 } 1281 pll->min_ref_div = 2; 1282 pll->max_ref_div = 0x3ff; 1283 pll->min_feedback_div = 4; 1284 pll->max_feedback_div = 0x7ff; 1285 pll->best_vco = 0; 1286 1287 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 1288 "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", 1289 pll->reference_freq, 1290 pll->reference_div, 1291 (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max, 1292 pll->xclk); 1293 1294 /* (Some?) Radeon BIOSes seem too lie about their minimum dot 1295 * clocks. Allow users to override the detected minimum dot clock 1296 * value (e.g., and allow it to be suitable for TV sets). 1297 */ 1298 if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, 1299 OPTUNITS_MHZ, &min_dotclock)) { 1300 if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) { 1301 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1302 "Illegal minimum dotclock specified %.2f MHz " 1303 "(option ignored)\n", 1304 min_dotclock); 1305 } else { 1306 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1307 "Forced minimum dotclock to %.2f MHz " 1308 "(instead of detected %.2f MHz)\n", 1309 min_dotclock, ((double)pll->pll_out_min/1000)); 1310 pll->pll_out_min = min_dotclock * 1000; 1311 } 1312 } 1313 } 1314 1315 1316 1317 /* This is called by RADEONPreInit to set up the default visual */ 1318 Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 1319 { 1320 RADEONInfoPtr info = RADEONPTR(pScrn); 1321 1322 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 1323 return FALSE; 1324 1325 switch (pScrn->depth) { 1326 case 8: 1327 case 15: 1328 case 16: 1329 case 24: 1330 break; 1331 1332 default: 1333 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1334 "Given depth (%d) is not supported by %s driver\n", 1335 pScrn->depth, RADEON_DRIVER_NAME); 1336 return FALSE; 1337 } 1338 1339 xf86PrintDepthBpp(pScrn); 1340 1341 info->pix24bpp = xf86GetBppFromDepth(pScrn, 1342 pScrn->depth); 1343 info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel; 1344 info->CurrentLayout.depth = pScrn->depth; 1345 info->CurrentLayout.pixel_bytes = pScrn->bitsPerPixel / 8; 1346 info->CurrentLayout.pixel_code = (pScrn->bitsPerPixel != 16 1347 ? pScrn->bitsPerPixel 1348 : pScrn->depth); 1349 1350 if (info->pix24bpp == 24) { 1351 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1352 "Radeon does NOT support 24bpp\n"); 1353 return FALSE; 1354 } 1355 1356 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1357 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 1358 pScrn->depth, 1359 info->CurrentLayout.pixel_bytes, 1360 info->CurrentLayout.pixel_bytes > 1 ? "s" : "", 1361 info->pix24bpp); 1362 1363 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 1364 1365 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 1366 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1367 "Default visual (%s) is not supported at depth %d\n", 1368 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 1369 return FALSE; 1370 } 1371 return TRUE; 1372 } 1373 1374 /* This is called by RADEONPreInit to handle all color weight issues */ 1375 Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 1376 { 1377 RADEONInfoPtr info = RADEONPTR(pScrn); 1378 1379 /* Save flag for 6 bit DAC to use for 1380 setting CRTC registers. Otherwise use 1381 an 8 bit DAC, even if xf86SetWeight sets 1382 pScrn->rgbBits to some value other than 1383 8. */ 1384 info->dac6bits = FALSE; 1385 1386 if (pScrn->depth > 8) { 1387 rgb defaultWeight = { 0, 0, 0 }; 1388 1389 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 1390 } else { 1391 pScrn->rgbBits = 8; 1392 if (xf86ReturnOptValBool(info->Options, OPTION_DAC_6BIT, FALSE)) { 1393 pScrn->rgbBits = 6; 1394 info->dac6bits = TRUE; 1395 } 1396 } 1397 1398 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1399 "Using %d bits per RGB (%d bit DAC)\n", 1400 pScrn->rgbBits, info->dac6bits ? 6 : 8); 1401 1402 return TRUE; 1403 } 1404 1405 void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1406 RADEONInfoPtr info) 1407 { 1408 save->mc_fb_location = info->mc_fb_location; 1409 save->mc_agp_location = info->mc_agp_location; 1410 1411 if (IS_AVIVO_VARIANT) { 1412 save->mc_agp_location_hi = info->mc_agp_location_hi; 1413 } else { 1414 save->display_base_addr = info->fbLocation; 1415 save->display2_base_addr = info->fbLocation; 1416 save->ov0_base_addr = info->fbLocation; 1417 } 1418 } 1419 1420 static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) 1421 { 1422 RADEONInfoPtr info = RADEONPTR(pScrn); 1423 unsigned char *RADEONMMIO = info->MMIO; 1424 uint64_t mem_size; 1425 uint64_t aper_size; 1426 1427 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, 1428 &info->mc_agp_location, &info->mc_agp_location_hi); 1429 1430 /* We shouldn't use info->videoRam here which might have been clipped 1431 * but the real video RAM instead 1432 */ 1433 if (info->ChipFamily >= CHIP_FAMILY_PALM) { 1434 /* size in bytes on fusion */ 1435 mem_size = INREG(R600_CONFIG_MEMSIZE); 1436 /* size in MB on fusion */ 1437 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024; 1438 } else if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 1439 /* size in MB on evergreen */ 1440 /* XXX watch for overflow!!! */ 1441 mem_size = INREG(R600_CONFIG_MEMSIZE) * 1024 * 1024; 1442 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024; 1443 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 1444 mem_size = INREG(R600_CONFIG_MEMSIZE); 1445 aper_size = INREG(R600_CONFIG_APER_SIZE); 1446 } else { 1447 mem_size = INREG(RADEON_CONFIG_MEMSIZE); 1448 aper_size = INREG(RADEON_CONFIG_APER_SIZE); 1449 } 1450 1451 if (mem_size == 0) 1452 mem_size = 0x800000; 1453 1454 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 1455 Novell bug 204882 + along with lots of ubuntu ones */ 1456 if (aper_size > mem_size) 1457 mem_size = aper_size; 1458 1459 /* don't map the whole FB in the internal address space. 1460 * we don't currently use fb space larger than the aperture 1461 * size and on cards with more than 512 MB of vram, this can overflow 1462 * the internal top of gart calculation on some systems. 1463 * Limit it to cards with more than 512 MB as this causes problems 1464 * on some other cards due to the way the ddx and drm set up the 1465 * internal memory map. 1466 * See fdo bug 24301. 1467 */ 1468 if (mem_size > 0x20000000) 1469 mem_size = aper_size; 1470 1471 #ifdef XF86DRI 1472 /* Apply memory map limitation if using an old DRI */ 1473 if (info->directRenderingEnabled && !info->dri->newMemoryMap) { 1474 if (aper_size < mem_size) 1475 mem_size = aper_size; 1476 } 1477 #endif 1478 1479 if ((info->ChipFamily != CHIP_FAMILY_RS600) && 1480 (info->ChipFamily != CHIP_FAMILY_RS690) && 1481 (info->ChipFamily != CHIP_FAMILY_RS740) && 1482 (info->ChipFamily != CHIP_FAMILY_RS780) && 1483 (info->ChipFamily != CHIP_FAMILY_RS880) && 1484 (info->ChipFamily != CHIP_FAMILY_PALM) && 1485 (info->ChipFamily != CHIP_FAMILY_SUMO) && 1486 (info->ChipFamily != CHIP_FAMILY_SUMO2)) { 1487 if (info->IsIGP) 1488 info->mc_fb_location = INREG(RADEON_NB_TOM); 1489 else 1490 #ifdef XF86DRI 1491 /* Old DRI has restrictions on the memory map */ 1492 if ( info->directRenderingEnabled && 1493 info->dri->pKernelDRMVersion->version_minor < 10 ) 1494 info->mc_fb_location = (mem_size - 1) & 0xffff0000U; 1495 else 1496 #endif 1497 { 1498 uint64_t aper0_base; 1499 1500 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1501 aper0_base = INREG(R600_CONFIG_F0_BASE); 1502 } else { 1503 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); 1504 } 1505 1506 /* Recent chips have an "issue" with the memory controller, the 1507 * location must be aligned to the size. We just align it down, 1508 * too bad if we walk over the top of system memory, we don't 1509 * use DMA without a remapped anyway. 1510 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 1511 */ 1512 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1513 info->ChipFamily == CHIP_FAMILY_R300 || 1514 info->ChipFamily == CHIP_FAMILY_R350 || 1515 info->ChipFamily == CHIP_FAMILY_RV350 || 1516 info->ChipFamily == CHIP_FAMILY_RV380 || 1517 info->ChipFamily == CHIP_FAMILY_R420 || 1518 info->ChipFamily == CHIP_FAMILY_RV410) 1519 aper0_base &= ~(mem_size - 1); 1520 1521 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1522 uint64_t mc_fb = ((aper0_base >> 24) & 0xffff) | 1523 (((aper0_base + mem_size - 1) >> 8) & 0xffff0000); 1524 info->mc_fb_location = mc_fb & 0xffffffff; 1525 ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); 1526 } else { 1527 uint64_t mc_fb = ((aper0_base >> 16) & 0xffff) | 1528 ((aper0_base + mem_size - 1) & 0xffff0000U); 1529 info->mc_fb_location = mc_fb & 0xffffffff; 1530 } 1531 } 1532 } 1533 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1534 info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 24; 1535 } else { 1536 info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 16; 1537 } 1538 /* Just disable the damn AGP apertures for now, it may be 1539 * re-enabled later by the DRM 1540 */ 1541 if (IS_AVIVO_VARIANT) 1542 info->mc_agp_location = 0x003f0000; 1543 else 1544 info->mc_agp_location = 0xffffffc0; 1545 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1546 "RADEONInitMemoryMap() : \n"); 1547 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1548 " mem_size : 0x%08x\n", (unsigned)mem_size); 1549 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1550 " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); 1551 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1552 " MC_AGP_LOCATION : 0x%08x\n", 1553 (unsigned)info->mc_agp_location); 1554 } 1555 1556 static void RADEONGetVRamType(ScrnInfoPtr pScrn) 1557 { 1558 RADEONInfoPtr info = RADEONPTR(pScrn); 1559 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1560 unsigned char *RADEONMMIO = info->MMIO; 1561 uint32_t tmp; 1562 1563 if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) 1564 info->IsDDR = TRUE; 1565 else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 1566 info->IsDDR = TRUE; 1567 else 1568 info->IsDDR = FALSE; 1569 1570 if ((info->ChipFamily >= CHIP_FAMILY_R600) && 1571 (info->ChipFamily <= CHIP_FAMILY_RV635)) { 1572 int chansize; 1573 /* r6xx */ 1574 tmp = INREG(R600_RAMCFG); 1575 if (tmp & R600_CHANSIZE_OVERRIDE) 1576 chansize = 16; 1577 else if (tmp & R600_CHANSIZE) 1578 chansize = 64; 1579 else 1580 chansize = 32; 1581 if (info->ChipFamily == CHIP_FAMILY_R600) 1582 info->RamWidth = 8 * chansize; 1583 else if (info->ChipFamily == CHIP_FAMILY_RV670) 1584 info->RamWidth = 4 * chansize; 1585 else if ((info->ChipFamily == CHIP_FAMILY_RV610) || 1586 (info->ChipFamily == CHIP_FAMILY_RV620)) 1587 info->RamWidth = chansize; 1588 else if ((info->ChipFamily == CHIP_FAMILY_RV630) || 1589 (info->ChipFamily == CHIP_FAMILY_RV635)) 1590 info->RamWidth = 2 * chansize; 1591 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 1592 /* rv515/rv550 */ 1593 tmp = INMC(pScrn, RV515_MC_CNTL); 1594 tmp &= RV515_MEM_NUM_CHANNELS_MASK; 1595 switch (tmp) { 1596 case 0: info->RamWidth = 64; break; 1597 case 1: info->RamWidth = 128; break; 1598 default: info->RamWidth = 128; break; 1599 } 1600 } else if ((info->ChipFamily >= CHIP_FAMILY_R520) && 1601 (info->ChipFamily <= CHIP_FAMILY_RV570)){ 1602 /* r520/rv530/rv560/rv570/r580 */ 1603 tmp = INMC(pScrn, R520_MC_CNTL0); 1604 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 1605 case 0: info->RamWidth = 32; break; 1606 case 1: info->RamWidth = 64; break; 1607 case 2: info->RamWidth = 128; break; 1608 case 3: info->RamWidth = 256; break; 1609 default: info->RamWidth = 64; break; 1610 } 1611 if (tmp & R520_MC_CHANNEL_SIZE) { 1612 info->RamWidth *= 2; 1613 } 1614 } else if ((info->ChipFamily >= CHIP_FAMILY_R300) && 1615 (info->ChipFamily <= CHIP_FAMILY_RV410)) { 1616 /* r3xx, r4xx */ 1617 tmp = INREG(RADEON_MEM_CNTL); 1618 tmp &= R300_MEM_NUM_CHANNELS_MASK; 1619 switch (tmp) { 1620 case 0: info->RamWidth = 64; break; 1621 case 1: info->RamWidth = 128; break; 1622 case 2: info->RamWidth = 256; break; 1623 default: info->RamWidth = 128; break; 1624 } 1625 } else if ((info->ChipFamily == CHIP_FAMILY_RV100) || 1626 (info->ChipFamily == CHIP_FAMILY_RS100) || 1627 (info->ChipFamily == CHIP_FAMILY_RS200)){ 1628 tmp = INREG(RADEON_MEM_CNTL); 1629 if (tmp & RV100_HALF_MODE) 1630 info->RamWidth = 32; 1631 else 1632 info->RamWidth = 64; 1633 1634 if (!pRADEONEnt->HasCRTC2) { 1635 info->RamWidth /= 4; 1636 info->IsDDR = TRUE; 1637 } 1638 } else if (info->ChipFamily <= CHIP_FAMILY_RV280) { 1639 tmp = INREG(RADEON_MEM_CNTL); 1640 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) 1641 info->RamWidth = 128; 1642 else 1643 info->RamWidth = 64; 1644 } else { 1645 /* newer IGPs */ 1646 info->RamWidth = 128; 1647 } 1648 1649 /* This may not be correct, as some cards can have half of channel disabled 1650 * ToDo: identify these cases 1651 */ 1652 } 1653 1654 /* 1655 * Depending on card genertation, chipset bugs, etc... the amount of vram 1656 * accessible to the CPU can vary. This function is our best shot at figuring 1657 * it out. Returns a value in KB. 1658 */ 1659 static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) 1660 { 1661 RADEONInfoPtr info = RADEONPTR(pScrn); 1662 unsigned char *RADEONMMIO = info->MMIO; 1663 uint32_t aper_size; 1664 unsigned char byte; 1665 1666 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) 1667 /* size in MB on evergreen and fusion */ 1668 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024; 1669 else if (info->ChipFamily >= CHIP_FAMILY_R600) 1670 aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024; 1671 else 1672 aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; 1673 1674 #ifdef XF86DRI 1675 /* If we use the DRI, we need to check if it's a version that has the 1676 * bug of always cropping MC_FB_LOCATION to one aperture, in which case 1677 * we need to limit the amount of accessible video memory 1678 */ 1679 if (info->directRenderingEnabled && 1680 info->dri->pKernelDRMVersion->version_minor < 23) { 1681 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1682 "[dri] limiting video memory to one aperture of %uK\n", 1683 (unsigned)aper_size); 1684 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1685 "[dri] detected radeon kernel module version 1.%d but" 1686 " 1.23 or newer is required for full memory mapping.\n", 1687 info->dri->pKernelDRMVersion->version_minor); 1688 info->dri->newMemoryMap = FALSE; 1689 return aper_size; 1690 } 1691 info->dri->newMemoryMap = TRUE; 1692 #endif /* XF86DRI */ 1693 1694 if (info->ChipFamily >= CHIP_FAMILY_R600) 1695 return aper_size; 1696 1697 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 1698 * that is has the 2nd generation multifunction PCI interface 1699 */ 1700 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1701 info->ChipFamily == CHIP_FAMILY_RV350 || 1702 info->ChipFamily == CHIP_FAMILY_RV380 || 1703 info->ChipFamily == CHIP_FAMILY_R420 || 1704 info->ChipFamily == CHIP_FAMILY_RV410 || 1705 IS_AVIVO_VARIANT) { 1706 OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 1707 ~RADEON_HDP_APER_CNTL); 1708 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1709 "Generation 2 PCI interface, using max accessible memory\n"); 1710 return aper_size * 2; 1711 } 1712 1713 /* Older cards have all sorts of funny issues to deal with. First 1714 * check if it's a multifunction card by reading the PCI config 1715 * header type... Limit those to one aperture size 1716 */ 1717 PCI_READ_BYTE(info->PciInfo, &byte, 0xe); 1718 if (byte & 0x80) { 1719 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1720 "Generation 1 PCI interface in multifunction mode" 1721 ", accessible memory limited to one aperture\n"); 1722 return aper_size; 1723 } 1724 1725 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 1726 * have set it up. We don't write this as it's broken on some ASICs but 1727 * we expect the BIOS to have done the right thing (might be too optimistic...) 1728 */ 1729 if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 1730 return aper_size * 2; 1731 1732 return aper_size; 1733 } 1734 1735 static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) 1736 { 1737 RADEONInfoPtr info = RADEONPTR(pScrn); 1738 EntityInfoPtr pEnt = info->pEnt; 1739 GDevPtr dev = pEnt->device; 1740 unsigned char *RADEONMMIO = info->MMIO; 1741 MessageType from = X_PROBED; 1742 uint32_t accessible, bar_size; 1743 1744 if ((!IS_AVIVO_VARIANT) && info->IsIGP) { 1745 uint32_t tom = INREG(RADEON_NB_TOM); 1746 1747 pScrn->videoRam = (((tom >> 16) - 1748 (tom & 0xffff) + 1) << 6); 1749 1750 OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); 1751 } else { 1752 if (info->ChipFamily >= CHIP_FAMILY_PALM) 1753 /* R600_CONFIG_MEMSIZE is bytes on fusion */ 1754 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; 1755 else if (info->ChipFamily >= CHIP_FAMILY_CEDAR) 1756 /* R600_CONFIG_MEMSIZE is MB on evergreen */ 1757 /* XXX watch for overflow!!! */ 1758 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) * 1024; 1759 else if (info->ChipFamily >= CHIP_FAMILY_R600) 1760 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; 1761 else { 1762 /* Read VRAM size from card */ 1763 pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; 1764 1765 /* Some production boards of m6 will return 0 if it's 8 MB */ 1766 if (pScrn->videoRam == 0) { 1767 pScrn->videoRam = 8192; 1768 OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); 1769 } 1770 } 1771 } 1772 1773 /* Get accessible memory */ 1774 accessible = RADEONGetAccessibleVRAM(pScrn); 1775 1776 /* Crop it to the size of the PCI BAR */ 1777 bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024; 1778 if (bar_size == 0) 1779 bar_size = 0x20000; 1780 if (accessible > bar_size) 1781 accessible = bar_size; 1782 1783 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1784 "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n", 1785 pScrn->videoRam, (unsigned)accessible, (unsigned)bar_size); 1786 if (pScrn->videoRam > accessible) 1787 pScrn->videoRam = accessible; 1788 1789 if (!IS_AVIVO_VARIANT) { 1790 info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); 1791 info->BusCntl = INREG(RADEON_BUS_CNTL); 1792 } 1793 1794 RADEONGetVRamType(pScrn); 1795 1796 if (dev->videoRam) { 1797 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1798 "Video RAM override, using %d kB instead of %d kB\n", 1799 dev->videoRam, 1800 pScrn->videoRam); 1801 from = X_CONFIG; 1802 pScrn->videoRam = dev->videoRam; 1803 } 1804 1805 xf86DrvMsg(pScrn->scrnIndex, from, 1806 "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); 1807 1808 /* Do this before we truncate since we only map fb once */ 1809 info->FbMapSize = (pScrn->videoRam & ~1023) * 1024; 1810 1811 if (info->IsPrimary) { 1812 pScrn->videoRam /= 2; 1813 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1814 "Using %dk of videoram for primary head\n", 1815 pScrn->videoRam); 1816 } else if (info->IsSecondary) { 1817 pScrn->videoRam /= 2; 1818 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1819 "Using %dk of videoram for secondary head\n", 1820 pScrn->videoRam); 1821 } 1822 pScrn->videoRam &= ~1023; 1823 1824 /* if the card is PCI Express reserve the last 32k for the gart table */ 1825 #ifdef XF86DRI 1826 if (info->cardType == CARD_PCIE && info->directRenderingEnabled) 1827 /* work out the size of pcie aperture */ 1828 info->FbSecureSize = RADEONDRIGetPciAperTableSize(pScrn); 1829 else 1830 #endif 1831 info->FbSecureSize = 0; 1832 1833 return TRUE; 1834 } 1835 1836 1837 /* This is called by RADEONPreInit to handle config file overrides for 1838 * things like chipset and memory regions. Also determine memory size 1839 * and type. If memory type ever needs an override, put it in this 1840 * routine. 1841 */ 1842 static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) 1843 { 1844 RADEONInfoPtr info = RADEONPTR(pScrn); 1845 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1846 EntityInfoPtr pEnt = info->pEnt; 1847 GDevPtr dev = pEnt->device; 1848 unsigned char *RADEONMMIO = info->MMIO; 1849 MessageType from = X_PROBED; 1850 int i; 1851 #ifdef XF86DRI 1852 const char *s; 1853 uint32_t cmd_stat; 1854 #endif 1855 1856 /* Chipset */ 1857 from = X_PROBED; 1858 if (dev->chipset && *dev->chipset) { 1859 info->Chipset = xf86StringToToken(RADEONChipsets, dev->chipset); 1860 from = X_CONFIG; 1861 } else if (dev->chipID >= 0) { 1862 info->Chipset = dev->chipID; 1863 from = X_CONFIG; 1864 } else { 1865 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 1866 } 1867 1868 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 1869 if (!pScrn->chipset) { 1870 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1871 "ChipID 0x%04x is not recognized\n", info->Chipset); 1872 return FALSE; 1873 } 1874 if (info->Chipset < 0) { 1875 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1876 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 1877 return FALSE; 1878 } 1879 xf86DrvMsg(pScrn->scrnIndex, from, 1880 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 1881 pScrn->chipset, 1882 info->Chipset); 1883 1884 pRADEONEnt->HasCRTC2 = TRUE; 1885 info->IsMobility = FALSE; 1886 info->IsIGP = FALSE; 1887 info->IsDellServer = FALSE; 1888 info->HasSingleDAC = FALSE; 1889 info->InternalTVOut = TRUE; 1890 info->get_hardcoded_edid_from_bios = FALSE; 1891 1892 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 1893 if (info->Chipset == RADEONCards[i].pci_device_id) { 1894 RADEONCardInfo *card = &RADEONCards[i]; 1895 info->ChipFamily = card->chip_family; 1896 info->IsMobility = card->mobility; 1897 info->IsIGP = card->igp; 1898 pRADEONEnt->HasCRTC2 = !card->nocrtc2; 1899 info->HasSingleDAC = card->singledac; 1900 info->InternalTVOut = !card->nointtvout; 1901 break; 1902 } 1903 } 1904 1905 if (info->ChipFamily >= CHIP_FAMILY_SUMO) { 1906 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1907 "Chipset: \"%s\" (ChipID = 0x%04x) requires KMS\n", 1908 pScrn->chipset, 1909 info->Chipset); 1910 return FALSE; 1911 } 1912 1913 switch (info->Chipset) { 1914 case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ 1915 case PCI_CHIP_RN50_5969: 1916 /* Some Sun servers have a hardcoded edid so KVMs work properly */ 1917 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x108e) && 1918 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x4133)) 1919 info->get_hardcoded_edid_from_bios = TRUE; 1920 case PCI_CHIP_RV100_QY: 1921 case PCI_CHIP_RV100_QZ: 1922 /* DELL triple-head configuration. */ 1923 if (((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) && 1924 ((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) || 1925 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016d) || 1926 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016e) || 1927 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016f) || 1928 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0170) || 1929 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017d) || 1930 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017e) || 1931 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0183) || 1932 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x018a) || 1933 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x019a) || 1934 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01b1) || 1935 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01b2) || 1936 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0205))) || 1937 ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_HP) && 1938 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x31fb))) { 1939 info->IsDellServer = TRUE; 1940 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL/HP server detected, force to special setup\n"); 1941 } 1942 break; 1943 case PCI_CHIP_RS482_5974: 1944 /* RH BZ 444586 - non mobility version 1945 * Dell appear to have the Vostro 1100 with a mobility part with the same pci-id */ 1946 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && 1947 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x7141)) { 1948 info->IsMobility = FALSE; 1949 } 1950 default: 1951 break; 1952 } 1953 1954 from = X_PROBED; 1955 info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffULL; 1956 pScrn->memPhysBase = info->LinearAddr; 1957 if (dev->MemBase) { 1958 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1959 "Linear address override, using 0x%016lx instead of 0x%016llx\n", 1960 dev->MemBase, 1961 info->LinearAddr); 1962 info->LinearAddr = dev->MemBase; 1963 from = X_CONFIG; 1964 } else if (!info->LinearAddr) { 1965 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1966 "No valid linear framebuffer address\n"); 1967 return FALSE; 1968 } 1969 xf86DrvMsg(pScrn->scrnIndex, from, 1970 "Linear framebuffer at 0x%016llx\n", info->LinearAddr); 1971 1972 #ifndef XSERVER_LIBPCIACCESS 1973 /* BIOS */ 1974 from = X_PROBED; 1975 info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000; 1976 if (info->BIOSAddr) { 1977 xf86DrvMsg(pScrn->scrnIndex, from, 1978 "BIOS at 0x%08lx\n", (unsigned long)info->BIOSAddr); 1979 } 1980 #endif 1981 1982 /* Read registers used to determine options */ 1983 /* Check chip errata */ 1984 info->ChipErrata = 0; 1985 1986 if (info->ChipFamily == CHIP_FAMILY_R300 && 1987 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) 1988 == RADEON_CFG_ATI_REV_A11) 1989 info->ChipErrata |= CHIP_ERRATA_R300_CG; 1990 1991 if (info->ChipFamily == CHIP_FAMILY_RV200 || 1992 info->ChipFamily == CHIP_FAMILY_RS200) 1993 info->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; 1994 1995 if (info->ChipFamily == CHIP_FAMILY_RV100 || 1996 info->ChipFamily == CHIP_FAMILY_RS100 || 1997 info->ChipFamily == CHIP_FAMILY_RS200) 1998 info->ChipErrata |= CHIP_ERRATA_PLL_DELAY; 1999 2000 #ifdef XF86DRI 2001 /* AGP/PCI */ 2002 /* Proper autodetection of an AGP capable device requires examining 2003 * PCI config registers to determine if the device implements extended 2004 * PCI capabilities, and then walking the capability list as indicated 2005 * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP 2006 * capability is present. The procedure is outlined as follows: 2007 * 2008 * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device 2009 * to determine wether or not this device implements any extended 2010 * capabilities. If this bit is zero, then the device is a PCI 2.1 2011 * or earlier device and is not AGP capable, and we can conclude it 2012 * to be a PCI device. 2013 * 2014 * 2) If bit 4 of the status register is set, then the device implements 2015 * extended capabilities. There is an 8 bit wide capabilities pointer 2016 * register located at offset 0x34 in PCI config space which points to 2017 * the first capability in a linked list of extended capabilities that 2018 * this device implements. The lower two bits of this register are 2019 * reserved and MBZ so must be masked out. 2020 * 2021 * 3) The extended capabilities list is formed by one or more extended 2022 * capabilities structures which are aligned on DWORD boundaries. 2023 * The first byte of the structure is the capability ID (CAP_ID) 2024 * indicating what extended capability this structure refers to. The 2025 * second byte of the structure is an offset from the beginning of 2026 * PCI config space pointing to the next capability in the linked 2027 * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower 2028 * two bits of this pointer are reserved and MBZ. By examining the 2029 * CAP_ID of each capability and walking through the list, we will 2030 * either find the AGP_CAP_ID (0x02) indicating this device is an 2031 * AGP device, or we'll reach the end of the list, indicating it is 2032 * a PCI device. 2033 * 2034 * Mike A. Harris <mharris (at) redhat.com> 2035 * 2036 * References: 2037 * - PCI Local Bus Specification Revision 2.2, Chapter 6 2038 * - AGP Interface Specification Revision 2.0, Section 6.1.5 2039 */ 2040 2041 info->cardType = CARD_PCI; 2042 2043 PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG); 2044 if (cmd_stat & RADEON_CAP_LIST) { 2045 uint32_t cap_ptr, cap_id; 2046 2047 PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG); 2048 cap_ptr &= RADEON_CAP_PTR_MASK; 2049 2050 while(cap_ptr != RADEON_CAP_ID_NULL) { 2051 PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr); 2052 if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { 2053 info->cardType = CARD_AGP; 2054 break; 2055 } 2056 if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { 2057 info->cardType = CARD_PCIE; 2058 break; 2059 } 2060 cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; 2061 } 2062 } 2063 2064 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n", 2065 (info->cardType==CARD_PCI) ? "PCI" : 2066 (info->cardType==CARD_PCIE) ? "PCIE" : "AGP"); 2067 2068 /* treat PCIE IGP cards as PCI */ 2069 if (info->cardType == CARD_PCIE && info->IsIGP) 2070 info->cardType = CARD_PCI; 2071 2072 /* some rs4xx cards report as agp */ 2073 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 2074 (info->ChipFamily == CHIP_FAMILY_RS480)) 2075 info->cardType = CARD_PCI; 2076 2077 if ((info->ChipFamily >= CHIP_FAMILY_R600) && info->IsIGP) 2078 info->cardType = CARD_PCIE; 2079 2080 /* not sure about gart table requirements */ 2081 if ((info->ChipFamily == CHIP_FAMILY_RS600) && info->IsIGP) 2082 info->cardType = CARD_PCIE; 2083 2084 if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) { 2085 if (strcmp(s, "AGP") == 0) { 2086 info->cardType = CARD_AGP; 2087 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n"); 2088 } else if ((strcmp(s, "PCI") == 0) || 2089 (strcmp(s, "PCIE") == 0)) { 2090 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 2091 (info->ChipFamily == CHIP_FAMILY_RS480) || 2092 (info->ChipFamily == CHIP_FAMILY_RS690) || 2093 (info->ChipFamily == CHIP_FAMILY_RS740)) { 2094 info->cardType = CARD_PCI; 2095 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); 2096 } else if (info->ChipFamily >= CHIP_FAMILY_RV380) { 2097 info->cardType = CARD_PCIE; 2098 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI Express mode\n"); 2099 } else { 2100 info->cardType = CARD_PCI; 2101 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); 2102 } 2103 } else { 2104 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 2105 "Invalid BusType option, using detected type\n"); 2106 } 2107 } 2108 #endif 2109 #ifdef RENDER 2110 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 2111 info->Chipset != PCI_CHIP_RN50_515E && 2112 info->Chipset != PCI_CHIP_RN50_5969); 2113 #endif 2114 2115 info->r4xx_atom = FALSE; 2116 if (((info->ChipFamily == CHIP_FAMILY_R420) || (info->ChipFamily == CHIP_FAMILY_RV410)) && 2117 xf86ReturnOptValBool(info->Options, OPTION_R4XX_ATOM, FALSE)) { 2118 info->r4xx_atom = TRUE; 2119 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using ATOMBIOS for R4xx chip\n"); 2120 } 2121 2122 return TRUE; 2123 } 2124 2125 2126 static void RADEONPreInitDDC(ScrnInfoPtr pScrn) 2127 { 2128 RADEONInfoPtr info = RADEONPTR(pScrn); 2129 /* vbeInfoPtr pVbe; */ 2130 2131 info->ddc1 = FALSE; 2132 info->ddc_bios = FALSE; 2133 if (!xf86LoadSubModule(pScrn, "ddc")) { 2134 info->ddc2 = FALSE; 2135 } else { 2136 info->ddc2 = TRUE; 2137 } 2138 2139 /* DDC can use I2C bus */ 2140 /* Load I2C if we have the code to use it */ 2141 if (info->ddc2) { 2142 xf86LoadSubModule(pScrn, "i2c"); 2143 } 2144 } 2145 2146 /* This is called by RADEONPreInit to initialize gamma correction */ 2147 static Bool RADEONPreInitGamma(ScrnInfoPtr pScrn) 2148 { 2149 Gamma zeros = { 0.0, 0.0, 0.0 }; 2150 2151 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 2152 return TRUE; 2153 } 2154 2155 /* This is called by RADEONPreInit to initialize the hardware cursor */ 2156 static Bool RADEONPreInitCursor(ScrnInfoPtr pScrn) 2157 { 2158 RADEONInfoPtr info = RADEONPTR(pScrn); 2159 2160 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 2161 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 2162 } 2163 return TRUE; 2164 } 2165 2166 /* This is called by RADEONPreInit to initialize hardware acceleration */ 2167 static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) 2168 { 2169 RADEONInfoPtr info = RADEONPTR(pScrn); 2170 MessageType from; 2171 #if defined(USE_EXA) && defined(USE_XAA) 2172 char *optstr; 2173 #endif 2174 #ifdef XF86DRI /* zaphod FbMapSize is wrong, but no dri then */ 2175 int maxy = info->FbMapSize / (pScrn->displayWidth * info->CurrentLayout.pixel_bytes); 2176 #endif 2177 2178 if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) { 2179 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); 2180 return FALSE; 2181 } 2182 info->accel_state->fifo_slots = 0; 2183 2184 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 2185 (info->ChipFamily == CHIP_FAMILY_RS200) || 2186 (info->ChipFamily == CHIP_FAMILY_RS300) || 2187 (info->ChipFamily == CHIP_FAMILY_RS400) || 2188 (info->ChipFamily == CHIP_FAMILY_RS480) || 2189 (info->ChipFamily == CHIP_FAMILY_RS600) || 2190 (info->ChipFamily == CHIP_FAMILY_RS690) || 2191 (info->ChipFamily == CHIP_FAMILY_RS740)) 2192 info->accel_state->has_tcl = FALSE; 2193 else { 2194 info->accel_state->has_tcl = TRUE; 2195 } 2196 2197 /* if we have shadow fb bail */ 2198 if (info->r600_shadow_fb) { 2199 info->useEXA = FALSE; 2200 return TRUE; 2201 } 2202 2203 #ifdef XF86DRI 2204 if ((!info->directRenderingEnabled) || 2205 (maxy <= pScrn->virtualY * 3) || 2206 (pScrn->videoRam <= 32768)) 2207 info->useEXA = FALSE; 2208 else 2209 info->useEXA = TRUE; 2210 #else 2211 info->useEXA = FALSE; 2212 #endif 2213 2214 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 2215 int errmaj = 0, errmin = 0; 2216 2217 from = X_DEFAULT; 2218 #if defined(USE_EXA) 2219 #if defined(USE_XAA) 2220 optstr = (char *)xf86GetOptValString(info->Options, OPTION_ACCELMETHOD); 2221 if (optstr != NULL) { 2222 if (xf86NameCmp(optstr, "EXA") == 0) { 2223 from = X_CONFIG; 2224 info->useEXA = TRUE; 2225 } else if (xf86NameCmp(optstr, "XAA") == 0) { 2226 from = X_CONFIG; 2227 if (info->ChipFamily < CHIP_FAMILY_R600) 2228 info->useEXA = FALSE; 2229 } 2230 } 2231 #else /* USE_XAA */ 2232 info->useEXA = TRUE; 2233 #endif /* !USE_XAA */ 2234 #else 2235 info->useEXA = FALSE; 2236 #endif /* USE_EXA */ 2237 if (info->ChipFamily < CHIP_FAMILY_R600) 2238 xf86DrvMsg(pScrn->scrnIndex, from, 2239 "Using %s acceleration architecture\n", 2240 info->useEXA ? "EXA" : "XAA"); 2241 else 2242 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, 2243 "Will attempt to use R6xx/R7xx EXA support if DRI is enabled.\n"); 2244 2245 #ifdef USE_EXA 2246 if (info->useEXA) { 2247 info->exaReq.majorversion = EXA_VERSION_MAJOR; 2248 info->exaReq.minorversion = EXA_VERSION_MINOR; 2249 2250 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 2251 &info->exaReq, &errmaj, &errmin)) { 2252 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 2253 return FALSE; 2254 } 2255 } 2256 #endif /* USE_EXA */ 2257 #ifdef USE_XAA 2258 if (!info->useEXA) { 2259 info->xaaReq.majorversion = 1; 2260 info->xaaReq.minorversion = 2; 2261 2262 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2263 &info->xaaReq, &errmaj, &errmin)) { 2264 info->xaaReq.minorversion = 1; 2265 2266 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2267 &info->xaaReq, &errmaj, &errmin)) { 2268 info->xaaReq.minorversion = 0; 2269 2270 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2271 &info->xaaReq, &errmaj, &errmin)) { 2272 LoaderErrorMsg(NULL, "xaa", errmaj, errmin); 2273 return FALSE; 2274 } 2275 } 2276 } 2277 } 2278 #endif /* USE_XAA */ 2279 } else { 2280 /* NoAccel */ 2281 info->useEXA = FALSE; 2282 } 2283 2284 return TRUE; 2285 } 2286 2287 static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) 2288 { 2289 #if (!defined(__powerpc__) && !defined(__sparc__)) || \ 2290 (defined(XSERVER_LIBPCIACCESS) && HAVE_PCI_DEVICE_ENABLE) 2291 RADEONInfoPtr info = RADEONPTR(pScrn); 2292 #endif 2293 #if !defined(__powerpc__) && !defined(__sparc__) 2294 unsigned char *RADEONMMIO = info->MMIO; 2295 uint32_t fp2_gen_ctl_save = 0; 2296 #endif 2297 2298 #ifdef XSERVER_LIBPCIACCESS 2299 #if HAVE_PCI_DEVICE_ENABLE 2300 pci_device_enable(info->PciInfo); 2301 #endif 2302 #endif 2303 2304 #if !defined(__powerpc__) && !defined(__sparc__) 2305 /* don't need int10 on atom cards. 2306 * in theory all radeons, but the older stuff 2307 * isn't 100% yet 2308 * secondary atom cards tend to hang when initializing int10, 2309 * however, on some stom cards, you can't read the bios without 2310 * intitializing int10. 2311 */ 2312 if (!xf86ReturnOptValBool(info->Options, OPTION_INT10, TRUE)) 2313 return TRUE; 2314 2315 if (xf86LoadSubModule(pScrn, "int10")) { 2316 /* The VGA BIOS on the RV100/QY cannot be read when the digital output 2317 * is enabled. Clear and restore FP2_ON around int10 to avoid this. 2318 */ 2319 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2320 fp2_gen_ctl_save = INREG(RADEON_FP2_GEN_CNTL); 2321 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2322 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "disabling digital out\n"); 2323 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); 2324 } 2325 } 2326 2327 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); 2328 *ppInt10 = xf86InitInt10(info->pEnt->index); 2329 2330 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2331 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2332 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); 2333 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); 2334 } 2335 } 2336 } 2337 #endif 2338 return TRUE; 2339 } 2340 2341 #ifdef XF86DRI 2342 static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) 2343 { 2344 RADEONInfoPtr info = RADEONPTR(pScrn); 2345 Bool ret; 2346 MessageType from; 2347 char *reason; 2348 2349 info->directRenderingEnabled = FALSE; 2350 info->directRenderingInited = FALSE; 2351 2352 if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) { 2353 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); 2354 return FALSE; 2355 } 2356 2357 if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) { 2358 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); 2359 return FALSE; 2360 } 2361 info->cp->CPInUse = FALSE; 2362 info->cp->CPStarted = FALSE; 2363 info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; 2364 2365 if (xf86IsEntityShared(info->pEnt->index)) { 2366 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2367 "Direct Rendering Disabled -- " 2368 "Zaphod Dual-head configuration is not working with " 2369 "DRI at present.\n" 2370 "Please use the xrandr 1.2 if you " 2371 "want Dual-head with DRI.\n"); 2372 return FALSE; 2373 } 2374 if (info->IsSecondary) 2375 return FALSE; 2376 2377 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 2378 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2379 "No DRI yet on Evergreen\n"); 2380 return FALSE; 2381 } 2382 2383 if (info->Chipset == PCI_CHIP_RN50_515E || 2384 info->Chipset == PCI_CHIP_RN50_5969) { 2385 if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { 2386 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2387 "Direct rendering for RN50 forced on -- " 2388 "This is NOT officially supported at the hardware level " 2389 "and may cause instability or lockups\n"); 2390 } else { 2391 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2392 "Direct rendering not officially supported on RN50\n"); 2393 return FALSE; 2394 } 2395 } 2396 2397 if (!xf86ReturnOptValBool(info->Options, OPTION_DRI, TRUE)) { 2398 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2399 "Direct rendering forced off\n"); 2400 return FALSE; 2401 } 2402 2403 if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 2404 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2405 "[dri] Acceleration disabled, not initializing the DRI\n"); 2406 return FALSE; 2407 } 2408 2409 info->dri->pLibDRMVersion = NULL; 2410 info->dri->pKernelDRMVersion = NULL; 2411 2412 ret = RADEONDRIGetVersion(pScrn); 2413 if (ret <= 0) 2414 return ret; 2415 2416 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2417 "[dri] Found DRI library version %d.%d.%d and kernel" 2418 " module version %d.%d.%d\n", 2419 info->dri->pLibDRMVersion->version_major, 2420 info->dri->pLibDRMVersion->version_minor, 2421 info->dri->pLibDRMVersion->version_patchlevel, 2422 info->dri->pKernelDRMVersion->version_major, 2423 info->dri->pKernelDRMVersion->version_minor, 2424 info->dri->pKernelDRMVersion->version_patchlevel); 2425 2426 if (info->Chipset == PCI_CHIP_RS400_5A41 || 2427 info->Chipset == PCI_CHIP_RS400_5A42 || 2428 info->Chipset == PCI_CHIP_RC410_5A61 || 2429 info->Chipset == PCI_CHIP_RC410_5A62 || 2430 info->Chipset == PCI_CHIP_RS480_5954 || 2431 info->Chipset == PCI_CHIP_RS480_5955 || 2432 info->Chipset == PCI_CHIP_RS482_5974 || 2433 info->Chipset == PCI_CHIP_RS485_5975) { 2434 2435 if (info->dri->pKernelDRMVersion->version_minor < 27) { 2436 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2437 "Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n"); 2438 return FALSE; 2439 } 2440 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2441 "Direct rendering experimental on RS400/Xpress 200 enabled\n"); 2442 } 2443 2444 if (info->ChipFamily >= CHIP_FAMILY_R300) 2445 info->dri->gartSize = R300_DEFAULT_GART_SIZE; 2446 else 2447 info->dri->gartSize = RADEON_DEFAULT_GART_SIZE; 2448 2449 info->dri->ringSize = RADEON_DEFAULT_RING_SIZE; 2450 info->dri->bufSize = RADEON_DEFAULT_BUFFER_SIZE; 2451 info->dri->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE; 2452 info->dri->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE; 2453 info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; 2454 2455 if ((xf86GetOptValInteger(info->Options, 2456 OPTION_GART_SIZE, (int *)&(info->dri->gartSize))) || 2457 (xf86GetOptValInteger(info->Options, 2458 OPTION_GART_SIZE_OLD, (int *)&(info->dri->gartSize)))) { 2459 switch (info->dri->gartSize) { 2460 case 4: 2461 case 8: 2462 case 16: 2463 case 32: 2464 case 64: 2465 case 128: 2466 case 256: 2467 break; 2468 2469 default: 2470 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2471 "Illegal GART size: %d MB\n", info->dri->gartSize); 2472 return FALSE; 2473 } 2474 } 2475 2476 if (xf86GetOptValInteger(info->Options, 2477 OPTION_RING_SIZE, &(info->dri->ringSize))) { 2478 if (info->dri->ringSize < 1 || info->dri->ringSize >= (int)info->dri->gartSize) { 2479 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2480 "Illegal ring buffer size: %d MB\n", 2481 info->dri->ringSize); 2482 return FALSE; 2483 } 2484 } 2485 2486 if (xf86GetOptValInteger(info->Options, 2487 OPTION_PCIAPER_SIZE, &(info->dri->pciAperSize))) { 2488 switch(info->dri->pciAperSize) { 2489 case 32: 2490 case 64: 2491 case 128: 2492 case 256: 2493 break; 2494 default: 2495 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2496 "Illegal pci aper size: %d MB\n", 2497 info->dri->pciAperSize); 2498 return FALSE; 2499 } 2500 } 2501 2502 2503 if (xf86GetOptValInteger(info->Options, 2504 OPTION_BUFFER_SIZE, &(info->dri->bufSize))) { 2505 if (info->dri->bufSize < 1 || info->dri->bufSize >= (int)info->dri->gartSize) { 2506 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2507 "Illegal vertex/indirect buffers size: %d MB\n", 2508 info->dri->bufSize); 2509 return FALSE; 2510 } 2511 if (info->dri->bufSize > 2) { 2512 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2513 "Illegal vertex/indirect buffers size: %d MB\n", 2514 info->dri->bufSize); 2515 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2516 "Clamping vertex/indirect buffers size to 2 MB\n"); 2517 info->dri->bufSize = 2; 2518 } 2519 } 2520 2521 if (info->dri->ringSize + info->dri->bufSize + info->dri->gartTexSize > 2522 (int)info->dri->gartSize) { 2523 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2524 "Buffers are too big for requested GART space\n"); 2525 return FALSE; 2526 } 2527 2528 info->dri->gartTexSize = info->dri->gartSize - (info->dri->ringSize + info->dri->bufSize); 2529 2530 if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT, 2531 &(info->cp->CPusecTimeout))) { 2532 /* This option checked by the RADEON DRM kernel module */ 2533 } 2534 2535 /* Two options to try and squeeze as much texture memory as possible 2536 * for dedicated 3d rendering boxes 2537 */ 2538 info->dri->noBackBuffer = xf86ReturnOptValBool(info->Options, 2539 OPTION_NO_BACKBUFFER, 2540 FALSE); 2541 2542 info->dri->allowPageFlip = 0; 2543 2544 #ifdef DAMAGE 2545 if (info->dri->noBackBuffer) { 2546 from = X_DEFAULT; 2547 reason = " because back buffer disabled"; 2548 } else { 2549 from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, 2550 &info->dri->allowPageFlip) ? X_CONFIG : X_DEFAULT; 2551 2552 if (IS_AVIVO_VARIANT) { 2553 info->dri->allowPageFlip = 0; 2554 reason = " on r5xx and newer chips.\n"; 2555 } else { 2556 reason = ""; 2557 } 2558 2559 } 2560 #else 2561 from = X_DEFAULT; 2562 reason = " because Damage layer not available at build time"; 2563 #endif 2564 2565 xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n", 2566 info->dri->allowPageFlip ? "en" : "dis", reason); 2567 2568 /* AGP seems to have problems with gart transfers */ 2569 if ((info->ChipFamily >= CHIP_FAMILY_R600) && (info->cardType == CARD_AGP)) 2570 info->DMAForXv = FALSE; 2571 else 2572 info->DMAForXv = TRUE; 2573 from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv) 2574 ? X_CONFIG : X_INFO; 2575 xf86DrvMsg(pScrn->scrnIndex, from, 2576 "Will %stry to use DMA for Xv image transfers\n", 2577 info->DMAForXv ? "" : "not "); 2578 2579 return TRUE; 2580 } 2581 #endif /* XF86DRI */ 2582 2583 static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) 2584 { 2585 RADEONInfoPtr info = RADEONPTR(pScrn); 2586 2587 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 2588 OPTION_COLOR_TILING, TRUE); 2589 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 2590 /* this may be 4096 on r4xx -- need to double check */ 2591 info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ 2592 info->MaxLines = 4096; 2593 } else { 2594 info->MaxSurfaceWidth = 2048; 2595 info->MaxLines = 2048; 2596 } 2597 2598 if (!info->allowColorTiling) 2599 return; 2600 2601 if (info->ChipFamily >= CHIP_FAMILY_R600) 2602 info->allowColorTiling = FALSE; 2603 2604 /* for zaphod disable tiling for now */ 2605 if (info->IsPrimary || info->IsSecondary) 2606 info->allowColorTiling = FALSE; 2607 2608 #ifdef XF86DRI 2609 if (info->directRenderingEnabled && 2610 info->dri->pKernelDRMVersion->version_minor < 14) { 2611 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2612 "[dri] color tiling disabled because of version " 2613 "mismatch.\n" 2614 "[dri] radeon.o kernel module version is %d.%d.%d but " 2615 "1.14.0 or later is required for color tiling.\n", 2616 info->dri->pKernelDRMVersion->version_major, 2617 info->dri->pKernelDRMVersion->version_minor, 2618 info->dri->pKernelDRMVersion->version_patchlevel); 2619 info->allowColorTiling = FALSE; 2620 return; 2621 } 2622 #endif /* XF86DRI */ 2623 2624 if (info->allowColorTiling) { 2625 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling enabled by default\n"); 2626 } else { 2627 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled\n"); 2628 } 2629 } 2630 2631 2632 static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) 2633 { 2634 RADEONInfoPtr info = RADEONPTR(pScrn); 2635 uint16_t mm_table; 2636 uint16_t bios_header; 2637 uint16_t pll_info_block; 2638 #ifdef XvExtension 2639 const char* microc_path = NULL; 2640 const char* microc_type = NULL; 2641 MessageType from; 2642 2643 if (xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY, 2644 &(info->videoKey))) { 2645 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n", 2646 info->videoKey); 2647 } else { 2648 info->videoKey = 0x1E; 2649 } 2650 2651 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_CRYSTAL, &(info->RageTheatreCrystal))) { 2652 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Crystal frequency was specified as %d.%d Mhz\n", 2653 info->RageTheatreCrystal/100, info->RageTheatreCrystal % 100); 2654 } else { 2655 info->RageTheatreCrystal=-1; 2656 } 2657 2658 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_TUNER_PORT, &(info->RageTheatreTunerPort))) { 2659 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre tuner port was specified as %d\n", 2660 info->RageTheatreTunerPort); 2661 } else { 2662 info->RageTheatreTunerPort=-1; 2663 } 2664 2665 if(info->RageTheatreTunerPort>5){ 2666 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre tuner port to invalid value. Disabling setting\n"); 2667 info->RageTheatreTunerPort=-1; 2668 } 2669 2670 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_COMPOSITE_PORT, &(info->RageTheatreCompositePort))) { 2671 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre composite port was specified as %d\n", 2672 info->RageTheatreCompositePort); 2673 } else { 2674 info->RageTheatreCompositePort=-1; 2675 } 2676 2677 if(info->RageTheatreCompositePort>6){ 2678 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre composite port to invalid value. Disabling setting\n"); 2679 info->RageTheatreCompositePort=-1; 2680 } 2681 2682 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_SVIDEO_PORT, &(info->RageTheatreSVideoPort))) { 2683 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre SVideo Port was specified as %d\n", 2684 info->RageTheatreSVideoPort); 2685 } else { 2686 info->RageTheatreSVideoPort=-1; 2687 } 2688 2689 if(info->RageTheatreSVideoPort>6){ 2690 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre SVideo port to invalid value. Disabling setting\n"); 2691 info->RageTheatreSVideoPort=-1; 2692 } 2693 2694 if(xf86GetOptValInteger(info->Options, OPTION_TUNER_TYPE, &(info->tunerType))) { 2695 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tuner type was specified as %d\n", 2696 info->tunerType); 2697 } else { 2698 info->tunerType=-1; 2699 } 2700 2701 if(info->tunerType>31){ 2702 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set tuner type to invalid value. Disabling setting\n"); 2703 info->tunerType=-1; 2704 } 2705 2706 if((microc_path = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_PATH)) != NULL) 2707 { 2708 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode path was specified as %s\n", microc_path); 2709 info->RageTheatreMicrocPath = microc_path; 2710 } else { 2711 info->RageTheatreMicrocPath= NULL; 2712 } 2713 2714 if((microc_type = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_TYPE)) != NULL) 2715 { 2716 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode type was specified as %s\n", microc_type); 2717 info->RageTheatreMicrocType = microc_type; 2718 } else { 2719 info->RageTheatreMicrocType= NULL; 2720 } 2721 2722 if(xf86GetOptValInteger(info->Options, OPTION_SCALER_WIDTH, &(info->overlay_scaler_buffer_width))) { 2723 if ((info->overlay_scaler_buffer_width < 1024) || 2724 (info->overlay_scaler_buffer_width > 2048) || 2725 ((info->overlay_scaler_buffer_width % 64) != 0)) { 2726 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set illegal scaler width. Using default\n"); 2727 from = X_DEFAULT; 2728 info->overlay_scaler_buffer_width = 0; 2729 } else 2730 from = X_CONFIG; 2731 } else { 2732 from = X_DEFAULT; 2733 info->overlay_scaler_buffer_width = 0; 2734 } 2735 if (!info->overlay_scaler_buffer_width) { 2736 /* overlay scaler line length differs for different revisions 2737 this needs to be maintained by hand */ 2738 switch(info->ChipFamily){ 2739 case CHIP_FAMILY_R200: 2740 case CHIP_FAMILY_R300: 2741 case CHIP_FAMILY_R350: 2742 case CHIP_FAMILY_RV350: 2743 case CHIP_FAMILY_RV380: 2744 case CHIP_FAMILY_R420: 2745 case CHIP_FAMILY_RV410: 2746 info->overlay_scaler_buffer_width = 1920; 2747 break; 2748 default: 2749 info->overlay_scaler_buffer_width = 1536; 2750 } 2751 } 2752 xf86DrvMsg(pScrn->scrnIndex, from, "Assuming overlay scaler buffer width is %d\n", 2753 info->overlay_scaler_buffer_width); 2754 #endif 2755 2756 /* Rescue MM_TABLE before VBIOS is freed */ 2757 info->MM_TABLE_valid = FALSE; 2758 2759 if((info->VBIOS==NULL)||(info->VBIOS[0]!=0x55)||(info->VBIOS[1]!=0xaa)){ 2760 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Cannot access BIOS or it is not valid.\n" 2761 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2762 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2763 ); 2764 info->MM_TABLE_valid = FALSE; 2765 return TRUE; 2766 } 2767 2768 bios_header=info->VBIOS[0x48]; 2769 bios_header+=(((int)info->VBIOS[0x49]+0)<<8); 2770 2771 mm_table=info->VBIOS[bios_header+0x38]; 2772 if(mm_table==0) 2773 { 2774 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"No MM_TABLE found - assuming CARD is not TV-in capable.\n"); 2775 info->MM_TABLE_valid = FALSE; 2776 return TRUE; 2777 } 2778 mm_table+=(((int)info->VBIOS[bios_header+0x39]+0)<<8)-2; 2779 2780 if(mm_table>0) 2781 { 2782 memcpy(&(info->MM_TABLE), &(info->VBIOS[mm_table]), sizeof(info->MM_TABLE)); 2783 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2784 info->MM_TABLE.table_revision, 2785 info->MM_TABLE.table_size, 2786 info->MM_TABLE.tuner_type, 2787 info->MM_TABLE.audio_chip, 2788 info->MM_TABLE.product_id, 2789 info->MM_TABLE.tuner_voltage_teletext_fm, 2790 info->MM_TABLE.i2s_config, 2791 info->MM_TABLE.video_decoder_type, 2792 info->MM_TABLE.video_decoder_host_config, 2793 info->MM_TABLE.input[0], 2794 info->MM_TABLE.input[1], 2795 info->MM_TABLE.input[2], 2796 info->MM_TABLE.input[3], 2797 info->MM_TABLE.input[4]); 2798 2799 /* Is it an MM_TABLE we know about ? */ 2800 if(info->MM_TABLE.table_size != 0xc){ 2801 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "This card has MM_TABLE we do not recognize.\n" 2802 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2803 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2804 ); 2805 info->MM_TABLE_valid = FALSE; 2806 return TRUE; 2807 } 2808 info->MM_TABLE_valid = TRUE; 2809 } else { 2810 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No MM_TABLE found - assuming card is not TV-in capable (mm_table=%d).\n", mm_table); 2811 info->MM_TABLE_valid = FALSE; 2812 } 2813 2814 pll_info_block=info->VBIOS[bios_header+0x30]; 2815 pll_info_block+=(((int)info->VBIOS[bios_header+0x31]+0)<<8); 2816 2817 info->video_decoder_type=info->VBIOS[pll_info_block+0x08]; 2818 info->video_decoder_type+=(((int)info->VBIOS[pll_info_block+0x09]+0)<<8); 2819 2820 return TRUE; 2821 } 2822 2823 static Bool 2824 RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) 2825 { 2826 RADEONInfoPtr info = RADEONPTR(pScrn); 2827 2828 if (!RADEONGetBIOSInfo(pScrn, pInt10)) { 2829 /* Avivo chips require bios for atom */ 2830 if (IS_AVIVO_VARIANT) 2831 return FALSE; 2832 } 2833 return TRUE; 2834 } 2835 2836 Bool 2837 RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name) 2838 { 2839 int i = 0; 2840 char s1[20]; 2841 2842 do { 2843 switch(*s) { 2844 case ',': 2845 s1[i] = '\0'; 2846 i = 0; 2847 if (strcmp(s1, output_name) == 0) 2848 return TRUE; 2849 break; 2850 case ' ': 2851 case '\t': 2852 case '\n': 2853 case '\r': 2854 break; 2855 default: 2856 s1[i] = *s; 2857 i++; 2858 break; 2859 } 2860 } while(*s++); 2861 2862 s1[i] = '\0'; 2863 if (strcmp(s1, output_name) == 0) 2864 return TRUE; 2865 2866 return FALSE; 2867 } 2868 2869 static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) 2870 { 2871 RADEONInfoPtr info = RADEONPTR(pScrn); 2872 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2873 int o; 2874 const char *s; 2875 2876 if ((s = xf86GetOptValString(info->Options, OPTION_ZAPHOD_HEADS))) { 2877 for (o = config->num_output; o > 0; o--) { 2878 if (!RADEONZaphodStringMatches(pScrn, s, config->output[o - 1]->name)) 2879 xf86OutputDestroy(config->output[o - 1]); 2880 } 2881 } else { 2882 if (info->IsPrimary) { 2883 xf86OutputDestroy(config->output[0]); 2884 while (config->num_output > 1) { 2885 xf86OutputDestroy(config->output[1]); 2886 } 2887 } else { 2888 while (config->num_output > 1) { 2889 xf86OutputDestroy(config->output[1]); 2890 } 2891 } 2892 } 2893 } 2894 2895 static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) 2896 { 2897 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2898 RADEONInfoPtr info = RADEONPTR(pScrn); 2899 int i; 2900 int mask; 2901 int found = 0; 2902 2903 if (info->IsPrimary) 2904 mask = 1; 2905 else if (info->IsSecondary) 2906 mask = 2; 2907 else 2908 mask = 3; 2909 2910 if (!RADEONAllocateControllers(pScrn, mask)) 2911 return FALSE; 2912 2913 RADEONGetClockInfo(pScrn); 2914 2915 if (info->IsAtomBios && info->IsIGP) 2916 RADEONATOMGetIGPInfo(pScrn); 2917 2918 if (!RADEONSetupConnectors(pScrn)) { 2919 return FALSE; 2920 } 2921 2922 if (info->IsPrimary || info->IsSecondary) { 2923 /* fixup outputs for zaphod */ 2924 RADEONFixZaphodOutputs(pScrn); 2925 } 2926 2927 RADEONPrintPortMap(pScrn); 2928 2929 info->first_load_no_devices = FALSE; 2930 for (i = 0; i < config->num_output; i++) { 2931 xf86OutputPtr output = config->output[i]; 2932 2933 output->status = (*output->funcs->detect) (output); 2934 ErrorF("finished output detect: %d\n", i); 2935 if (info->IsPrimary || info->IsSecondary) { 2936 if (output->status != XF86OutputStatusConnected) 2937 return FALSE; 2938 } 2939 if (output->status != XF86OutputStatusDisconnected) 2940 found++; 2941 } 2942 2943 if (!found) { 2944 /* nothing connected, light up some defaults so the server comes up */ 2945 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No connected devices found!\n"); 2946 info->first_load_no_devices = TRUE; 2947 } 2948 2949 ErrorF("finished all detect\n"); 2950 return TRUE; 2951 } 2952 2953 static void 2954 RADEONProbeDDC(ScrnInfoPtr pScrn, int indx) 2955 { 2956 vbeInfoPtr pVbe; 2957 2958 if (xf86LoadSubModule(pScrn, "vbe")) { 2959 pVbe = VBEInit(NULL,indx); 2960 ConfiguredMonitor = vbeDoEDID(pVbe, NULL); 2961 vbeFree(pVbe); 2962 } 2963 } 2964 2965 static Bool 2966 RADEONCRTCResize(ScrnInfoPtr scrn, int width, int height) 2967 { 2968 scrn->virtualX = width; 2969 scrn->virtualY = height; 2970 /* RADEONSetPitch(scrn); */ 2971 return TRUE; 2972 } 2973 2974 static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { 2975 RADEONCRTCResize 2976 }; 2977 2978 Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) 2979 { 2980 xf86CrtcConfigPtr xf86_config; 2981 RADEONInfoPtr info; 2982 xf86Int10InfoPtr pInt10 = NULL; 2983 void *int10_save = NULL; 2984 const char *s; 2985 RADEONEntPtr pRADEONEnt; 2986 DevUnion* pPriv; 2987 2988 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2989 "RADEONPreInit\n"); 2990 if (pScrn->numEntities != 1) return FALSE; 2991 2992 if (!RADEONGetRec(pScrn)) return FALSE; 2993 2994 info = RADEONPTR(pScrn); 2995 info->MMIO = NULL; 2996 2997 info->IsSecondary = FALSE; 2998 info->IsPrimary = FALSE; 2999 info->kms_enabled = FALSE; 3000 3001 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 3002 if (info->pEnt->location.type != BUS_PCI) goto fail; 3003 3004 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 3005 getRADEONEntityIndex()); 3006 pRADEONEnt = pPriv->ptr; 3007 3008 if(xf86IsEntityShared(pScrn->entityList[0])) 3009 { 3010 if(xf86IsPrimInitDone(pScrn->entityList[0])) 3011 { 3012 info->IsSecondary = TRUE; 3013 pRADEONEnt->pSecondaryScrn = pScrn; 3014 info->SavedReg = &pRADEONEnt->SavedReg; 3015 info->ModeReg = &pRADEONEnt->ModeReg; 3016 } 3017 else 3018 { 3019 info->IsPrimary = TRUE; 3020 xf86SetPrimInitDone(pScrn->entityList[0]); 3021 pRADEONEnt->pPrimaryScrn = pScrn; 3022 pRADEONEnt->HasSecondary = FALSE; 3023 info->SavedReg = &pRADEONEnt->SavedReg; 3024 info->ModeReg = &pRADEONEnt->ModeReg; 3025 } 3026 } else { 3027 info->SavedReg = &pRADEONEnt->SavedReg; 3028 info->ModeReg = &pRADEONEnt->ModeReg; 3029 } 3030 3031 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 3032 #ifndef XSERVER_LIBPCIACCESS 3033 info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), 3034 PCI_DEV_DEV(info->PciInfo), 3035 PCI_DEV_FUNC(info->PciInfo)); 3036 #endif 3037 info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL; 3038 info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2); 3039 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n", 3040 (unsigned long long)PCI_REGION_BASE(info->PciInfo, 3041 2, REGION_MEM)); 3042 if (info->pEnt->device->IOBase) { 3043 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 3044 "MMIO address override, using 0x%08lx instead of 0x%016llx\n", 3045 info->pEnt->device->IOBase, 3046 info->MMIOAddr); 3047 info->MMIOAddr = info->pEnt->device->IOBase; 3048 } else if (!info->MMIOAddr) { 3049 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid MMIO address\n"); 3050 goto fail1; 3051 } 3052 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3053 "MMIO registers at 0x%016llx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); 3054 3055 if(!RADEONMapMMIO(pScrn)) { 3056 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3057 "Memory map the MMIO region failed\n"); 3058 goto fail1; 3059 } 3060 3061 #if !defined(__alpha__) 3062 if ( 3063 #ifndef XSERVER_LIBPCIACCESS 3064 xf86GetPciDomain(info->PciTag) || 3065 #endif 3066 !xf86IsPrimaryPci(info->PciInfo)) 3067 RADEONPreInt10Save(pScrn, &int10_save); 3068 #else 3069 /* [Alpha] On the primary, the console already ran the BIOS and we're 3070 * going to run it again - so make sure to "fix up" the card 3071 * so that (1) we can read the BIOS ROM and (2) the BIOS will 3072 * get the memory config right. 3073 */ 3074 RADEONPreInt10Save(pScrn, &int10_save); 3075 #endif 3076 3077 if (flags & PROBE_DETECT) { 3078 RADEONProbeDDC(pScrn, info->pEnt->index); 3079 RADEONPostInt10Check(pScrn, int10_save); 3080 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3081 return TRUE; 3082 } 3083 3084 3085 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3086 "PCI bus %d card %d func %d\n", 3087 PCI_DEV_BUS(info->PciInfo), 3088 PCI_DEV_DEV(info->PciInfo), 3089 PCI_DEV_FUNC(info->PciInfo)); 3090 3091 #ifndef XSERVER_LIBPCIACCESS 3092 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) 3093 goto fail; 3094 3095 xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr); 3096 3097 pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; 3098 #endif 3099 pScrn->monitor = pScrn->confScreen->monitor; 3100 3101 /* Allocate an xf86CrtcConfig */ 3102 xf86CrtcConfigInit (pScrn, &RADEONCRTCResizeFuncs); 3103 xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 3104 3105 3106 if (!RADEONPreInitVisual(pScrn)) 3107 goto fail; 3108 3109 /* We can't do this until we have a 3110 pScrn->display. */ 3111 xf86CollectOptions(pScrn, NULL); 3112 if (!(info->Options = malloc(sizeof(RADEONOptions)))) 3113 goto fail; 3114 3115 memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); 3116 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 3117 3118 /* By default, don't do VGA IOs on ppc/sparc */ 3119 #if defined(__powerpc__) || defined(__sparc__) || !defined(WITH_VGAHW) 3120 info->VGAAccess = FALSE; 3121 #else 3122 info->VGAAccess = TRUE; 3123 #endif 3124 3125 #ifdef WITH_VGAHW 3126 xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess); 3127 if (info->VGAAccess) { 3128 if (!xf86LoadSubModule(pScrn, "vgahw")) 3129 info->VGAAccess = FALSE; 3130 else { 3131 if (!vgaHWGetHWRec(pScrn)) 3132 info->VGAAccess = FALSE; 3133 } 3134 if (!info->VGAAccess) 3135 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed," 3136 " trying to run without it\n"); 3137 } else 3138 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE," 3139 " VGA module load skipped\n"); 3140 if (info->VGAAccess) { 3141 vgaHWSetStdFuncs(VGAHWPTR(pScrn)); 3142 vgaHWGetIOBase(VGAHWPTR(pScrn)); 3143 } 3144 #endif 3145 3146 3147 if (!RADEONPreInitWeight(pScrn)) 3148 goto fail; 3149 3150 info->DispPriority = 1; 3151 if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { 3152 if (strcmp(s, "AUTO") == 0) { 3153 info->DispPriority = 1; 3154 } else if (strcmp(s, "BIOS") == 0) { 3155 info->DispPriority = 0; 3156 } else if (strcmp(s, "HIGH") == 0) { 3157 info->DispPriority = 2; 3158 } else 3159 info->DispPriority = 1; 3160 } 3161 3162 if (!RADEONPreInitChipType(pScrn)) 3163 goto fail; 3164 3165 if (!RADEONPreInitInt10(pScrn, &pInt10)) 3166 goto fail; 3167 3168 RADEONPostInt10Check(pScrn, int10_save); 3169 3170 if (!RADEONPreInitBIOS(pScrn, pInt10)) 3171 goto fail; 3172 3173 /* Save BIOS scratch registers */ 3174 RADEONSaveBIOSRegisters(pScrn, info->SavedReg); 3175 3176 #ifdef XF86DRI 3177 /* PreInit DRI first of all since we need that for getting a proper 3178 * memory map 3179 */ 3180 info->directRenderingEnabled = RADEONPreInitDRI(pScrn); 3181 if (info->directRenderingEnabled < 0) 3182 goto fail; 3183 #endif 3184 if (!info->directRenderingEnabled) { 3185 if (info->ChipFamily >= CHIP_FAMILY_R600) { 3186 info->r600_shadow_fb = TRUE; 3187 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3188 "using shadow framebuffer\n"); 3189 if (!xf86LoadSubModule(pScrn, "shadow")) 3190 info->r600_shadow_fb = FALSE; 3191 } 3192 } 3193 3194 if (!RADEONPreInitVRAM(pScrn)) 3195 goto fail; 3196 3197 RADEONPreInitColorTiling(pScrn); 3198 3199 if (IS_AVIVO_VARIANT) 3200 xf86CrtcSetSizeRange (pScrn, 320, 200, 8192, 8192); 3201 else 3202 xf86CrtcSetSizeRange (pScrn, 320, 200, 4096, 4096); 3203 3204 RADEONPreInitDDC(pScrn); 3205 3206 if (!RADEONPreInitControllers(pScrn)) 3207 goto fail; 3208 3209 if (!xf86InitialConfiguration (pScrn, FALSE)) 3210 { 3211 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n"); 3212 goto fail; 3213 } 3214 3215 /* fix up cloning on rn50 cards 3216 * since they only have one crtc sometimes the xserver doesn't assign 3217 * a crtc to one of the outputs even though both outputs have common modes 3218 * which results in only one monitor being enabled. Assign a crtc here so 3219 * that both outputs light up. 3220 */ 3221 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 3222 int i; 3223 3224 for (i = 0; i < xf86_config->num_output; i++) { 3225 xf86OutputPtr output = xf86_config->output[i]; 3226 3227 /* XXX: double check crtc mode */ 3228 if ((output->probed_modes != NULL) && (output->crtc == NULL)) 3229 output->crtc = xf86_config->crtc[0]; 3230 } 3231 } 3232 3233 RADEONSetPitch(pScrn); 3234 3235 /* Set display resolution */ 3236 xf86SetDpi(pScrn, 0, 0); 3237 3238 /* Get ScreenInit function */ 3239 if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; 3240 3241 if (!RADEONPreInitGamma(pScrn)) goto fail; 3242 3243 if (!RADEONPreInitCursor(pScrn)) goto fail; 3244 3245 if (!RADEONPreInitAccel(pScrn)) goto fail; 3246 3247 if (!IS_AVIVO_VARIANT) { 3248 if (!RADEONPreInitXv(pScrn)) goto fail; 3249 } 3250 3251 if (!xf86RandR12PreInit (pScrn)) 3252 { 3253 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n"); 3254 goto fail; 3255 } 3256 3257 if (pScrn->modes == NULL) { 3258 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 3259 goto fail; 3260 } 3261 3262 3263 /* Free int10 info */ 3264 if (pInt10) 3265 xf86FreeInt10(pInt10); 3266 3267 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3268 info->MMIO = NULL; 3269 3270 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, 3271 "MergedFB support has been removed and replaced with" 3272 " xrandr 1.2 support\n"); 3273 3274 return TRUE; 3275 3276 fail: 3277 /* Pre-init failed. */ 3278 /* Free the video bios (if applicable) */ 3279 if (info->VBIOS) { 3280 free(info->VBIOS); 3281 info->VBIOS = NULL; 3282 } 3283 3284 /* Free int10 info */ 3285 if (pInt10) 3286 xf86FreeInt10(pInt10); 3287 3288 #ifdef WITH_VGAHW 3289 if (info->VGAAccess) 3290 vgaHWFreeHWRec(pScrn); 3291 #endif 3292 3293 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3294 info->MMIO = NULL; 3295 3296 fail1: 3297 RADEONFreeRec(pScrn); 3298 3299 return FALSE; 3300 } 3301 3302 /* Load a palette */ 3303 static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, 3304 int *indices, LOCO *colors, VisualPtr pVisual) 3305 { 3306 RADEONInfoPtr info = RADEONPTR(pScrn); 3307 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 3308 int i; 3309 int index, j; 3310 uint16_t lut_r[256], lut_g[256], lut_b[256]; 3311 int c; 3312 3313 #ifdef XF86DRI 3314 if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 3315 #endif 3316 3317 if (info->accelOn && pScrn->pScreen) 3318 RADEON_SYNC(info, pScrn); 3319 3320 { 3321 3322 for (c = 0; c < xf86_config->num_crtc; c++) { 3323 xf86CrtcPtr crtc = xf86_config->crtc[c]; 3324 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 3325 3326 for (i = 0 ; i < 256; i++) { 3327 lut_r[i] = radeon_crtc->lut_r[i] << 6; 3328 lut_g[i] = radeon_crtc->lut_g[i] << 6; 3329 lut_b[i] = radeon_crtc->lut_b[i] << 6; 3330 } 3331 3332 switch (info->CurrentLayout.depth) { 3333 case 15: 3334 for (i = 0; i < numColors; i++) { 3335 index = indices[i]; 3336 for (j = 0; j < 8; j++) { 3337 lut_r[index * 8 + j] = colors[index].red << 6; 3338 lut_g[index * 8 + j] = colors[index].green << 6; 3339 lut_b[index * 8 + j] = colors[index].blue << 6; 3340 } 3341 } 3342 case 16: 3343 for (i = 0; i < numColors; i++) { 3344 index = indices[i]; 3345 3346 if (i <= 31) { 3347 for (j = 0; j < 8; j++) { 3348 lut_r[index * 8 + j] = colors[index].red << 6; 3349 lut_b[index * 8 + j] = colors[index].blue << 6; 3350 } 3351 } 3352 3353 for (j = 0; j < 4; j++) { 3354 lut_g[index * 4 + j] = colors[index].green << 6; 3355 } 3356 } 3357 default: 3358 for (i = 0; i < numColors; i++) { 3359 index = indices[i]; 3360 lut_r[index] = colors[index].red << 6; 3361 lut_g[index] = colors[index].green << 6; 3362 lut_b[index] = colors[index].blue << 6; 3363 } 3364 break; 3365 } 3366 3367 /* Make the change through RandR */ 3368 #ifdef RANDR_12_INTERFACE 3369 if (crtc->randr_crtc) 3370 RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); 3371 else 3372 #endif 3373 crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); 3374 } 3375 } 3376 3377 #ifdef XF86DRI 3378 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 3379 #endif 3380 } 3381 3382 static void RADEONBlockHandler(BLOCKHANDLER_ARGS_DECL) 3383 { 3384 SCREEN_PTR(arg); 3385 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 3386 RADEONInfoPtr info = RADEONPTR(pScrn); 3387 3388 pScreen->BlockHandler = info->BlockHandler; 3389 (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); 3390 pScreen->BlockHandler = RADEONBlockHandler; 3391 3392 if (info->VideoTimerCallback) 3393 (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); 3394 3395 #if defined(RENDER) && defined(USE_XAA) 3396 if(info->accel_state->RenderCallback) 3397 (*info->accel_state->RenderCallback)(pScrn); 3398 #endif 3399 3400 #ifdef USE_EXA 3401 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 3402 #endif 3403 3404 if (info->pm.dynamic_mode_enabled) 3405 RADEONPMBlockHandler(pScrn); 3406 } 3407 3408 static void 3409 RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) 3410 { 3411 RADEONInfoPtr info = RADEONPTR(pScrn); 3412 unsigned char *RADEONMMIO = info->MMIO; 3413 RADEONSavePtr save = info->ModeReg; 3414 3415 save->bios_0_scratch = info->SavedReg->bios_0_scratch; 3416 save->bios_1_scratch = info->SavedReg->bios_1_scratch; 3417 save->bios_2_scratch = info->SavedReg->bios_2_scratch; 3418 save->bios_3_scratch = info->SavedReg->bios_3_scratch; 3419 save->bios_4_scratch = info->SavedReg->bios_4_scratch; 3420 save->bios_5_scratch = info->SavedReg->bios_5_scratch; 3421 save->bios_6_scratch = info->SavedReg->bios_6_scratch; 3422 save->bios_7_scratch = info->SavedReg->bios_7_scratch; 3423 3424 if (info->IsAtomBios) { 3425 /* let the bios control the backlight */ 3426 save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 3427 /* tell the bios not to handle mode switching */ 3428 save->bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | 3429 ATOM_S6_ACC_MODE); 3430 3431 if (info->ChipFamily >= CHIP_FAMILY_R600) { 3432 OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); 3433 OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch); 3434 } else { 3435 OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch); 3436 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3437 } 3438 } else { 3439 /* let the bios control the backlight */ 3440 save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3441 /* tell the bios not to handle mode switching */ 3442 save->bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3443 RADEON_ACC_MODE_CHANGE); 3444 /* tell the bios a driver is loaded */ 3445 save->bios_7_scratch |= RADEON_DRV_LOADED; 3446 3447 OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch); 3448 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3449 //OUTREG(RADEON_BIOS_7_SCRATCH, save->bios_7_scratch); 3450 } 3451 3452 } 3453 3454 3455 /* Called at the start of each server generation. */ 3456 Bool RADEONScreenInit(SCREEN_INIT_ARGS_DECL) 3457 { 3458 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 3459 RADEONInfoPtr info = RADEONPTR(pScrn); 3460 int hasDRI = 0; 3461 #ifdef RENDER 3462 int subPixelOrder = SubPixelUnknown; 3463 const char* s; 3464 #endif 3465 3466 3467 info->accelOn = FALSE; 3468 #ifdef USE_XAA 3469 info->accel_state->accel = NULL; 3470 #endif 3471 #ifdef XF86DRI 3472 pScrn->fbOffset = info->dri->frontOffset; 3473 #endif 3474 3475 if (info->IsSecondary) 3476 pScrn->fbOffset = pScrn->videoRam * 1024; 3477 #ifdef XF86DRI 3478 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3479 "RADEONScreenInit %lx %ld %d\n", 3480 pScrn->memPhysBase, pScrn->fbOffset, info->dri->frontOffset); 3481 #else 3482 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3483 "RADEONScreenInit %lx %ld\n", 3484 pScrn->memPhysBase, pScrn->fbOffset); 3485 #endif 3486 if (!RADEONMapMem(pScrn)) return FALSE; 3487 3488 #ifdef XF86DRI 3489 info->dri->fbX = 0; 3490 info->dri->fbY = 0; 3491 #endif 3492 3493 info->PaletteSavedOnVT = FALSE; 3494 3495 info->crtc_on = FALSE; 3496 info->crtc2_on = FALSE; 3497 3498 /* save the real front buffer size 3499 * it changes with randr, rotation, etc. 3500 */ 3501 info->virtualX = pScrn->virtualX; 3502 info->virtualY = pScrn->virtualY; 3503 3504 RADEONSave(pScrn); 3505 3506 /* set initial bios scratch reg state */ 3507 RADEONInitBIOSRegisters(pScrn); 3508 3509 /* blank the outputs/crtcs */ 3510 RADEONBlank(pScrn); 3511 3512 RADEONPMInit(pScrn); 3513 3514 if (info->allowColorTiling && (pScrn->virtualX > info->MaxSurfaceWidth)) { 3515 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3516 "Color tiling not supported with virtual x resolutions larger than %d, disabling\n", 3517 info->MaxSurfaceWidth); 3518 info->allowColorTiling = FALSE; 3519 } 3520 if (info->allowColorTiling) { 3521 info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 3522 } 3523 3524 /* Visual setup */ 3525 miClearVisualTypes(); 3526 if (!miSetVisualTypes(pScrn->depth, 3527 miGetDefaultVisualMask(pScrn->depth), 3528 pScrn->rgbBits, 3529 pScrn->defaultVisual)) return FALSE; 3530 miSetPixmapDepths (); 3531 3532 #ifdef XF86DRI 3533 if (info->directRenderingEnabled) { 3534 MessageType from; 3535 3536 info->dri->depthBits = pScrn->depth; 3537 3538 from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS, 3539 &info->dri->depthBits) 3540 ? X_CONFIG : X_DEFAULT; 3541 3542 if (info->dri->depthBits != 16 && info->dri->depthBits != 24) { 3543 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3544 "Value for Option \"DepthBits\" must be 16 or 24\n"); 3545 info->dri->depthBits = pScrn->depth; 3546 from = X_DEFAULT; 3547 } 3548 3549 xf86DrvMsg(pScrn->scrnIndex, from, 3550 "Using %d bit depth buffer\n", info->dri->depthBits); 3551 } 3552 3553 3554 hasDRI = info->directRenderingEnabled; 3555 #endif /* XF86DRI */ 3556 3557 /* Initialize the memory map, this basically calculates the values 3558 * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION 3559 */ 3560 RADEONInitMemoryMap(pScrn); 3561 3562 /* empty the surfaces */ 3563 if (info->ChipFamily < CHIP_FAMILY_R600) { 3564 unsigned char *RADEONMMIO = info->MMIO; 3565 unsigned int j; 3566 for (j = 0; j < 8; j++) { 3567 OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0); 3568 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0); 3569 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0); 3570 } 3571 } 3572 3573 #ifdef XF86DRI 3574 /* Depth moves are disabled by default since they are extremely slow */ 3575 info->dri->depthMoves = xf86ReturnOptValBool(info->Options, 3576 OPTION_DEPTH_MOVE, FALSE); 3577 if (info->dri->depthMoves && info->allowColorTiling) { 3578 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n"); 3579 } else if (info->dri->depthMoves) { 3580 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3581 "Depth moves don't work without color tiling, disabled\n"); 3582 info->dri->depthMoves = FALSE; 3583 } else { 3584 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3585 "Depth moves disabled by default\n"); 3586 } 3587 #endif 3588 3589 /* Initial setup of surfaces */ 3590 if (info->ChipFamily < CHIP_FAMILY_R600) { 3591 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3592 "Setting up initial surfaces\n"); 3593 RADEONChangeSurfaces(pScrn); 3594 } 3595 3596 /* Memory manager setup */ 3597 3598 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3599 "Setting up accel memmap\n"); 3600 3601 #ifdef USE_EXA 3602 if (info->useEXA) { 3603 #ifdef XF86DRI 3604 if (hasDRI) { 3605 info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS, 3606 info->cardType != CARD_AGP); 3607 3608 /* Reserve approx. half of offscreen memory for local textures by 3609 * default, can be overridden with Option "FBTexPercent". 3610 * Round down to a whole number of texture regions. 3611 */ 3612 info->dri->textureSize = 50; 3613 3614 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3615 &(info->dri->textureSize))) { 3616 if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { 3617 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3618 "Illegal texture memory percentage: %dx, setting to default 50%%\n", 3619 info->dri->textureSize); 3620 info->dri->textureSize = 50; 3621 } 3622 } 3623 } 3624 #endif /* XF86DRI */ 3625 3626 if (!RADEONSetupMemEXA(pScreen)) 3627 return FALSE; 3628 } 3629 #endif 3630 3631 #if defined(XF86DRI) && defined(USE_XAA) 3632 if (!info->useEXA && hasDRI) { 3633 info->dri->textureSize = -1; 3634 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3635 &(info->dri->textureSize))) { 3636 if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { 3637 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3638 "Illegal texture memory percentage: %dx, using default behaviour\n", 3639 info->dri->textureSize); 3640 info->dri->textureSize = -1; 3641 } 3642 } 3643 if (!RADEONSetupMemXAA_DRI(pScreen)) 3644 return FALSE; 3645 pScrn->fbOffset = info->dri->frontOffset; 3646 } 3647 #endif 3648 3649 #ifdef USE_XAA 3650 if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(pScreen)) 3651 return FALSE; 3652 #endif 3653 3654 info->accel_state->dst_pitch_offset = 3655 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 3656 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 3657 3658 /* Setup DRI after visuals have been established, but before fbScreenInit is 3659 * called. fbScreenInit will eventually call the driver's InitGLXVisuals 3660 * call back. */ 3661 #ifdef XF86DRI 3662 if (info->directRenderingEnabled) { 3663 /* FIXME: When we move to dynamic allocation of back and depth 3664 * buffers, we will want to revisit the following check for 3 3665 * times the virtual size of the screen below. 3666 */ 3667 int width_bytes = (pScrn->displayWidth * 3668 info->CurrentLayout.pixel_bytes); 3669 int maxy = info->FbMapSize / width_bytes; 3670 3671 if (maxy <= pScrn->virtualY * 3) { 3672 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3673 "Static buffer allocation failed. Disabling DRI.\n"); 3674 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3675 "At least %d kB of video memory needed at this " 3676 "resolution and depth.\n", 3677 (pScrn->displayWidth * pScrn->virtualY * 3678 info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); 3679 info->directRenderingEnabled = FALSE; 3680 } else { 3681 info->directRenderingEnabled = RADEONDRIScreenInit(pScreen); 3682 } 3683 } 3684 3685 /* Tell DRI about new memory map */ 3686 if (info->directRenderingEnabled && info->dri->newMemoryMap) { 3687 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) { 3688 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3689 "[drm] failed to enable new memory map\n"); 3690 RADEONDRICloseScreen(pScreen); 3691 info->directRenderingEnabled = FALSE; 3692 } 3693 } 3694 #endif 3695 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3696 "Initializing fb layer\n"); 3697 3698 if (info->r600_shadow_fb) { 3699 info->fb_shadow = calloc(1, 3700 pScrn->displayWidth * pScrn->virtualY * 3701 ((pScrn->bitsPerPixel + 7) >> 3)); 3702 if (info->fb_shadow == NULL) { 3703 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3704 "Failed to allocate shadow framebuffer\n"); 3705 info->r600_shadow_fb = FALSE; 3706 } else { 3707 if (!fbScreenInit(pScreen, info->fb_shadow, 3708 pScrn->virtualX, pScrn->virtualY, 3709 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3710 pScrn->bitsPerPixel)) 3711 return FALSE; 3712 } 3713 } 3714 3715 if (info->r600_shadow_fb == FALSE) { 3716 /* Init fb layer */ 3717 if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset, 3718 pScrn->virtualX, pScrn->virtualY, 3719 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3720 pScrn->bitsPerPixel)) 3721 return FALSE; 3722 } 3723 3724 xf86SetBlackWhitePixels(pScreen); 3725 3726 if (pScrn->bitsPerPixel > 8) { 3727 VisualPtr visual; 3728 3729 visual = pScreen->visuals + pScreen->numVisuals; 3730 while (--visual >= pScreen->visuals) { 3731 if ((visual->class | DynamicClass) == DirectColor) { 3732 visual->offsetRed = pScrn->offset.red; 3733 visual->offsetGreen = pScrn->offset.green; 3734 visual->offsetBlue = pScrn->offset.blue; 3735 visual->redMask = pScrn->mask.red; 3736 visual->greenMask = pScrn->mask.green; 3737 visual->blueMask = pScrn->mask.blue; 3738 } 3739 } 3740 } 3741 3742 /* Must be after RGB order fixed */ 3743 fbPictureInit (pScreen, 0, 0); 3744 3745 #ifdef RENDER 3746 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 3747 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 3748 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 3749 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 3750 PictureSetSubpixelOrder (pScreen, subPixelOrder); 3751 } 3752 #endif 3753 3754 pScrn->vtSema = TRUE; 3755 3756 /* restore the memory map here otherwise we may get a hang when 3757 * initializing the drm below 3758 */ 3759 RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); 3760 RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); 3761 3762 /* Backing store setup */ 3763 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3764 "Initializing backing store\n"); 3765 xf86SetBackingStore(pScreen); 3766 3767 /* DRI finalisation */ 3768 #ifdef XF86DRI 3769 if (info->directRenderingEnabled && 3770 (info->cardType==CARD_PCIE || info->cardType==CARD_PCI) && 3771 info->dri->pKernelDRMVersion->version_minor >= 19) 3772 { 3773 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0) 3774 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3775 "[drm] failed set pci gart location\n"); 3776 3777 if (info->dri->pKernelDRMVersion->version_minor >= 26) { 3778 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->dri->pciGartSize) < 0) 3779 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3780 "[drm] failed set pci gart table size\n"); 3781 } 3782 } 3783 if (info->directRenderingEnabled) { 3784 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3785 "DRI Finishing init !\n"); 3786 info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); 3787 } 3788 if (info->directRenderingEnabled) { 3789 /* DRI final init might have changed the memory map, we need to adjust 3790 * our local image to make sure we restore them properly on mode 3791 * changes or VT switches 3792 */ 3793 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 3794 3795 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 3796 3797 /* we might already be in tiled mode, tell drm about it */ 3798 if (info->directRenderingEnabled && info->tilingEnabled) { 3799 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 3800 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3801 "[drm] failed changing tiling status\n"); 3802 } 3803 } else { 3804 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3805 "Direct rendering disabled\n"); 3806 } 3807 #endif 3808 3809 /* Make sure surfaces are allright since DRI setup may have changed them */ 3810 if (info->ChipFamily < CHIP_FAMILY_R600) { 3811 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3812 "Setting up final surfaces\n"); 3813 3814 RADEONChangeSurfaces(pScrn); 3815 } 3816 3817 3818 /* Enable aceleration */ 3819 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 3820 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3821 "Initializing Acceleration\n"); 3822 if (RADEONAccelInit(pScreen)) { 3823 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n"); 3824 info->accelOn = TRUE; 3825 } else { 3826 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3827 "Acceleration initialization failed\n"); 3828 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 3829 info->accelOn = FALSE; 3830 } 3831 } else { 3832 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 3833 info->accelOn = FALSE; 3834 } 3835 3836 /* Init DPMS */ 3837 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3838 "Initializing DPMS\n"); 3839 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 3840 3841 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3842 "Initializing Cursor\n"); 3843 3844 /* Set Silken Mouse */ 3845 xf86SetSilkenMouse(pScreen); 3846 3847 /* Cursor setup */ 3848 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 3849 3850 /* Hardware cursor setup */ 3851 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 3852 if (RADEONCursorInit(pScreen)) { 3853 #ifdef USE_XAA 3854 if (!info->useEXA) { 3855 int width, height; 3856 3857 if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, 3858 0, 0, 0)) { 3859 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3860 "Largest offscreen area available: %d x %d\n", 3861 width, height); 3862 } 3863 } 3864 #endif /* USE_XAA */ 3865 } else { 3866 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3867 "Hardware cursor initialization failed\n"); 3868 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using software cursor\n"); 3869 } 3870 } else { 3871 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using software cursor\n"); 3872 } 3873 3874 /* DGA setup */ 3875 #ifdef XFreeXDGA 3876 xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); 3877 #endif 3878 3879 /* Init Xv */ 3880 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3881 "Initializing Xv\n"); 3882 RADEONInitVideo(pScreen); 3883 3884 if (info->r600_shadow_fb == TRUE) { 3885 if (!shadowSetup(pScreen)) { 3886 return FALSE; 3887 } 3888 } 3889 3890 /* Clear the framebuffer */ 3891 memset(info->FB + pScrn->fbOffset, 0, 3892 pScrn->virtualY * pScrn->displayWidth * info->CurrentLayout.pixel_bytes); 3893 3894 pScrn->pScreen = pScreen; 3895 3896 /* set the modes with desired rotation, etc. */ 3897 if (!xf86SetDesiredModes (pScrn)) 3898 return FALSE; 3899 3900 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 3901 /* Wrap CloseScreen */ 3902 info->CloseScreen = pScreen->CloseScreen; 3903 pScreen->CloseScreen = RADEONCloseScreen; 3904 pScreen->SaveScreen = RADEONSaveScreen; 3905 info->BlockHandler = pScreen->BlockHandler; 3906 pScreen->BlockHandler = RADEONBlockHandler; 3907 info->CreateScreenResources = pScreen->CreateScreenResources; 3908 pScreen->CreateScreenResources = RADEONCreateScreenResources; 3909 3910 if (!xf86CrtcScreenInit (pScreen)) 3911 return FALSE; 3912 3913 /* Colormap setup */ 3914 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3915 "Initializing color map\n"); 3916 if (!miCreateDefColormap(pScreen)) return FALSE; 3917 /* all radeons support 10 bit CLUTs */ 3918 if (!xf86HandleColormaps(pScreen, 256, 10, 3919 RADEONLoadPalette, NULL, 3920 CMAP_PALETTED_TRUECOLOR 3921 #if 0 /* This option messes up text mode! (eich (at) suse.de) */ 3922 | CMAP_LOAD_EVEN_IF_OFFSCREEN 3923 #endif 3924 | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; 3925 3926 /* Note unused options */ 3927 if (serverGeneration == 1) 3928 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 3929 3930 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3931 "RADEONScreenInit finished\n"); 3932 3933 return TRUE; 3934 } 3935 3936 /* Write memory mapping registers */ 3937 void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 3938 RADEONSavePtr restore) 3939 { 3940 RADEONInfoPtr info = RADEONPTR(pScrn); 3941 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 3942 unsigned char *RADEONMMIO = info->MMIO; 3943 int timeout; 3944 uint32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; 3945 3946 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, 3947 &mc_agp_loc, &mc_agp_loc_hi); 3948 3949 if (info->IsSecondary) 3950 return; 3951 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3952 "RADEONRestoreMemMapRegisters() : \n"); 3953 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3954 " MC_FB_LOCATION : 0x%08x 0x%08x\n", 3955 (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc); 3956 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3957 " MC_AGP_LOCATION : 0x%08x\n", 3958 (unsigned)restore->mc_agp_location); 3959 3960 if (IS_DCE4_VARIANT) { 3961 if (mc_fb_loc != restore->mc_fb_location || 3962 mc_agp_loc != restore->mc_agp_location) { 3963 uint32_t tmp; 3964 3965 //XXX 3966 //RADEONWaitForIdleMMIO(pScrn); 3967 3968 /* disable VGA rendering core */ 3969 OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) & ~AVIVO_VGA_VSTATUS_CNTL_MASK); 3970 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3971 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3972 OUTREG(EVERGREEN_D3VGA_CONTROL, INREG(EVERGREEN_D3VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3973 OUTREG(EVERGREEN_D4VGA_CONTROL, INREG(EVERGREEN_D4VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3974 OUTREG(EVERGREEN_D5VGA_CONTROL, INREG(EVERGREEN_D5VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3975 OUTREG(EVERGREEN_D6VGA_CONTROL, INREG(EVERGREEN_D6VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3976 3977 /* Stop display & memory access */ 3978 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 3979 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3980 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 3981 3982 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 3983 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3984 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 3985 3986 if (!IS_DCE41_VARIANT) { 3987 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 3988 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3989 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 3990 3991 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 3992 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3993 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 3994 3995 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 3996 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3997 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 3998 3999 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 4000 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 4001 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 4002 } 4003 4004 usleep(10000); 4005 timeout = 0; 4006 while (!(radeon_get_mc_idle(pScrn))) { 4007 if (++timeout > 1000000) { 4008 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4009 "Timeout trying to update memory controller settings !\n"); 4010 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4011 "You will probably crash now ... \n"); 4012 /* Nothing we can do except maybe try to kill the server, 4013 * let's wait 2 seconds to leave the above message a chance 4014 * to maybe hit the disk and continue trying to setup despite 4015 * the MC being non-idle 4016 */ 4017 usleep(2000000); 4018 } 4019 usleep(10); 4020 } 4021 4022 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, 4023 restore->mc_fb_location, 4024 restore->mc_agp_location, 4025 restore->mc_agp_location_hi); 4026 4027 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location & 0xffff) << 16); 4028 4029 } 4030 } else if (IS_AVIVO_VARIANT) { 4031 if (mc_fb_loc != restore->mc_fb_location || 4032 mc_agp_loc != restore->mc_agp_location) { 4033 uint32_t tmp; 4034 4035 RADEONWaitForIdleMMIO(pScrn); 4036 4037 /* disable VGA rendering core */ 4038 OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) &~ AVIVO_VGA_VSTATUS_CNTL_MASK); 4039 4040 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 4041 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 4042 4043 /* Stop display & memory access */ 4044 tmp = INREG(AVIVO_D1CRTC_CONTROL); 4045 OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 4046 4047 tmp = INREG(AVIVO_D2CRTC_CONTROL); 4048 OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 4049 4050 tmp = INREG(AVIVO_D2CRTC_CONTROL); 4051 4052 usleep(10000); 4053 timeout = 0; 4054 while (!(radeon_get_mc_idle(pScrn))) { 4055 if (++timeout > 1000000) { 4056 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4057 "Timeout trying to update memory controller settings !\n"); 4058 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4059 "You will probably crash now ... \n"); 4060 /* Nothing we can do except maybe try to kill the server, 4061 * let's wait 2 seconds to leave the above message a chance 4062 * to maybe hit the disk and continue trying to setup despite 4063 * the MC being non-idle 4064 */ 4065 usleep(2000000); 4066 } 4067 usleep(10); 4068 } 4069 4070 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, 4071 restore->mc_fb_location, 4072 restore->mc_agp_location, 4073 restore->mc_agp_location_hi); 4074 4075 if (info->ChipFamily < CHIP_FAMILY_R600) { 4076 OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location); 4077 } else { 4078 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000); 4079 } 4080 4081 /* Reset the engine and HDP */ 4082 if (info->ChipFamily < CHIP_FAMILY_R600) 4083 RADEONEngineReset(pScrn); 4084 } 4085 } else { 4086 4087 /* Write memory mapping registers only if their value change 4088 * since we must ensure no access is done while they are 4089 * reprogrammed 4090 */ 4091 if (mc_fb_loc != restore->mc_fb_location || 4092 mc_agp_loc != restore->mc_agp_location) { 4093 uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; 4094 uint32_t old_mc_status; 4095 4096 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4097 " Map Changed ! Applying ...\n"); 4098 4099 /* Make sure engine is idle. We assume the CCE is stopped 4100 * at this point 4101 */ 4102 RADEONWaitForIdleMMIO(pScrn); 4103 4104 if (info->IsIGP) 4105 goto igp_no_mcfb; 4106 4107 /* Capture MC_STATUS in case things go wrong ... */ 4108 old_mc_status = INREG(RADEON_MC_STATUS); 4109 4110 /* Stop display & memory access */ 4111 ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); 4112 OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); 4113 crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 4114 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); 4115 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 4116 RADEONWaitForVerticalSync(pScrn); 4117 OUTREG(RADEON_CRTC_GEN_CNTL, 4118 (crtc_gen_cntl 4119 & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) 4120 | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); 4121 4122 if (pRADEONEnt->HasCRTC2) { 4123 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 4124 RADEONWaitForVerticalSync2(pScrn); 4125 OUTREG(RADEON_CRTC2_GEN_CNTL, 4126 (crtc2_gen_cntl 4127 & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) 4128 | RADEON_CRTC2_DISP_REQ_EN_B); 4129 } 4130 4131 /* Make sure the chip settles down (paranoid !) */ 4132 usleep(100000); 4133 timeout = 0; 4134 while (!(radeon_get_mc_idle(pScrn))) { 4135 if (++timeout > 1000000) { 4136 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4137 "Timeout trying to update memory controller settings !\n"); 4138 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4139 "MC_STATUS = 0x%08x (on entry = 0x%08x)\n", 4140 (unsigned int)INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status); 4141 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4142 "You will probably crash now ... \n"); 4143 /* Nothing we can do except maybe try to kill the server, 4144 * let's wait 2 seconds to leave the above message a chance 4145 * to maybe hit the disk and continue trying to setup despite 4146 * the MC being non-idle 4147 */ 4148 usleep(2000000); 4149 } 4150 usleep(10); 4151 } 4152 4153 /* Update maps, first clearing out AGP to make sure we don't get 4154 * a temporary overlap 4155 */ 4156 OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); 4157 OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); 4158 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location, 4159 0xfffffffc, 0); 4160 igp_no_mcfb: 4161 radeon_write_mc_fb_agp_location(pScrn, LOC_AGP, 0, 4162 restore->mc_agp_location, 0); 4163 /* Make sure map fully reached the chip */ 4164 (void)INREG(RADEON_MC_FB_LOCATION); 4165 4166 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4167 " Map applied, resetting engine ...\n"); 4168 4169 /* Reset the engine and HDP */ 4170 RADEONEngineReset(pScrn); 4171 4172 /* Make sure we have sane offsets before re-enabling the CRTCs, disable 4173 * stereo, clear offsets, and wait for offsets to catch up with hw 4174 */ 4175 4176 OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); 4177 OUTREG(RADEON_CRTC_OFFSET, 0); 4178 OUTREG(RADEON_CUR_OFFSET, 0); 4179 timeout = 0; 4180 while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { 4181 if (timeout++ > 1000000) { 4182 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4183 "Timeout waiting for CRTC offset to update !\n"); 4184 break; 4185 } 4186 usleep(1000); 4187 } 4188 if (pRADEONEnt->HasCRTC2) { 4189 OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); 4190 OUTREG(RADEON_CRTC2_OFFSET, 0); 4191 OUTREG(RADEON_CUR2_OFFSET, 0); 4192 timeout = 0; 4193 while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { 4194 if (timeout++ > 1000000) { 4195 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4196 "Timeout waiting for CRTC2 offset to update !\n"); 4197 break; 4198 } 4199 usleep(1000); 4200 } 4201 } 4202 } 4203 4204 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4205 "Updating display base addresses...\n"); 4206 4207 OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); 4208 if (pRADEONEnt->HasCRTC2) 4209 OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); 4210 OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); 4211 (void)INREG(RADEON_OV0_BASE_ADDR); 4212 4213 /* More paranoia delays, wait 100ms */ 4214 usleep(100000); 4215 4216 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4217 "Memory map updated.\n"); 4218 } 4219 } 4220 4221 #ifdef XF86DRI 4222 static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4223 { 4224 RADEONInfoPtr info = RADEONPTR(pScrn); 4225 uint32_t fb, agp, agp_hi; 4226 int changed = 0; 4227 4228 if (info->IsSecondary) 4229 return; 4230 4231 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi); 4232 4233 if (fb != save->mc_fb_location || agp != save->mc_agp_location || 4234 agp_hi != save->mc_agp_location_hi) 4235 changed = 1; 4236 4237 if (changed) { 4238 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4239 "DRI init changed memory map, adjusting ...\n"); 4240 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4241 " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n", 4242 (long unsigned int)info->mc_fb_location, (long unsigned int)fb); 4243 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4244 " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n", 4245 (long unsigned int)info->mc_agp_location, (long unsigned int)agp); 4246 info->mc_fb_location = fb; 4247 info->mc_agp_location = agp; 4248 if (info->ChipFamily >= CHIP_FAMILY_R600) 4249 info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 24; 4250 else 4251 info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 16; 4252 4253 info->accel_state->dst_pitch_offset = 4254 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 4255 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 4256 RADEONInitMemMapRegisters(pScrn, save, info); 4257 RADEONRestoreMemMapRegisters(pScrn, save); 4258 } 4259 4260 #ifdef USE_EXA 4261 if (info->accelDFS || (info->ChipFamily >= CHIP_FAMILY_R600)) 4262 { 4263 drm_radeon_getparam_t gp; 4264 int gart_base; 4265 4266 memset(&gp, 0, sizeof(gp)); 4267 gp.param = RADEON_PARAM_GART_BASE; 4268 gp.value = &gart_base; 4269 4270 if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &gp, 4271 sizeof(gp)) < 0) { 4272 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4273 "Failed to determine GART area MC location, not using " 4274 "accelerated DownloadFromScreen hook!\n"); 4275 info->accelDFS = FALSE; 4276 } else { 4277 info->gartLocation = gart_base; 4278 } 4279 } 4280 #endif /* USE_EXA */ 4281 } 4282 #endif 4283 4284 /* restore original surface info (for fb console). */ 4285 static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4286 { 4287 RADEONInfoPtr info = RADEONPTR(pScrn); 4288 unsigned char *RADEONMMIO = info->MMIO; 4289 unsigned int surfnr; 4290 4291 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 4292 OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]); 4293 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]); 4294 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr, restore->surfaces[surfnr][2]); 4295 } 4296 } 4297 4298 /* save original surface info (for fb console). */ 4299 static void RADEONSaveSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr save) 4300 { 4301 RADEONInfoPtr info = RADEONPTR(pScrn); 4302 unsigned char *RADEONMMIO = info->MMIO; 4303 unsigned int surfnr; 4304 4305 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 4306 save->surfaces[surfnr][0] = INREG(RADEON_SURFACE0_INFO + 16 * surfnr); 4307 save->surfaces[surfnr][1] = INREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr); 4308 save->surfaces[surfnr][2] = INREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr); 4309 } 4310 } 4311 4312 void RADEONChangeSurfaces(ScrnInfoPtr pScrn) 4313 { 4314 /* the idea here is to only set up front buffer as tiled, and back/depth buffer when needed. 4315 Everything else is left as untiled. This means we need to use eplicit src/dst pitch control 4316 when blitting, based on the src/target address, and can no longer use a default offset. 4317 But OTOH we don't need to dynamically change surfaces (for xv for instance), and some 4318 ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works... 4319 For simplicity, just always update everything (just let the ioctl fail - could do better). 4320 All surface addresses are relative to RADEON_MC_FB_LOCATION */ 4321 4322 RADEONInfoPtr info = RADEONPTR(pScrn); 4323 int cpp = info->CurrentLayout.pixel_bytes; 4324 /* depth/front/back pitch must be identical (and the same as displayWidth) */ 4325 int width_bytes = pScrn->displayWidth * cpp; 4326 int bufferSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * width_bytes, 4327 RADEON_GPU_PAGE_SIZE); 4328 unsigned int color_pattern, swap_pattern; 4329 4330 if (!info->allowColorTiling) 4331 return; 4332 4333 swap_pattern = 0; 4334 #if X_BYTE_ORDER == X_BIG_ENDIAN 4335 switch (pScrn->bitsPerPixel) { 4336 case 16: 4337 swap_pattern = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 4338 break; 4339 4340 case 32: 4341 swap_pattern = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 4342 break; 4343 } 4344 #endif 4345 if (info->ChipFamily < CHIP_FAMILY_R200) { 4346 color_pattern = RADEON_SURF_TILE_COLOR_MACRO; 4347 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4348 color_pattern = R300_SURF_TILE_COLOR_MACRO; 4349 } else { 4350 color_pattern = R200_SURF_TILE_COLOR_MACRO; 4351 } 4352 #ifdef XF86DRI 4353 if (info->directRenderingInited) { 4354 drm_radeon_surface_free_t drmsurffree; 4355 drm_radeon_surface_alloc_t drmsurfalloc; 4356 int retvalue; 4357 int depthCpp = (info->dri->depthBits - 8) / 4; 4358 int depth_width_bytes = pScrn->displayWidth * depthCpp; 4359 int depthBufferSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * depth_width_bytes, 4360 RADEON_GPU_PAGE_SIZE); 4361 unsigned int depth_pattern; 4362 4363 drmsurffree.address = info->dri->frontOffset; 4364 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4365 &drmsurffree, sizeof(drmsurffree)); 4366 4367 if (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4368 (info->ChipFamily == CHIP_FAMILY_RS100) || 4369 (info->ChipFamily == CHIP_FAMILY_RS200))) { 4370 drmsurffree.address = info->dri->depthOffset; 4371 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4372 &drmsurffree, sizeof(drmsurffree)); 4373 } 4374 4375 if (!info->dri->noBackBuffer) { 4376 drmsurffree.address = info->dri->backOffset; 4377 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4378 &drmsurffree, sizeof(drmsurffree)); 4379 } 4380 4381 drmsurfalloc.size = bufferSize; 4382 drmsurfalloc.address = info->dri->frontOffset; 4383 drmsurfalloc.flags = swap_pattern; 4384 4385 if (info->tilingEnabled) { 4386 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4387 drmsurfalloc.flags |= (width_bytes / 8) | color_pattern; 4388 else 4389 drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; 4390 } 4391 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4392 &drmsurfalloc, sizeof(drmsurfalloc)); 4393 if (retvalue < 0) 4394 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4395 "drm: could not allocate surface for front buffer!\n"); 4396 4397 if ((info->dri->have3DWindows) && (!info->dri->noBackBuffer)) { 4398 drmsurfalloc.address = info->dri->backOffset; 4399 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4400 &drmsurfalloc, sizeof(drmsurfalloc)); 4401 if (retvalue < 0) 4402 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4403 "drm: could not allocate surface for back buffer!\n"); 4404 } 4405 4406 if (info->ChipFamily < CHIP_FAMILY_R200) { 4407 if (depthCpp == 2) 4408 depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; 4409 else 4410 depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; 4411 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4412 if (depthCpp == 2) 4413 depth_pattern = R300_SURF_TILE_COLOR_MACRO; 4414 else 4415 depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP; 4416 } else { 4417 if (depthCpp == 2) 4418 depth_pattern = R200_SURF_TILE_DEPTH_16BPP; 4419 else 4420 depth_pattern = R200_SURF_TILE_DEPTH_32BPP; 4421 } 4422 4423 /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ 4424 if (info->dri->have3DWindows && 4425 (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4426 (info->ChipFamily == CHIP_FAMILY_RS100) || 4427 (info->ChipFamily == CHIP_FAMILY_RS200)))) { 4428 drm_radeon_surface_alloc_t drmsurfalloc; 4429 drmsurfalloc.size = depthBufferSize; 4430 drmsurfalloc.address = info->dri->depthOffset; 4431 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4432 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern; 4433 else 4434 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern; 4435 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4436 &drmsurfalloc, sizeof(drmsurfalloc)); 4437 if (retvalue < 0) 4438 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4439 "drm: could not allocate surface for depth buffer!\n"); 4440 } 4441 } 4442 else 4443 #endif 4444 { 4445 unsigned int surf_info = swap_pattern; 4446 unsigned char *RADEONMMIO = info->MMIO; 4447 /* we don't need anything like WaitForFifo, no? */ 4448 if (info->tilingEnabled) { 4449 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4450 surf_info |= (width_bytes / 8) | color_pattern; 4451 else 4452 surf_info |= (width_bytes / 16) | color_pattern; 4453 } 4454 OUTREG(RADEON_SURFACE0_INFO, surf_info); 4455 OUTREG(RADEON_SURFACE0_LOWER_BOUND, 0); 4456 OUTREG(RADEON_SURFACE0_UPPER_BOUND, bufferSize - 1); 4457 /* xf86DrvMsg(pScrn->scrnIndex, X_INFO, 4458 "surface0 set to %x, LB 0x%x UB 0x%x\n", 4459 surf_info, 0, bufferSize - 1024);*/ 4460 } 4461 4462 /* Update surface images */ 4463 if (info->ChipFamily < CHIP_FAMILY_R600) 4464 RADEONSaveSurfaces(pScrn, info->ModeReg); 4465 } 4466 4467 /* Read memory map */ 4468 static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4469 { 4470 RADEONInfoPtr info = RADEONPTR(pScrn); 4471 unsigned char *RADEONMMIO = info->MMIO; 4472 4473 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location, 4474 &save->mc_agp_location, &save->mc_agp_location_hi); 4475 4476 if (!IS_AVIVO_VARIANT) { 4477 save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); 4478 save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); 4479 save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); 4480 } 4481 } 4482 4483 /* Read palette data */ 4484 static void RADEONSavePalette(ScrnInfoPtr pScrn, int palID, RADEONSavePtr save) 4485 { 4486 RADEONInfoPtr info = RADEONPTR(pScrn); 4487 unsigned char *RADEONMMIO = info->MMIO; 4488 int i; 4489 4490 PAL_SELECT(palID); 4491 INPAL_START(0); 4492 4493 for (i = 0; i < 256; i++) { 4494 save->palette[palID][i] = INREG(RADEON_PALETTE_30_DATA); 4495 } 4496 } 4497 4498 static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4499 { 4500 RADEONInfoPtr info = RADEONPTR(pScrn); 4501 unsigned char *RADEONMMIO = info->MMIO; 4502 int i; 4503 4504 if (restore->palette_saved[1]) { 4505 ErrorF("Restore Palette 2\n"); 4506 PAL_SELECT(1); 4507 OUTPAL_START(0); 4508 for (i = 0; i < 256; i++) { 4509 OUTREG(RADEON_PALETTE_30_DATA, restore->palette[1][i]); 4510 } 4511 } 4512 if (restore->palette_saved[0]) { 4513 ErrorF("Restore Palette 1\n"); 4514 PAL_SELECT(0); 4515 OUTPAL_START(0); 4516 for (i = 0; i < 256; i++) { 4517 OUTREG(RADEON_PALETTE_30_DATA, restore->palette[0][i]); 4518 } 4519 } 4520 } 4521 4522 static void 4523 dce4_save_grph(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4524 uint32_t offset) 4525 { 4526 RADEONInfoPtr info = RADEONPTR(pScrn); 4527 unsigned char *RADEONMMIO = info->MMIO; 4528 4529 state->grph.enable = INREG(offset + EVERGREEN_GRPH_ENABLE); 4530 state->grph.control = INREG(offset + EVERGREEN_GRPH_CONTROL); 4531 state->grph.swap_control = INREG(offset + EVERGREEN_GRPH_SWAP_CONTROL); 4532 state->grph.prim_surf_addr = INREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS); 4533 state->grph.sec_surf_addr = INREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS); 4534 state->grph.pitch = INREG(offset + EVERGREEN_GRPH_PITCH); 4535 state->grph.prim_surf_addr_hi = INREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH); 4536 state->grph.sec_surf_addr_hi = INREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH); 4537 state->grph.x_offset = INREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_X); 4538 state->grph.y_offset = INREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_Y); 4539 state->grph.x_start = INREG(offset + EVERGREEN_GRPH_X_START); 4540 state->grph.y_start = INREG(offset + EVERGREEN_GRPH_Y_START); 4541 state->grph.x_end = INREG(offset + EVERGREEN_GRPH_X_END); 4542 state->grph.y_end = INREG(offset + EVERGREEN_GRPH_Y_END); 4543 4544 state->grph.desktop_height = INREG(offset + EVERGREEN_DESKTOP_HEIGHT); 4545 state->grph.viewport_start = INREG(offset + EVERGREEN_VIEWPORT_START); 4546 state->grph.viewport_size = INREG(offset + EVERGREEN_VIEWPORT_SIZE); 4547 state->grph.mode_data_format = INREG(offset + EVERGREEN_DATA_FORMAT); 4548 } 4549 4550 static void 4551 dce4_restore_grph(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4552 uint32_t offset) 4553 { 4554 RADEONInfoPtr info = RADEONPTR(pScrn); 4555 unsigned char *RADEONMMIO = info->MMIO; 4556 4557 OUTREG(offset + EVERGREEN_GRPH_ENABLE, state->grph.enable); 4558 OUTREG(offset + EVERGREEN_GRPH_CONTROL, state->grph.control); 4559 OUTREG(offset + EVERGREEN_GRPH_SWAP_CONTROL, state->grph.swap_control); 4560 OUTREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS, state->grph.prim_surf_addr); 4561 OUTREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS, state->grph.sec_surf_addr); 4562 OUTREG(offset + EVERGREEN_GRPH_PITCH, state->grph.pitch); 4563 OUTREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, state->grph.prim_surf_addr_hi); 4564 OUTREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, state->grph.sec_surf_addr_hi); 4565 OUTREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_X, state->grph.x_offset); 4566 OUTREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_Y, state->grph.y_offset); 4567 OUTREG(offset + EVERGREEN_GRPH_X_START, state->grph.x_start); 4568 OUTREG(offset + EVERGREEN_GRPH_Y_START, state->grph.y_start); 4569 OUTREG(offset + EVERGREEN_GRPH_X_END, state->grph.x_end); 4570 OUTREG(offset + EVERGREEN_GRPH_Y_END, state->grph.y_end); 4571 4572 OUTREG(offset + EVERGREEN_DESKTOP_HEIGHT, state->grph.desktop_height); 4573 OUTREG(offset + EVERGREEN_VIEWPORT_START, state->grph.viewport_start); 4574 OUTREG(offset + EVERGREEN_VIEWPORT_SIZE, state->grph.viewport_size); 4575 OUTREG(offset + EVERGREEN_DATA_FORMAT, state->grph.mode_data_format); 4576 } 4577 4578 static uint32_t dce4_dac_regs[] = { 4579 0x6690, 0x6694, 0x66b0, 0x66cc, 0x66d0, 0x66d4, 0x66d8 }; 4580 4581 static uint32_t dce4_scl_regs[] = { 4582 0x6d08, 0x6d0c, 0x6d14, 0x6d1c }; 4583 4584 static uint32_t dce4_dig_regs[] = { 4585 0x7000, 0x7004, 0x7008, 0x700c, 0x7010, 0x7014, 4586 0x71f0, 0x71f4, 0x71f8, 0x71fc, 0x7200, 0x7204, 4587 0x7208, 0x720c, 0x7210, 0x7218, 0x721c, 0x7220, 4588 0x7230}; 4589 4590 static uint32_t dce4_crtc_regs[] = { 4591 0x6e00, 0x6e04, 0x6e08, 0x6e0c, 0x6e1c, 0x6e34, 0x6e38, 0x6e3c, 0x6e70, 0x6e74, 0x6e78}; 4592 4593 4594 #define DCE4_REG_SCL_NUM (sizeof(dce4_scl_regs)/sizeof(uint32_t)) 4595 #define DCE4_REG_CRTC_NUM (sizeof(dce4_crtc_regs)/sizeof(uint32_t)) 4596 #define DCE4_REG_DIG_NUM (sizeof(dce4_dig_regs)/sizeof(uint32_t)) 4597 #define DCE4_DAC_NUM (sizeof(dce4_dac_regs)/sizeof(uint32_t)) 4598 4599 4600 static void 4601 dce4_save_crtc(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4602 uint32_t offset) 4603 { 4604 RADEONInfoPtr info = RADEONPTR(pScrn); 4605 unsigned char *RADEONMMIO = info->MMIO; 4606 int i; 4607 4608 for (i = 0; i < DCE4_REG_CRTC_NUM; i++) 4609 state->crtc[i] = INREG(offset + dce4_crtc_regs[i]); 4610 } 4611 4612 static void 4613 dce4_restore_crtc(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4614 uint32_t offset) 4615 { 4616 RADEONInfoPtr info = RADEONPTR(pScrn); 4617 unsigned char *RADEONMMIO = info->MMIO; 4618 int i; 4619 4620 for (i = 0; i < DCE4_REG_CRTC_NUM; i++) 4621 OUTREG(offset + dce4_crtc_regs[i], state->crtc[i]); 4622 } 4623 4624 static void 4625 dce4_save_scl(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4626 uint32_t offset) 4627 { 4628 RADEONInfoPtr info = RADEONPTR(pScrn); 4629 unsigned char *RADEONMMIO = info->MMIO; 4630 int i; 4631 4632 for (i = 0; i < DCE4_REG_SCL_NUM; i++) 4633 state->scl[i] = INREG(offset + dce4_scl_regs[i]); 4634 } 4635 4636 static void 4637 dce4_restore_scl(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4638 uint32_t offset) 4639 { 4640 RADEONInfoPtr info = RADEONPTR(pScrn); 4641 unsigned char *RADEONMMIO = info->MMIO; 4642 int i; 4643 4644 for (i = 0; i < DCE4_REG_SCL_NUM; i++) 4645 OUTREG(offset + dce4_scl_regs[i], state->scl[i]); 4646 } 4647 4648 4649 static void 4650 dce4_save_fmt(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4651 uint32_t offset) 4652 { 4653 RADEONInfoPtr info = RADEONPTR(pScrn); 4654 unsigned char *RADEONMMIO = info->MMIO; 4655 int i, index = 0; 4656 4657 for (i = 0x6fb4; i <= 0x6fd4; i += 4) 4658 state->fmt[index++] = INREG(offset + i); 4659 } 4660 4661 static void 4662 dce4_restore_fmt(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4663 uint32_t offset) 4664 { 4665 RADEONInfoPtr info = RADEONPTR(pScrn); 4666 unsigned char *RADEONMMIO = info->MMIO; 4667 int i, index = 0; 4668 4669 for (i = 0x6fb4; i <= 0x6fd4; i += 4) 4670 OUTREG(offset + i, state->fmt[index++]); 4671 } 4672 4673 4674 static void 4675 dce4_save_dig(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4676 uint32_t offset) 4677 { 4678 RADEONInfoPtr info = RADEONPTR(pScrn); 4679 unsigned char *RADEONMMIO = info->MMIO; 4680 int i; 4681 4682 for (i = 0; i < DCE4_REG_DIG_NUM; i++) 4683 state->dig[i] = INREG(offset + dce4_dig_regs[i]); 4684 } 4685 4686 static void 4687 dce4_restore_dig(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4688 uint32_t offset) 4689 { 4690 RADEONInfoPtr info = RADEONPTR(pScrn); 4691 unsigned char *RADEONMMIO = info->MMIO; 4692 int i; 4693 4694 for (i = 0; i < DCE4_REG_DIG_NUM; i++) 4695 OUTREG(offset + dce4_dig_regs[i], state->dig[i]); 4696 } 4697 4698 4699 4700 static void dce4_save_block(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4701 uint32_t offset) 4702 { 4703 dce4_save_grph(pScrn, state, offset); 4704 dce4_save_crtc(pScrn, state, offset); 4705 dce4_save_scl(pScrn, state, offset); 4706 dce4_save_dig(pScrn, state, offset); 4707 dce4_save_fmt(pScrn, state, offset); 4708 } 4709 4710 static void dce4_restore_block(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, 4711 uint32_t offset) 4712 { 4713 dce4_restore_grph(pScrn, state, offset); 4714 dce4_restore_crtc(pScrn, state, offset); 4715 dce4_restore_scl(pScrn, state, offset); 4716 dce4_restore_dig(pScrn, state, offset); 4717 dce4_restore_fmt(pScrn, state, offset); 4718 } 4719 4720 static void dce4_save_uniphy(ScrnInfoPtr pScrn, struct dce4_state *state, int index) 4721 { 4722 RADEONInfoPtr info = RADEONPTR(pScrn); 4723 unsigned char *RADEONMMIO = info->MMIO; 4724 uint32_t uniphy_offset[6] = {0x0, 0x30, 0x60, 0x100, 0x130, 0x160 }; 4725 int i, ri = 0; 4726 for (i = 0; i < 0x18; i+=4) 4727 state->uniphy[index][ri++] = INREG(0x6600 + uniphy_offset[index] + i); 4728 } 4729 4730 static void dce4_restore_uniphy(ScrnInfoPtr pScrn, struct dce4_state *state, int index) 4731 { 4732 RADEONInfoPtr info = RADEONPTR(pScrn); 4733 unsigned char *RADEONMMIO = info->MMIO; 4734 uint32_t uniphy_offset[6] = {0x0, 0x30, 0x60, 0x100, 0x130, 0x160 }; 4735 int i, ri = 0; 4736 for (i = 0; i <= 0x18; i+=4) 4737 OUTREG(0x6600 + uniphy_offset[index] + i, state->uniphy[index][ri++]); 4738 } 4739 4740 static void dce4_save_dig_regs(ScrnInfoPtr pScrn, struct dce4_state *state) 4741 { 4742 RADEONInfoPtr info = RADEONPTR(pScrn); 4743 unsigned char *RADEONMMIO = info->MMIO; 4744 int i, ri = 0; 4745 4746 for (i = 0x6578; i <= 0x6598; i += 4) 4747 state->dig[ri++] = INREG(i); 4748 for (i = 0x65ac; i <= 0x65d8; i += 4) 4749 state->dig[ri++] = INREG(i); 4750 } 4751 4752 static void dce4_restore_dig_regs(ScrnInfoPtr pScrn, struct dce4_state *state) 4753 { 4754 RADEONInfoPtr info = RADEONPTR(pScrn); 4755 unsigned char *RADEONMMIO = info->MMIO; 4756 int i, ri = 0; 4757 4758 for (i = 0x6578; i <= 0x6598; i += 4) 4759 OUTREG(i, state->dig[ri++]); 4760 for (i = 0x65ac; i <= 0x65d8; i += 4) 4761 OUTREG(i, state->dig[ri++]); 4762 } 4763 4764 static void dce4_save_pll_regs(ScrnInfoPtr pScrn, struct dce4_state *state) 4765 { 4766 RADEONInfoPtr info = RADEONPTR(pScrn); 4767 unsigned char *RADEONMMIO = info->MMIO; 4768 int i, ri = 0; 4769 4770 for (i = 0x360; i <= 0x368; i += 4) 4771 state->vga_pll[0][ri++] = INREG(i); 4772 4773 ri = 0; 4774 for (i = 0x370; i <= 0x378; i += 4) 4775 state->vga_pll[1][ri++] = INREG(i); 4776 4777 ri = 0; 4778 for (i = 0x390; i <= 0x398; i += 4) 4779 state->vga_pll[2][ri++] = INREG(i); 4780 4781 ri = 0; 4782 for (i = 0x400; i <= 0x408; i += 4) 4783 state->pll[0][ri++] = INREG(i); 4784 for (i = 0x410; i <= 0x43c; i += 4) 4785 state->pll[0][ri++] = INREG(i); 4786 4787 ri = 0; 4788 for (i = 0x440; i <= 0x448; i += 4) 4789 state->pll[1][ri++] = INREG(i); 4790 for (i = 0x450; i <= 0x47c; i += 4) 4791 state->pll[1][ri++] = INREG(i); 4792 4793 ri = 0; 4794 for (i = 0x500; i <= 0x550; i += 0x10) 4795 state->pll_route[ri++] = INREG(i); 4796 } 4797 4798 static void dce4_restore_pll_regs(ScrnInfoPtr pScrn, struct dce4_state *state) 4799 { 4800 RADEONInfoPtr info = RADEONPTR(pScrn); 4801 unsigned char *RADEONMMIO = info->MMIO; 4802 int i, ri = 0; 4803 4804 for (i = 0x360; i <= 0x368; i += 4) 4805 OUTREG(i, state->vga_pll[0][ri++]); 4806 4807 ri = 0; 4808 for (i = 0x370; i <= 0x378; i += 4) 4809 OUTREG(i, state->vga_pll[1][ri++]); 4810 4811 ri = 0; 4812 for (i = 0x390; i <= 0x398; i += 4) 4813 OUTREG(i, state->vga_pll[2][ri++]); 4814 4815 ri = 0; 4816 for (i = 0x400; i <= 0x408; i += 4) 4817 OUTREG(i, state->pll[0][ri++]); 4818 for (i = 0x410; i <= 0x43c; i += 4) 4819 OUTREG(i, state->pll[0][ri++]); 4820 4821 ri = 0; 4822 for (i = 0x440; i <= 0x448; i += 4) 4823 OUTREG(i, state->pll[1][ri++]); 4824 for (i = 0x450; i <= 0x47c; i += 4) 4825 OUTREG(i, state->pll[1][ri++]); 4826 4827 ri = 0; 4828 for (i = 0x500; i <= 0x550; i += 0x10) 4829 OUTREG(i, state->pll_route[ri++]); 4830 } 4831 4832 static void 4833 dce4_save(ScrnInfoPtr pScrn, RADEONSavePtr save) 4834 { 4835 RADEONInfoPtr info = RADEONPTR(pScrn); 4836 unsigned char *RADEONMMIO = info->MMIO; 4837 struct dce4_state *state = &save->dce4; 4838 int i, j; 4839 uint32_t crtc_offset[] = {EVERGREEN_CRTC0_REGISTER_OFFSET, 4840 EVERGREEN_CRTC1_REGISTER_OFFSET, 4841 EVERGREEN_CRTC2_REGISTER_OFFSET, 4842 EVERGREEN_CRTC3_REGISTER_OFFSET, 4843 EVERGREEN_CRTC4_REGISTER_OFFSET, 4844 EVERGREEN_CRTC5_REGISTER_OFFSET}; 4845 4846 state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); 4847 state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); 4848 state->vga3_cntl = INREG(EVERGREEN_D3VGA_CONTROL); 4849 state->vga4_cntl = INREG(EVERGREEN_D4VGA_CONTROL); 4850 state->vga5_cntl = INREG(EVERGREEN_D5VGA_CONTROL); 4851 state->vga6_cntl = INREG(EVERGREEN_D6VGA_CONTROL); 4852 state->vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 4853 4854 dce4_save_pll_regs(pScrn, state); 4855 dce4_save_dig_regs(pScrn, state); 4856 4857 for (i = 0; i < 6; i++) 4858 dce4_save_block(pScrn, &state->block[i], crtc_offset[i]); 4859 4860 for (i = 0; i < 6; i++) 4861 dce4_save_uniphy(pScrn, state, i); 4862 4863 for (i = 0; i < 2; i++) { 4864 for (j = 0; j < DCE4_DAC_NUM; j++) { 4865 uint32_t offset = i ? 0x100 : 0x0; 4866 state->dac[i][j] = INREG(dce4_dac_regs[j] + offset); 4867 } 4868 } 4869 } 4870 4871 static void 4872 dce4_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4873 { 4874 RADEONInfoPtr info = RADEONPTR(pScrn); 4875 unsigned char *RADEONMMIO = info->MMIO; 4876 struct dce4_state *state = &restore->dce4; 4877 int i, j; 4878 uint32_t crtc_offset[] = {EVERGREEN_CRTC0_REGISTER_OFFSET, 4879 EVERGREEN_CRTC1_REGISTER_OFFSET, 4880 EVERGREEN_CRTC2_REGISTER_OFFSET, 4881 EVERGREEN_CRTC3_REGISTER_OFFSET, 4882 EVERGREEN_CRTC4_REGISTER_OFFSET, 4883 EVERGREEN_CRTC5_REGISTER_OFFSET}; 4884 4885 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 4886 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);; 4887 OUTREG(EVERGREEN_D3VGA_CONTROL, state->vga3_cntl); 4888 OUTREG(EVERGREEN_D4VGA_CONTROL, state->vga4_cntl); 4889 OUTREG(EVERGREEN_D5VGA_CONTROL, state->vga5_cntl); 4890 OUTREG(EVERGREEN_D6VGA_CONTROL, state->vga6_cntl); 4891 OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); 4892 4893 dce4_restore_dig_regs(pScrn, state); 4894 dce4_restore_pll_regs(pScrn, state); 4895 for (i = 0; i < 6; i++) 4896 dce4_restore_uniphy(pScrn, state, i); 4897 4898 for (i = 0; i < 6; i++) 4899 dce4_restore_block(pScrn, &state->block[i], crtc_offset[i]); 4900 4901 for (i = 0; i < 2; i++) { 4902 for (j = 0; j < DCE4_DAC_NUM; j++) { 4903 uint32_t offset = i ? 0x100 : 0x0; 4904 OUTREG(dce4_dac_regs[j] + offset, state->dac[i][j]); 4905 } 4906 } 4907 } 4908 4909 static void 4910 avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) 4911 { 4912 RADEONInfoPtr info = RADEONPTR(pScrn); 4913 unsigned char *RADEONMMIO = info->MMIO; 4914 struct avivo_state *state = &save->avivo; 4915 int i, j; 4916 4917 // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); 4918 // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); 4919 state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); 4920 state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); 4921 state->vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 4922 4923 state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); 4924 state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); 4925 state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT); 4926 4927 state->pll[0].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4928 state->pll[0].ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); 4929 state->pll[0].fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV); 4930 state->pll[0].post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC); 4931 state->pll[0].post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV); 4932 state->pll[0].ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL); 4933 state->pll[0].pll_cntl = INREG(AVIVO_P1PLL_CNTL); 4934 state->pll[0].int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL); 4935 4936 state->pll[1].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4937 state->pll[1].ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV); 4938 state->pll[1].fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV); 4939 state->pll[1].post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC); 4940 state->pll[1].post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV); 4941 state->pll[1].ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL); 4942 state->pll[1].pll_cntl = INREG(AVIVO_P2PLL_CNTL); 4943 state->pll[1].int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL); 4944 4945 state->vga25_ppll.ref_div_src = INREG(AVIVO_VGA25_PPLL_REF_DIV_SRC); 4946 state->vga25_ppll.ref_div = INREG(AVIVO_VGA25_PPLL_REF_DIV); 4947 state->vga25_ppll.fb_div = INREG(AVIVO_VGA25_PPLL_FB_DIV); 4948 state->vga25_ppll.post_div_src = INREG(AVIVO_VGA25_PPLL_POST_DIV_SRC); 4949 state->vga25_ppll.post_div = INREG(AVIVO_VGA25_PPLL_POST_DIV); 4950 state->vga25_ppll.pll_cntl = INREG(AVIVO_VGA25_PPLL_CNTL); 4951 4952 state->vga28_ppll.ref_div_src = INREG(AVIVO_VGA28_PPLL_REF_DIV_SRC); 4953 state->vga28_ppll.ref_div = INREG(AVIVO_VGA28_PPLL_REF_DIV); 4954 state->vga28_ppll.fb_div = INREG(AVIVO_VGA28_PPLL_FB_DIV); 4955 state->vga28_ppll.post_div_src = INREG(AVIVO_VGA28_PPLL_POST_DIV_SRC); 4956 state->vga28_ppll.post_div = INREG(AVIVO_VGA28_PPLL_POST_DIV); 4957 state->vga28_ppll.pll_cntl = INREG(AVIVO_VGA28_PPLL_CNTL); 4958 4959 state->vga41_ppll.ref_div_src = INREG(AVIVO_VGA41_PPLL_REF_DIV_SRC); 4960 state->vga41_ppll.ref_div = INREG(AVIVO_VGA41_PPLL_REF_DIV); 4961 state->vga41_ppll.fb_div = INREG(AVIVO_VGA41_PPLL_FB_DIV); 4962 state->vga41_ppll.post_div_src = INREG(AVIVO_VGA41_PPLL_POST_DIV_SRC); 4963 state->vga41_ppll.post_div = INREG(AVIVO_VGA41_PPLL_POST_DIV); 4964 state->vga41_ppll.pll_cntl = INREG(AVIVO_VGA41_PPLL_CNTL); 4965 4966 state->crtc[0].pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL); 4967 4968 state->crtc[0].h_total = INREG(AVIVO_D1CRTC_H_TOTAL); 4969 state->crtc[0].h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END); 4970 state->crtc[0].h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A); 4971 state->crtc[0].h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL); 4972 state->crtc[0].h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B); 4973 state->crtc[0].h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL); 4974 4975 state->crtc[0].v_total = INREG(AVIVO_D1CRTC_V_TOTAL); 4976 state->crtc[0].v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END); 4977 state->crtc[0].v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A); 4978 state->crtc[0].v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL); 4979 state->crtc[0].v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B); 4980 state->crtc[0].v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL); 4981 4982 state->crtc[0].control = INREG(AVIVO_D1CRTC_CONTROL); 4983 state->crtc[0].blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL); 4984 state->crtc[0].interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL); 4985 state->crtc[0].stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL); 4986 4987 state->crtc[0].cursor_control = INREG(AVIVO_D1CUR_CONTROL); 4988 4989 state->grph[0].enable = INREG(AVIVO_D1GRPH_ENABLE); 4990 state->grph[0].control = INREG(AVIVO_D1GRPH_CONTROL); 4991 state->grph[0].control = INREG(AVIVO_D1GRPH_CONTROL); 4992 state->grph[0].prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS); 4993 state->grph[0].sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS); 4994 state->grph[0].pitch = INREG(AVIVO_D1GRPH_PITCH); 4995 state->grph[0].x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X); 4996 state->grph[0].y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y); 4997 state->grph[0].x_start = INREG(AVIVO_D1GRPH_X_START); 4998 state->grph[0].y_start = INREG(AVIVO_D1GRPH_Y_START); 4999 state->grph[0].x_end = INREG(AVIVO_D1GRPH_X_END); 5000 state->grph[0].y_end = INREG(AVIVO_D1GRPH_Y_END); 5001 5002 state->grph[0].desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT); 5003 state->grph[0].viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); 5004 state->grph[0].viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); 5005 state->grph[0].mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT); 5006 5007 state->crtc[1].pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); 5008 5009 state->crtc[1].h_total = INREG(AVIVO_D2CRTC_H_TOTAL); 5010 state->crtc[1].h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END); 5011 state->crtc[1].h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A); 5012 state->crtc[1].h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL); 5013 state->crtc[1].h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B); 5014 state->crtc[1].h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL); 5015 5016 state->crtc[1].v_total = INREG(AVIVO_D2CRTC_V_TOTAL); 5017 state->crtc[1].v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END); 5018 state->crtc[1].v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A); 5019 state->crtc[1].v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL); 5020 state->crtc[1].v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B); 5021 state->crtc[1].v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL); 5022 5023 state->crtc[1].control = INREG(AVIVO_D2CRTC_CONTROL); 5024 state->crtc[1].blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL); 5025 state->crtc[1].interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL); 5026 state->crtc[1].stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL); 5027 5028 state->crtc[1].cursor_control = INREG(AVIVO_D2CUR_CONTROL); 5029 5030 state->grph[1].enable = INREG(AVIVO_D2GRPH_ENABLE); 5031 state->grph[1].control = INREG(AVIVO_D2GRPH_CONTROL); 5032 state->grph[1].control = INREG(AVIVO_D2GRPH_CONTROL); 5033 state->grph[1].prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS); 5034 state->grph[1].sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS); 5035 state->grph[1].pitch = INREG(AVIVO_D2GRPH_PITCH); 5036 state->grph[1].x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X); 5037 state->grph[1].y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y); 5038 state->grph[1].x_start = INREG(AVIVO_D2GRPH_X_START); 5039 state->grph[1].y_start = INREG(AVIVO_D2GRPH_Y_START); 5040 state->grph[1].x_end = INREG(AVIVO_D2GRPH_X_END); 5041 state->grph[1].y_end = INREG(AVIVO_D2GRPH_Y_END); 5042 5043 state->grph[1].desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT); 5044 state->grph[1].viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); 5045 state->grph[1].viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); 5046 state->grph[1].mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT); 5047 5048 if (IS_DCE3_VARIANT) { 5049 /* save DVOA regs */ 5050 state->dvoa[0] = INREG(0x7080); 5051 state->dvoa[1] = INREG(0x7084); 5052 state->dvoa[2] = INREG(0x708c); 5053 state->dvoa[3] = INREG(0x7090); 5054 state->dvoa[4] = INREG(0x7094); 5055 state->dvoa[5] = INREG(0x70ac); 5056 state->dvoa[6] = INREG(0x70b0); 5057 5058 j = 0; 5059 /* save DAC regs */ 5060 for (i = 0x7000; i <= 0x7040; i += 4) { 5061 state->daca[j] = INREG(i); 5062 state->dacb[j] = INREG(i + 0x100); 5063 j++; 5064 } 5065 for (i = 0x7058; i <= 0x7060; i += 4) { 5066 state->daca[j] = INREG(i); 5067 state->dacb[j] = INREG(i + 0x100); 5068 j++; 5069 } 5070 for (i = 0x7068; i <= 0x706c; i += 4) { 5071 state->daca[j] = INREG(i); 5072 state->dacb[j] = INREG(i + 0x100); 5073 j++; 5074 } 5075 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 5076 state->daca[j] = INREG(i); 5077 state->dacb[j] = INREG(i + 0x100); 5078 j++; 5079 } 5080 state->daca[j] = INREG(0x7050); 5081 state->dacb[j] = INREG(0x7050 + 0x100); 5082 5083 j = 0; 5084 /* save FMT regs */ 5085 for (i = 0x6700; i <= 0x6744; i += 4) { 5086 state->fmt1[j] = INREG(i); 5087 state->fmt2[j] = INREG(i + 0x800); 5088 j++; 5089 } 5090 5091 j = 0; 5092 /* save DIG regs */ 5093 for (i = 0x75a0; i <= 0x75e0; i += 4) { 5094 state->dig1[j] = INREG(i); 5095 state->dig2[j] = INREG(i + 0x400); 5096 j++; 5097 } 5098 for (i = 0x75e8; i <= 0x75ec; i += 4) { 5099 state->dig1[j] = INREG(i); 5100 state->dig2[j] = INREG(i + 0x400); 5101 j++; 5102 } 5103 5104 j = 0; 5105 /* save HDMI regs */ 5106 for (i = 0x7400; i <= 0x741c; i += 4) { 5107 state->hdmi1[j] = INREG(i); 5108 state->hdmi2[j] = INREG(i + 0x400); 5109 j++; 5110 } 5111 for (i = 0x7430; i <= 0x74ec; i += 4) { 5112 state->hdmi1[j] = INREG(i); 5113 state->hdmi2[j] = INREG(i + 0x400); 5114 j++; 5115 } 5116 state->hdmi1[j] = INREG(0x7428); 5117 state->hdmi2[j] = INREG(0x7828); 5118 5119 j = 0; 5120 /* save AUX regs */ 5121 for (i = 0x7780; i <= 0x77b4; i += 4) { 5122 state->aux_cntl1[j] = INREG(i); 5123 state->aux_cntl2[j] = INREG(i + 0x040); 5124 state->aux_cntl3[j] = INREG(i + 0x400); 5125 state->aux_cntl4[j] = INREG(i + 0x440); 5126 if (IS_DCE32_VARIANT) { 5127 state->aux_cntl5[j] = INREG(i + 0x500); 5128 state->aux_cntl6[j] = INREG(i + 0x540); 5129 } 5130 j++; 5131 } 5132 5133 j = 0; 5134 /* save UNIPHY regs */ 5135 if (IS_DCE32_VARIANT) { 5136 for (i = 0x7680; i <= 0x7690; i += 4) { 5137 state->uniphy1[j] = INREG(i); 5138 state->uniphy2[j] = INREG(i + 0x20); 5139 state->uniphy3[j] = INREG(i + 0x400); 5140 state->uniphy4[j] = INREG(i + 0x420); 5141 state->uniphy5[j] = INREG(i + 0x840); 5142 state->uniphy6[j] = INREG(i + 0x940); 5143 j++; 5144 } 5145 for (i = 0x7698; i <= 0x769c; i += 4) { 5146 state->uniphy1[j] = INREG(i); 5147 state->uniphy2[j] = INREG(i + 0x20); 5148 state->uniphy3[j] = INREG(i + 0x400); 5149 state->uniphy4[j] = INREG(i + 0x420); 5150 state->uniphy5[j] = INREG(i + 0x840); 5151 state->uniphy6[j] = INREG(i + 0x940); 5152 j++; 5153 } 5154 } else { 5155 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 5156 state->uniphy1[j] = INREG(i); 5157 state->uniphy2[j] = INREG(i + 0x100); 5158 j++; 5159 } 5160 } 5161 j = 0; 5162 /* save PHY,LINK regs */ 5163 for (i = 0x7f20; i <= 0x7f34; i += 4) { 5164 state->phy[j] = INREG(i); 5165 j++; 5166 } 5167 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 5168 state->phy[j] = INREG(i); 5169 j++; 5170 } 5171 state->phy[j] = INREG(0x7f40); 5172 5173 j = 0; 5174 /* save LVTMA regs */ 5175 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 5176 state->lvtma[j] = INREG(i); 5177 j++; 5178 } 5179 for (i = 0x7f80; i <= 0x7f98; i += 4) { 5180 state->lvtma[j] = INREG(i); 5181 j++; 5182 } 5183 } else { 5184 j = 0; 5185 /* save DVOA regs */ 5186 for (i = 0x7980; i <= 0x79bc; i += 4) { 5187 state->dvoa[j] = INREG(i); 5188 j++; 5189 } 5190 5191 j = 0; 5192 /* save DAC regs */ 5193 for (i = 0x7800; i <= 0x782c; i += 4) { 5194 state->daca[j] = INREG(i); 5195 state->dacb[j] = INREG(i + 0x200); 5196 j++; 5197 } 5198 for (i = 0x7834; i <= 0x7840; i += 4) { 5199 state->daca[j] = INREG(i); 5200 state->dacb[j] = INREG(i + 0x200); 5201 j++; 5202 } 5203 for (i = 0x7850; i <= 0x7868; i += 4) { 5204 state->daca[j] = INREG(i); 5205 state->dacb[j] = INREG(i + 0x200); 5206 j++; 5207 } 5208 5209 j = 0; 5210 /* save TMDSA regs */ 5211 for (i = 0x7880; i <= 0x78e0; i += 4) { 5212 state->tmdsa[j] = INREG(i); 5213 j++; 5214 } 5215 for (i = 0x7904; i <= 0x7918; i += 4) { 5216 state->tmdsa[j] = INREG(i); 5217 j++; 5218 } 5219 5220 j = 0; 5221 /* save LVTMA regs */ 5222 for (i = 0x7a80; i <= 0x7b18; i += 4) { 5223 state->lvtma[j] = INREG(i); 5224 j++; 5225 } 5226 5227 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 5228 (info->ChipFamily == CHIP_FAMILY_RS690) || 5229 (info->ChipFamily == CHIP_FAMILY_RS740)) { 5230 j = 0; 5231 /* save DDIA regs */ 5232 for (i = 0x7200; i <= 0x7290; i += 4) { 5233 state->ddia[j] = INREG(i); 5234 j++; 5235 } 5236 } 5237 } 5238 5239 /* scalers */ 5240 j = 0; 5241 for (i = 0x6578; i <= 0x65e4; i += 4) { 5242 state->d1scl[j] = INREG(i); 5243 state->d2scl[j] = INREG(i + 0x800); 5244 j++; 5245 } 5246 for (i = 0x6600; i <= 0x662c; i += 4) { 5247 state->d1scl[j] = INREG(i); 5248 state->d2scl[j] = INREG(i + 0x800); 5249 j++; 5250 } 5251 j = 0; 5252 for (i = 0x66e8; i <= 0x66fc; i += 4) { 5253 state->dxscl[j] = INREG(i); 5254 j++; 5255 } 5256 state->dxscl[6] = INREG(0x6e30); 5257 state->dxscl[7] = INREG(0x6e34); 5258 5259 if (state->crtc[0].control & AVIVO_CRTC_EN) 5260 info->crtc_on = TRUE; 5261 5262 if (state->crtc[1].control & AVIVO_CRTC_EN) 5263 info->crtc2_on = TRUE; 5264 5265 } 5266 5267 static void 5268 avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5269 { 5270 RADEONInfoPtr info = RADEONPTR(pScrn); 5271 unsigned char *RADEONMMIO = info->MMIO; 5272 struct avivo_state *state = &restore->avivo; 5273 int i, j; 5274 5275 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "avivo_restore !\n"); 5276 5277 /* Disable VGA control for now.. maybe needs to be changed */ 5278 OUTREG(AVIVO_D1VGA_CONTROL, 0); 5279 OUTREG(AVIVO_D2VGA_CONTROL, 0); 5280 5281 /* Disable CRTCs */ 5282 OUTREG(AVIVO_D1CRTC_CONTROL, 5283 (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000); 5284 OUTREG(AVIVO_D2CRTC_CONTROL, 5285 (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000); 5286 OUTREG(AVIVO_D1CRTC_CONTROL, 5287 INREG(AVIVO_D1CRTC_CONTROL) & ~0x1); 5288 OUTREG(AVIVO_D2CRTC_CONTROL, 5289 INREG(AVIVO_D2CRTC_CONTROL) & ~0x1); 5290 OUTREG(AVIVO_D1CRTC_CONTROL, 5291 INREG(AVIVO_D1CRTC_CONTROL) | 0x100); 5292 OUTREG(AVIVO_D2CRTC_CONTROL, 5293 INREG(AVIVO_D2CRTC_CONTROL) | 0x100); 5294 5295 /* Lock graph registers */ 5296 OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); 5297 OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph[0].prim_surf_addr); 5298 OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph[0].sec_surf_addr); 5299 OUTREG(AVIVO_D1GRPH_CONTROL, state->grph[0].control); 5300 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph[0].x_offset); 5301 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph[0].y_offset); 5302 OUTREG(AVIVO_D1GRPH_X_START, state->grph[0].x_start); 5303 OUTREG(AVIVO_D1GRPH_Y_START, state->grph[0].y_start); 5304 OUTREG(AVIVO_D1GRPH_X_END, state->grph[0].x_end); 5305 OUTREG(AVIVO_D1GRPH_Y_END, state->grph[0].y_end); 5306 OUTREG(AVIVO_D1GRPH_PITCH, state->grph[0].pitch); 5307 OUTREG(AVIVO_D1GRPH_ENABLE, state->grph[0].enable); 5308 OUTREG(AVIVO_D1GRPH_UPDATE, 0); 5309 5310 OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); 5311 OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph[1].prim_surf_addr); 5312 OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph[1].sec_surf_addr); 5313 OUTREG(AVIVO_D2GRPH_CONTROL, state->grph[1].control); 5314 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph[1].x_offset); 5315 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph[1].y_offset); 5316 OUTREG(AVIVO_D2GRPH_X_START, state->grph[1].x_start); 5317 OUTREG(AVIVO_D2GRPH_Y_START, state->grph[1].y_start); 5318 OUTREG(AVIVO_D2GRPH_X_END, state->grph[1].x_end); 5319 OUTREG(AVIVO_D2GRPH_Y_END, state->grph[1].y_end); 5320 OUTREG(AVIVO_D2GRPH_PITCH, state->grph[1].pitch); 5321 OUTREG(AVIVO_D2GRPH_ENABLE, state->grph[1].enable); 5322 OUTREG(AVIVO_D2GRPH_UPDATE, 0); 5323 5324 /* Whack some mode regs too */ 5325 OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); 5326 OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph[0].desktop_height); 5327 OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph[0].viewport_start); 5328 OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph[0].viewport_size); 5329 OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph[0].mode_data_format); 5330 OUTREG(AVIVO_D1SCL_UPDATE, 0); 5331 5332 OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); 5333 OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph[1].desktop_height); 5334 OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph[1].viewport_start); 5335 OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph[1].viewport_size); 5336 OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph[1].mode_data_format); 5337 OUTREG(AVIVO_D2SCL_UPDATE, 0); 5338 5339 /* Set the PLL */ 5340 OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll[0].ref_div_src); 5341 OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll[0].ref_div); 5342 OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll[0].fb_div); 5343 OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll[0].post_div_src); 5344 OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll[0].post_div); 5345 OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll[0].ext_ppll_cntl); 5346 OUTREG(AVIVO_P1PLL_CNTL, state->pll[0].pll_cntl); 5347 OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll[0].int_ss_cntl); 5348 5349 OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll[1].ref_div_src); 5350 OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll[1].ref_div); 5351 OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll[1].fb_div); 5352 OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll[1].post_div_src); 5353 OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll[1].post_div); 5354 OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll[1].ext_ppll_cntl); 5355 OUTREG(AVIVO_P2PLL_CNTL, state->pll[1].pll_cntl); 5356 OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll[1].int_ss_cntl); 5357 5358 OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc[0].pll_source); 5359 OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc[1].pll_source); 5360 5361 /* Set the vga PLL */ 5362 OUTREG(AVIVO_VGA25_PPLL_REF_DIV_SRC, state->vga25_ppll.ref_div_src); 5363 OUTREG(AVIVO_VGA25_PPLL_REF_DIV, state->vga25_ppll.ref_div); 5364 OUTREG(AVIVO_VGA25_PPLL_FB_DIV, state->vga25_ppll.fb_div); 5365 OUTREG(AVIVO_VGA25_PPLL_POST_DIV_SRC, state->vga25_ppll.post_div_src); 5366 OUTREG(AVIVO_VGA25_PPLL_POST_DIV, state->vga25_ppll.post_div); 5367 OUTREG(AVIVO_VGA25_PPLL_CNTL, state->vga25_ppll.pll_cntl); 5368 5369 OUTREG(AVIVO_VGA28_PPLL_REF_DIV_SRC, state->vga28_ppll.ref_div_src); 5370 OUTREG(AVIVO_VGA28_PPLL_REF_DIV, state->vga28_ppll.ref_div); 5371 OUTREG(AVIVO_VGA28_PPLL_FB_DIV, state->vga28_ppll.fb_div); 5372 OUTREG(AVIVO_VGA28_PPLL_POST_DIV_SRC, state->vga28_ppll.post_div_src); 5373 OUTREG(AVIVO_VGA28_PPLL_POST_DIV, state->vga28_ppll.post_div); 5374 OUTREG(AVIVO_VGA28_PPLL_CNTL, state->vga28_ppll.pll_cntl); 5375 5376 OUTREG(AVIVO_VGA41_PPLL_REF_DIV_SRC, state->vga41_ppll.ref_div_src); 5377 OUTREG(AVIVO_VGA41_PPLL_REF_DIV, state->vga41_ppll.ref_div); 5378 OUTREG(AVIVO_VGA41_PPLL_FB_DIV, state->vga41_ppll.fb_div); 5379 OUTREG(AVIVO_VGA41_PPLL_POST_DIV_SRC, state->vga41_ppll.post_div_src); 5380 OUTREG(AVIVO_VGA41_PPLL_POST_DIV, state->vga41_ppll.post_div); 5381 OUTREG(AVIVO_VGA41_PPLL_CNTL, state->vga41_ppll.pll_cntl); 5382 5383 /* Set the CRTC */ 5384 OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc[0].h_total); 5385 OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc[0].h_blank_start_end); 5386 OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc[0].h_sync_a); 5387 OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc[0].h_sync_a_cntl); 5388 OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc[0].h_sync_b); 5389 OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc[0].h_sync_b_cntl); 5390 5391 OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc[0].v_total); 5392 OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc[0].v_blank_start_end); 5393 OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc[0].v_sync_a); 5394 OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc[0].v_sync_a_cntl); 5395 OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc[0].v_sync_b); 5396 OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc[0].v_sync_b_cntl); 5397 5398 OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc[0].interlace_control); 5399 OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc[0].stereo_control); 5400 5401 OUTREG(AVIVO_D1CUR_CONTROL, state->crtc[0].cursor_control); 5402 5403 /* XXX Fix scaler */ 5404 5405 OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc[1].h_total); 5406 OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc[1].h_blank_start_end); 5407 OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc[1].h_sync_a); 5408 OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc[1].h_sync_a_cntl); 5409 OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc[1].h_sync_b); 5410 OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc[1].h_sync_b_cntl); 5411 5412 OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc[1].v_total); 5413 OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc[1].v_blank_start_end); 5414 OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc[1].v_sync_a); 5415 OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc[1].v_sync_a_cntl); 5416 OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc[1].v_sync_b); 5417 OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc[1].v_sync_b_cntl); 5418 5419 OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc[1].interlace_control); 5420 OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc[1].stereo_control); 5421 5422 OUTREG(AVIVO_D2CUR_CONTROL, state->crtc[1].cursor_control); 5423 5424 if (IS_DCE3_VARIANT) { 5425 /* DVOA regs */ 5426 OUTREG(0x7080, state->dvoa[0]); 5427 OUTREG(0x7084, state->dvoa[1]); 5428 OUTREG(0x708c, state->dvoa[2]); 5429 OUTREG(0x7090, state->dvoa[3]); 5430 OUTREG(0x7094, state->dvoa[4]); 5431 OUTREG(0x70ac, state->dvoa[5]); 5432 OUTREG(0x70b0, state->dvoa[6]); 5433 5434 j = 0; 5435 /* DAC regs */ 5436 for (i = 0x7000; i <= 0x7040; i += 4) { 5437 OUTREG(i, state->daca[j]); 5438 OUTREG((i + 0x100), state->dacb[j]); 5439 j++; 5440 } 5441 for (i = 0x7058; i <= 0x7060; i += 4) { 5442 OUTREG(i, state->daca[j]); 5443 OUTREG((i + 0x100), state->dacb[j]); 5444 j++; 5445 } 5446 for (i = 0x7068; i <= 0x706c; i += 4) { 5447 OUTREG(i, state->daca[j]); 5448 OUTREG((i + 0x100), state->dacb[j]); 5449 j++; 5450 } 5451 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 5452 OUTREG(i, state->daca[j]); 5453 OUTREG((i + 0x100), state->dacb[j]); 5454 j++; 5455 } 5456 OUTREG(0x7050, state->daca[j]); 5457 OUTREG((0x7050 + 0x100), state->dacb[j]); 5458 5459 j = 0; 5460 /* FMT regs */ 5461 for (i = 0x6700; i <= 0x6744; i += 4) { 5462 OUTREG(i, state->fmt1[j]); 5463 OUTREG((i + 0x800), state->fmt2[j]); 5464 j++; 5465 } 5466 5467 j = 0; 5468 /* DIG regs */ 5469 for (i = 0x75a0; i <= 0x75e0; i += 4) { 5470 OUTREG(i, state->dig1[j]); 5471 OUTREG((i + 0x400), state->dig2[j]); 5472 j++; 5473 } 5474 for (i = 0x75e8; i <= 0x75ec; i += 4) { 5475 OUTREG(i, state->dig1[j]); 5476 OUTREG((i + 0x400), state->dig2[j]); 5477 j++; 5478 } 5479 5480 j = 0; 5481 /* HDMI regs */ 5482 for (i = 0x7400; i <= 0x741c; i += 4) { 5483 OUTREG(i, state->hdmi1[j]); 5484 OUTREG((i + 0x400), state->hdmi2[j]); 5485 j++; 5486 } 5487 for (i = 0x7430; i <= 0x74ec; i += 4) { 5488 OUTREG(i, state->hdmi1[j]); 5489 OUTREG((i + 0x400), state->hdmi2[j]); 5490 j++; 5491 } 5492 OUTREG(0x7428, state->hdmi1[j]); 5493 OUTREG((0x7428 + 0x400), state->hdmi2[j]); 5494 5495 j = 0; 5496 /* save AUX regs */ 5497 for (i = 0x7780; i <= 0x77b4; i += 4) { 5498 OUTREG(i, state->aux_cntl1[j]); 5499 OUTREG((i + 0x040), state->aux_cntl2[j]); 5500 OUTREG((i + 0x400), state->aux_cntl3[j]); 5501 OUTREG((i + 0x440), state->aux_cntl4[j]); 5502 if (IS_DCE32_VARIANT) { 5503 OUTREG((i + 0x500), state->aux_cntl5[j]); 5504 OUTREG((i + 0x540), state->aux_cntl6[j]); 5505 } 5506 j++; 5507 } 5508 5509 j = 0; 5510 /* save UNIPHY regs */ 5511 if (IS_DCE32_VARIANT) { 5512 for (i = 0x7680; i <= 0x7690; i += 4) { 5513 OUTREG(i, state->uniphy1[j]); 5514 OUTREG((i + 0x20), state->uniphy2[j]); 5515 OUTREG((i + 0x400), state->uniphy3[j]); 5516 OUTREG((i + 0x420), state->uniphy4[j]); 5517 OUTREG((i + 0x840), state->uniphy5[j]); 5518 OUTREG((i + 0x940), state->uniphy6[j]); 5519 j++; 5520 } 5521 for (i = 0x7698; i <= 0x769c; i += 4) { 5522 OUTREG(i, state->uniphy1[j]); 5523 OUTREG((i + 0x20), state->uniphy2[j]); 5524 OUTREG((i + 0x400), state->uniphy3[j]); 5525 OUTREG((i + 0x420), state->uniphy4[j]); 5526 OUTREG((i + 0x840), state->uniphy5[j]); 5527 OUTREG((i + 0x940), state->uniphy6[j]); 5528 j++; 5529 } 5530 } else { 5531 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 5532 OUTREG(i, state->uniphy1[j]); 5533 OUTREG((i + 0x100), state->uniphy2[j]); 5534 j++; 5535 } 5536 } 5537 j = 0; 5538 /* save PHY,LINK regs */ 5539 for (i = 0x7f20; i <= 0x7f34; i += 4) { 5540 OUTREG(i, state->phy[j]); 5541 j++; 5542 } 5543 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 5544 OUTREG(i, state->phy[j]); 5545 j++; 5546 } 5547 state->phy[j] = INREG(0x7f40); 5548 5549 j = 0; 5550 /* save LVTMA regs */ 5551 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 5552 OUTREG(i, state->lvtma[j]); 5553 j++; 5554 } 5555 for (i = 0x7f80; i <= 0x7f98; i += 4) { 5556 OUTREG(i, state->lvtma[j]); 5557 j++; 5558 } 5559 } else { 5560 j = 0; 5561 /* DVOA regs */ 5562 for (i = 0x7980; i <= 0x79bc; i += 4) { 5563 OUTREG(i, state->dvoa[j]); 5564 j++; 5565 } 5566 5567 j = 0; 5568 /* DAC regs */ /* -- MIGHT NEED ORDERING FIX & DELAYS -- */ 5569 for (i = 0x7800; i <= 0x782c; i += 4) { 5570 OUTREG(i, state->daca[j]); 5571 OUTREG((i + 0x200), state->dacb[j]); 5572 j++; 5573 } 5574 for (i = 0x7834; i <= 0x7840; i += 4) { 5575 OUTREG(i, state->daca[j]); 5576 OUTREG((i + 0x200), state->dacb[j]); 5577 j++; 5578 } 5579 for (i = 0x7850; i <= 0x7868; i += 4) { 5580 OUTREG(i, state->daca[j]); 5581 OUTREG((i + 0x200), state->dacb[j]); 5582 j++; 5583 } 5584 5585 j = 0; 5586 /* TMDSA regs */ 5587 for (i = 0x7880; i <= 0x78e0; i += 4) { 5588 OUTREG(i, state->tmdsa[j]); 5589 j++; 5590 } 5591 for (i = 0x7904; i <= 0x7918; i += 4) { 5592 OUTREG(i, state->tmdsa[j]); 5593 j++; 5594 } 5595 5596 j = 0; 5597 /* LVTMA regs */ 5598 for (i = 0x7a80; i <= 0x7b18; i += 4) { 5599 OUTREG(i, state->lvtma[j]); 5600 j++; 5601 } 5602 5603 /* DDIA regs */ 5604 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 5605 (info->ChipFamily == CHIP_FAMILY_RS690) || 5606 (info->ChipFamily == CHIP_FAMILY_RS740)) { 5607 j = 0; 5608 for (i = 0x7200; i <= 0x7290; i += 4) { 5609 OUTREG(i, state->ddia[j]); 5610 j++; 5611 } 5612 } 5613 } 5614 5615 /* scalers */ 5616 j = 0; 5617 for (i = 0x6578; i <= 0x65e4; i += 4) { 5618 OUTREG(i, state->d1scl[j]); 5619 OUTREG((i + 0x800), state->d2scl[j]); 5620 j++; 5621 } 5622 for (i = 0x6600; i <= 0x662c; i += 4) { 5623 OUTREG(i, state->d1scl[j]); 5624 OUTREG((i + 0x800), state->d2scl[j]); 5625 j++; 5626 } 5627 j = 0; 5628 for (i = 0x66e8; i <= 0x66fc; i += 4) { 5629 OUTREG(i, state->dxscl[j]); 5630 j++; 5631 } 5632 OUTREG(0x6e30, state->dxscl[6]); 5633 OUTREG(0x6e34, state->dxscl[7]); 5634 5635 /* Enable CRTCs */ 5636 if (state->crtc[0].control & 1) { 5637 OUTREG(AVIVO_D1CRTC_CONTROL, 0x01000101); 5638 INREG(AVIVO_D1CRTC_CONTROL); 5639 OUTREG(AVIVO_D1CRTC_CONTROL, 0x00010101); 5640 } 5641 if (state->crtc[1].control & 1) { 5642 OUTREG(AVIVO_D2CRTC_CONTROL, 0x01000101); 5643 INREG(AVIVO_D2CRTC_CONTROL); 5644 OUTREG(AVIVO_D2CRTC_CONTROL, 0x00010101); 5645 } 5646 5647 /* Where should that go ? */ 5648 OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); 5649 OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, state->dc_lb_memory_split); 5650 5651 /* Need fixing too ? */ 5652 OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc[0].blank_control); 5653 OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc[1].blank_control); 5654 5655 /* Dbl check */ 5656 OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); 5657 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 5658 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 5659 5660 /* Should only enable outputs here */ 5661 } 5662 5663 static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5664 { 5665 RADEONInfoPtr info = RADEONPTR(pScrn); 5666 unsigned char *RADEONMMIO = info->MMIO; 5667 struct avivo_state *state = &restore->avivo; 5668 5669 OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); 5670 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 5671 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 5672 } 5673 5674 static void dce4_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5675 { 5676 RADEONInfoPtr info = RADEONPTR(pScrn); 5677 unsigned char *RADEONMMIO = info->MMIO; 5678 struct dce4_state *state = &restore->dce4; 5679 5680 OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); 5681 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 5682 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 5683 OUTREG(EVERGREEN_D3VGA_CONTROL, state->vga3_cntl); 5684 OUTREG(EVERGREEN_D4VGA_CONTROL, state->vga4_cntl); 5685 OUTREG(EVERGREEN_D5VGA_CONTROL, state->vga5_cntl); 5686 OUTREG(EVERGREEN_D6VGA_CONTROL, state->vga6_cntl); 5687 } 5688 5689 5690 static void 5691 RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5692 { 5693 RADEONInfoPtr info = RADEONPTR(pScrn); 5694 unsigned char *RADEONMMIO = info->MMIO; 5695 5696 if (info->ChipFamily >= CHIP_FAMILY_R600) { 5697 OUTREG(R600_BIOS_0_SCRATCH, restore->bios_0_scratch); 5698 OUTREG(R600_BIOS_1_SCRATCH, restore->bios_1_scratch); 5699 OUTREG(R600_BIOS_2_SCRATCH, restore->bios_2_scratch); 5700 OUTREG(R600_BIOS_3_SCRATCH, restore->bios_3_scratch); 5701 OUTREG(R600_BIOS_4_SCRATCH, restore->bios_4_scratch); 5702 OUTREG(R600_BIOS_5_SCRATCH, restore->bios_5_scratch); 5703 OUTREG(R600_BIOS_6_SCRATCH, restore->bios_6_scratch); 5704 OUTREG(R600_BIOS_7_SCRATCH, restore->bios_7_scratch); 5705 } else { 5706 OUTREG(RADEON_BIOS_0_SCRATCH, restore->bios_0_scratch); 5707 OUTREG(RADEON_BIOS_1_SCRATCH, restore->bios_1_scratch); 5708 OUTREG(RADEON_BIOS_2_SCRATCH, restore->bios_2_scratch); 5709 OUTREG(RADEON_BIOS_3_SCRATCH, restore->bios_3_scratch); 5710 OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch); 5711 OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); 5712 OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch); 5713 OUTREG(RADEON_BIOS_7_SCRATCH, restore->bios_7_scratch); 5714 } 5715 } 5716 5717 static void 5718 RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 5719 { 5720 RADEONInfoPtr info = RADEONPTR(pScrn); 5721 unsigned char *RADEONMMIO = info->MMIO; 5722 5723 if (info->ChipFamily >= CHIP_FAMILY_R600) { 5724 save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); 5725 save->bios_1_scratch = INREG(R600_BIOS_1_SCRATCH); 5726 save->bios_2_scratch = INREG(R600_BIOS_2_SCRATCH); 5727 save->bios_3_scratch = INREG(R600_BIOS_3_SCRATCH); 5728 save->bios_4_scratch = INREG(R600_BIOS_4_SCRATCH); 5729 save->bios_5_scratch = INREG(R600_BIOS_5_SCRATCH); 5730 save->bios_6_scratch = INREG(R600_BIOS_6_SCRATCH); 5731 save->bios_7_scratch = INREG(R600_BIOS_7_SCRATCH); 5732 } else { 5733 save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); 5734 save->bios_1_scratch = INREG(RADEON_BIOS_1_SCRATCH); 5735 save->bios_2_scratch = INREG(RADEON_BIOS_2_SCRATCH); 5736 save->bios_3_scratch = INREG(RADEON_BIOS_3_SCRATCH); 5737 save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH); 5738 save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH); 5739 save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH); 5740 save->bios_7_scratch = INREG(RADEON_BIOS_7_SCRATCH); 5741 } 5742 } 5743 5744 void radeon_save_palette_on_demand(ScrnInfoPtr pScrn, int palID) 5745 { 5746 RADEONInfoPtr info = RADEONPTR(pScrn); 5747 RADEONSavePtr save = info->SavedReg; 5748 5749 if (save->palette_saved[palID] == TRUE) 5750 return; 5751 5752 if (!IS_AVIVO_VARIANT) 5753 RADEONSavePalette(pScrn, palID, save); 5754 5755 save->palette_saved[palID] = TRUE; 5756 } 5757 5758 /* Save everything needed to restore the original VC state */ 5759 static void RADEONSave(ScrnInfoPtr pScrn) 5760 { 5761 RADEONInfoPtr info = RADEONPTR(pScrn); 5762 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5763 unsigned char *RADEONMMIO = info->MMIO; 5764 RADEONSavePtr save = info->SavedReg; 5765 5766 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5767 "RADEONSave\n"); 5768 5769 #ifdef WITH_VGAHW 5770 if (info->VGAAccess) { 5771 vgaHWPtr hwp = VGAHWPTR(pScrn); 5772 5773 vgaHWUnlock(hwp); 5774 # if defined(__powerpc__) 5775 /* temporary hack to prevent crashing on PowerMacs when trying to 5776 * read VGA fonts and colormap, will find a better solution 5777 * in the future. TODO: Check if there's actually some VGA stuff 5778 * setup in the card at all !! 5779 */ 5780 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ 5781 # else 5782 /* Save only mode * & fonts */ 5783 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 5784 # endif 5785 vgaHWLock(hwp); 5786 } 5787 #endif 5788 5789 if (IS_DCE4_VARIANT) { 5790 RADEONSaveMemMapRegisters(pScrn, save); 5791 dce4_save(pScrn, save); 5792 //XXX 5793 } else if (IS_AVIVO_VARIANT) { 5794 RADEONSaveMemMapRegisters(pScrn, save); 5795 avivo_save(pScrn, save); 5796 } else { 5797 save->dp_datatype = INREG(RADEON_DP_DATATYPE); 5798 save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); 5799 save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); 5800 RADEONPllErrataAfterIndex(info); 5801 5802 RADEONSaveMemMapRegisters(pScrn, save); 5803 RADEONSaveCommonRegisters(pScrn, save); 5804 RADEONSavePLLRegisters(pScrn, save); 5805 RADEONSaveCrtcRegisters(pScrn, save); 5806 RADEONSaveFPRegisters(pScrn, save); 5807 RADEONSaveDACRegisters(pScrn, save); 5808 /* Palette saving is done on demand now */ 5809 5810 if (pRADEONEnt->HasCRTC2) { 5811 RADEONSaveCrtc2Registers(pScrn, save); 5812 RADEONSavePLL2Registers(pScrn, save); 5813 } 5814 if (info->InternalTVOut) 5815 RADEONSaveTVRegisters(pScrn, save); 5816 } 5817 5818 if (info->ChipFamily < CHIP_FAMILY_R600) 5819 RADEONSaveSurfaces(pScrn, save); 5820 5821 } 5822 5823 /* Restore the original (text) mode */ 5824 static void RADEONRestore(ScrnInfoPtr pScrn) 5825 { 5826 RADEONInfoPtr info = RADEONPTR(pScrn); 5827 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5828 unsigned char *RADEONMMIO = info->MMIO; 5829 RADEONSavePtr restore = info->SavedReg; 5830 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 5831 xf86CrtcPtr crtc; 5832 5833 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5834 "RADEONRestore\n"); 5835 5836 #if X_BYTE_ORDER == X_BIG_ENDIAN 5837 if (info->ChipFamily < CHIP_FAMILY_R600) { 5838 RADEONWaitForFifo(pScrn, 1); 5839 OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); 5840 } 5841 #endif 5842 5843 RADEONBlank(pScrn); 5844 5845 if (IS_DCE4_VARIANT) { 5846 RADEONRestoreMemMapRegisters(pScrn, restore); 5847 dce4_restore(pScrn, restore); 5848 //XXX 5849 } else if (IS_AVIVO_VARIANT) { 5850 RADEONRestoreMemMapRegisters(pScrn, restore); 5851 avivo_restore(pScrn, restore); 5852 } else { 5853 OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); 5854 OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); 5855 OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); 5856 OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); 5857 5858 if (!info->IsSecondary) { 5859 RADEONRestoreMemMapRegisters(pScrn, restore); 5860 RADEONRestoreCommonRegisters(pScrn, restore); 5861 5862 RADEONRestorePalette(pScrn, restore); 5863 if (pRADEONEnt->HasCRTC2) { 5864 RADEONRestoreCrtc2Registers(pScrn, restore); 5865 RADEONRestorePLL2Registers(pScrn, restore); 5866 } 5867 5868 RADEONRestoreCrtcRegisters(pScrn, restore); 5869 RADEONRestorePLLRegisters(pScrn, restore); 5870 RADEONRestoreRMXRegisters(pScrn, restore); 5871 RADEONRestoreFPRegisters(pScrn, restore); 5872 RADEONRestoreFP2Registers(pScrn, restore); 5873 RADEONRestoreLVDSRegisters(pScrn, restore); 5874 5875 if (info->InternalTVOut) 5876 RADEONRestoreTVRegisters(pScrn, restore); 5877 } 5878 5879 OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); 5880 RADEONPllErrataAfterIndex(info); 5881 5882 RADEONRestoreBIOSRegisters(pScrn, restore); 5883 } 5884 5885 5886 #if 1 5887 /* Temp fix to "solve" VT switch problems. When switching VTs on 5888 * some systems, the console can either hang or the fonts can be 5889 * corrupted. This hack solves the problem 99% of the time. A 5890 * correct fix is being worked on. 5891 */ 5892 usleep(100000); 5893 #endif 5894 5895 if (info->ChipFamily < CHIP_FAMILY_R600) 5896 RADEONRestoreSurfaces(pScrn, restore); 5897 5898 /* need to make sure we don't enable a crtc by accident or we may get a hang */ 5899 if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { 5900 if (info->crtc2_on && xf86_config->num_crtc > 1) { 5901 crtc = xf86_config->crtc[1]; 5902 radeon_do_crtc_dpms(crtc, DPMSModeOn); 5903 } 5904 } 5905 if (info->crtc_on) { 5906 crtc = xf86_config->crtc[0]; 5907 radeon_do_crtc_dpms(crtc, DPMSModeOn); 5908 } 5909 5910 #ifdef WITH_VGAHW 5911 if (info->VGAAccess) { 5912 vgaHWPtr hwp = VGAHWPTR(pScrn); 5913 vgaHWUnlock(hwp); 5914 # if defined(__powerpc__) 5915 /* Temporary hack to prevent crashing on PowerMacs when trying to 5916 * write VGA fonts, will find a better solution in the future 5917 */ 5918 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); 5919 # else 5920 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 5921 # endif 5922 vgaHWLock(hwp); 5923 } 5924 #endif 5925 5926 /* to restore console mode, DAC registers should be set after every other registers are set, 5927 * otherwise,we may get blank screen 5928 */ 5929 if (IS_DCE4_VARIANT) 5930 dce4_restore_vga_regs(pScrn, restore); 5931 else if (IS_AVIVO_VARIANT) 5932 avivo_restore_vga_regs(pScrn, restore); 5933 else { 5934 RADEONRestoreDACRegisters(pScrn, restore); 5935 } 5936 #if 0 5937 RADEONWaitForVerticalSync(pScrn); 5938 #endif 5939 } 5940 5941 static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) 5942 { 5943 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 5944 Bool unblank; 5945 5946 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5947 "RADEONSaveScreen(%d)\n", mode); 5948 5949 unblank = xf86IsUnblank(mode); 5950 if (unblank) SetTimeSinceLastInputEvent(); 5951 5952 if ((pScrn != NULL) && pScrn->vtSema) { 5953 if (unblank) 5954 RADEONUnblank(pScrn); 5955 else 5956 RADEONBlank(pScrn); 5957 } 5958 return TRUE; 5959 } 5960 5961 Bool RADEONSwitchMode(SWITCH_MODE_ARGS_DECL) 5962 { 5963 SCRN_INFO_PTR(arg); 5964 RADEONInfoPtr info = RADEONPTR(pScrn); 5965 Bool tilingOld = info->tilingEnabled; 5966 Bool ret; 5967 #ifdef XF86DRI 5968 Bool CPStarted = info->cp->CPStarted; 5969 5970 if (CPStarted) { 5971 DRILock(pScrn->pScreen, 0); 5972 RADEONCP_STOP(pScrn, info); 5973 } 5974 #endif 5975 5976 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5977 "RADEONSwitchMode() !n"); 5978 5979 if (info->allowColorTiling) { 5980 info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 5981 #ifdef XF86DRI 5982 if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { 5983 drm_radeon_sarea_t *pSAREAPriv; 5984 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 5985 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 5986 "[drm] failed changing tiling status\n"); 5987 pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); 5988 info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; 5989 } 5990 #endif 5991 } 5992 5993 if (info->accelOn) 5994 RADEON_SYNC(info, pScrn); 5995 5996 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 5997 5998 if (info->tilingEnabled != tilingOld) { 5999 /* need to redraw front buffer, I guess this can be considered a hack ? */ 6000 xf86EnableDisableFBAccess(arg, FALSE); 6001 RADEONChangeSurfaces(pScrn); 6002 xf86EnableDisableFBAccess(arg, TRUE); 6003 /* xf86SetRootClip would do, but can't access that here */ 6004 } 6005 6006 if (info->accelOn) { 6007 RADEON_SYNC(info, pScrn); 6008 if (info->ChipFamily < CHIP_FAMILY_R600) 6009 RADEONEngineRestore(pScrn); 6010 } 6011 6012 #ifdef XF86DRI 6013 if (CPStarted) { 6014 RADEONCP_START(pScrn, info); 6015 DRIUnlock(pScrn->pScreen); 6016 } 6017 #endif 6018 6019 /* reset ecp for overlay */ 6020 info->ecp_div = -1; 6021 6022 return ret; 6023 } 6024 6025 #ifdef X_XF86MiscPassMessage 6026 Bool RADEONHandleMessage(int scrnIndex, const char* msgtype, 6027 const char* msgval, char** retmsg) 6028 { 6029 ErrorF("RADEONHandleMessage(%d, \"%s\", \"%s\", retmsg)\n", scrnIndex, 6030 msgtype, msgval); 6031 *retmsg = ""; 6032 return 0; 6033 } 6034 #endif 6035 6036 #ifndef HAVE_XF86MODEBANDWIDTH 6037 /** Calculates the memory bandwidth (in MiB/sec) of a mode. */ 6038 _X_HIDDEN unsigned int 6039 xf86ModeBandwidth(DisplayModePtr mode, int depth) 6040 { 6041 float a_active, a_total, active_percent, pixels_per_second; 6042 int bytes_per_pixel = (depth + 7) / 8; 6043 6044 if (!mode->HTotal || !mode->VTotal || !mode->Clock) 6045 return 0; 6046 6047 a_active = mode->HDisplay * mode->VDisplay; 6048 a_total = mode->HTotal * mode->VTotal; 6049 active_percent = a_active / a_total; 6050 pixels_per_second = active_percent * mode->Clock * 1000.0; 6051 6052 return (unsigned int)(pixels_per_second * bytes_per_pixel / (1024 * 1024)); 6053 } 6054 #endif 6055 6056 /* Used to disallow modes that are not supported by the hardware */ 6057 ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, 6058 Bool verbose, int flag) 6059 { 6060 SCRN_INFO_PTR(arg); 6061 RADEONInfoPtr info = RADEONPTR(pScrn); 6062 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 6063 6064 /* 6065 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 6066 * XXX should really do this for all chips by properly computing 6067 * memory bandwidth and an overhead factor. 6068 */ 6069 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 6070 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 6071 return MODE_BANDWIDTH; 6072 } 6073 6074 /* There are problems with double scan mode at high clocks 6075 * They're likely related PLL and display buffer settings. 6076 * Disable these modes for now. 6077 */ 6078 if (mode->Flags & V_DBLSCAN) { 6079 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 6080 return MODE_CLOCK_RANGE; 6081 } 6082 return MODE_OK; 6083 } 6084 6085 /* Adjust viewport into virtual desktop such that (0,0) in viewport 6086 * space is (x,y) in virtual space. 6087 */ 6088 void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) 6089 { 6090 RADEONInfoPtr info = RADEONPTR(pScrn); 6091 unsigned char *RADEONMMIO = info->MMIO; 6092 int Base, reg, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0; 6093 #ifdef XF86DRI 6094 drm_radeon_sarea_t *pSAREAPriv; 6095 XF86DRISAREAPtr pSAREA; 6096 #endif 6097 6098 #if 0 /* Verbose */ 6099 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6100 "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone); 6101 #endif 6102 6103 Base = pScrn->fbOffset; 6104 6105 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 6106 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 6107 flickering when scrolling vertically in a virtual screen, possibly because crtc will 6108 pick up the new offset value at the end of each scanline, but the new offset_cntl value 6109 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 6110 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 6111 if (crtc2) { 6112 reg = RADEON_CRTC2_OFFSET; 6113 regcntl = RADEON_CRTC2_OFFSET_CNTL; 6114 xytilereg = R300_CRTC2_TILE_X0_Y0; 6115 } else { 6116 reg = RADEON_CRTC_OFFSET; 6117 regcntl = RADEON_CRTC_OFFSET_CNTL; 6118 xytilereg = R300_CRTC_TILE_X0_Y0; 6119 } 6120 crtcoffsetcntl = INREG(regcntl) & ~0xf; 6121 #if 0 6122 /* try to get rid of flickering when scrolling at least for 2d */ 6123 #ifdef XF86DRI 6124 if (!info->dri->have3DWindows) 6125 #endif 6126 crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 6127 #endif 6128 if (info->tilingEnabled) { 6129 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 6130 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 6131 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 6132 * Makes tiling MUCH easier. 6133 */ 6134 crtcxytile = x | (y << 16); 6135 Base &= ~0x7ff; 6136 } else { 6137 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 6138 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 6139 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 6140 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 6141 crtcoffsetcntl = crtcoffsetcntl | (y % 16); 6142 } 6143 } 6144 else { 6145 int offset = y * info->CurrentLayout.displayWidth + x; 6146 switch (info->CurrentLayout.pixel_code) { 6147 case 15: 6148 case 16: offset *= 2; break; 6149 case 24: offset *= 3; break; 6150 case 32: offset *= 4; break; 6151 } 6152 Base += offset; 6153 } 6154 6155 Base &= ~7; /* 3 lower bits are always 0 */ 6156 6157 #ifdef XF86DRI 6158 if (info->directRenderingInited) { 6159 /* note cannot use pScrn->pScreen since this is unitialized when called from 6160 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 6161 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 6162 *** pageflipping! 6163 ***/ 6164 pSAREAPriv = DRIGetSAREAPrivate(xf86ScrnToScreen(pScrn)); 6165 /* can't get at sarea in a semi-sane way? */ 6166 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 6167 6168 if (crtc2) { 6169 pSAREAPriv->crtc2_base = Base; 6170 } 6171 else { 6172 pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) 6173 % info->CurrentLayout.displayWidth; 6174 pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) 6175 / info->CurrentLayout.displayWidth; 6176 pSAREA->frame.width = pScrn->frameX1 - x + 1; 6177 pSAREA->frame.height = pScrn->frameY1 - y + 1; 6178 } 6179 6180 if (pSAREAPriv->pfCurrentPage == 1) { 6181 Base += info->dri->backOffset - info->dri->frontOffset; 6182 } 6183 } 6184 #endif 6185 6186 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 6187 OUTREG(xytilereg, crtcxytile); 6188 } else { 6189 OUTREG(regcntl, crtcoffsetcntl); 6190 } 6191 6192 OUTREG(reg, Base); 6193 } 6194 6195 void RADEONAdjustFrame(ADJUST_FRAME_ARGS_DECL) 6196 { 6197 SCRN_INFO_PTR(arg); 6198 RADEONInfoPtr info = RADEONPTR(pScrn); 6199 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 6200 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 6201 xf86OutputPtr output = config->output[config->compat_output]; 6202 xf86CrtcPtr crtc = output->crtc; 6203 6204 /* not handled */ 6205 if (IS_AVIVO_VARIANT) 6206 return; 6207 6208 #ifdef XF86DRI 6209 if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 6210 #endif 6211 6212 if (info->accelOn) 6213 RADEON_SYNC(info, pScrn); 6214 6215 if (crtc && crtc->enabled) { 6216 if (crtc == pRADEONEnt->pCrtc[0]) 6217 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, FALSE); 6218 else 6219 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, TRUE); 6220 crtc->x = output->initial_x + x; 6221 crtc->y = output->initial_y + y; 6222 } 6223 6224 6225 #ifdef XF86DRI 6226 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 6227 #endif 6228 } 6229 6230 /* Called when VT switching back to the X server. Reinitialize the 6231 * video mode. 6232 */ 6233 Bool RADEONEnterVT(VT_FUNC_ARGS_DECL) 6234 { 6235 SCRN_INFO_PTR(arg); 6236 RADEONInfoPtr info = RADEONPTR(pScrn); 6237 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 6238 int i; 6239 6240 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6241 "RADEONEnterVT\n"); 6242 6243 if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */ 6244 if (info->IsAtomBios) { 6245 rhdAtomASICInit(info->atomBIOS); 6246 } else { 6247 xf86Int10InfoPtr pInt; 6248 6249 pInt = xf86InitInt10 (info->pEnt->index); 6250 if (pInt) { 6251 pInt->num = 0xe6; 6252 xf86ExecX86int10 (pInt); 6253 xf86FreeInt10 (pInt); 6254 } else { 6255 RADEONGetBIOSInitTableOffsets(pScrn); 6256 RADEONPostCardFromBIOSTables(pScrn); 6257 } 6258 } 6259 } 6260 6261 /* Makes sure the engine is idle before doing anything */ 6262 RADEONWaitForIdleMMIO(pScrn); 6263 6264 RADEONPMEnterVT(pScrn); 6265 6266 for (i = 0; i < config->num_crtc; i++) 6267 radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); 6268 6269 pScrn->vtSema = TRUE; 6270 6271 /* Clear the framebuffer */ 6272 memset(info->FB + pScrn->fbOffset, 0, 6273 pScrn->virtualY * pScrn->displayWidth * info->CurrentLayout.pixel_bytes); 6274 6275 if (!xf86SetDesiredModes(pScrn)) 6276 return FALSE; 6277 6278 if (info->ChipFamily < CHIP_FAMILY_R600) 6279 RADEONRestoreSurfaces(pScrn, info->ModeReg); 6280 #ifdef XF86DRI 6281 if (info->directRenderingEnabled) { 6282 if (info->cardType == CARD_PCIE && 6283 info->dri->pKernelDRMVersion->version_minor >= 19 && 6284 info->FbSecureSize) { 6285 #if X_BYTE_ORDER == X_BIG_ENDIAN 6286 unsigned char *RADEONMMIO = info->MMIO; 6287 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); 6288 6289 /* we need to backup the PCIE GART TABLE from fb memory */ 6290 OUTREG(RADEON_SURFACE_CNTL, 0); 6291 #endif 6292 memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize); 6293 #if X_BYTE_ORDER == X_BIG_ENDIAN 6294 OUTREG(RADEON_SURFACE_CNTL, sctrl); 6295 #endif 6296 } 6297 6298 /* get the DRI back into shape after resume */ 6299 RADEONDRISetVBlankInterrupt (pScrn, TRUE); 6300 RADEONDRIResume(pScrn->pScreen); 6301 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 6302 6303 } 6304 #endif 6305 /* this will get XVideo going again, but only if XVideo was initialised 6306 during server startup (hence the info->adaptor if). */ 6307 if (info->adaptor) 6308 RADEONResetVideo(pScrn); 6309 6310 if (info->accelOn && (info->ChipFamily < CHIP_FAMILY_R600)) 6311 RADEONEngineRestore(pScrn); 6312 6313 if (info->accelOn && info->accel_state) 6314 info->accel_state->XInited3D = FALSE; 6315 6316 #ifdef XF86DRI 6317 if (info->directRenderingEnabled) { 6318 if (info->ChipFamily >= CHIP_FAMILY_R600) 6319 R600LoadShaders(pScrn); 6320 RADEONCP_START(pScrn, info); 6321 DRIUnlock(pScrn->pScreen); 6322 } 6323 #endif 6324 if (IS_R500_3D || IS_R300_3D) 6325 radeon_load_bicubic_texture(pScrn); 6326 6327 return TRUE; 6328 } 6329 6330 /* Called when VT switching away from the X server. Restore the 6331 * original text mode. 6332 */ 6333 void RADEONLeaveVT(VT_FUNC_ARGS_DECL) 6334 { 6335 SCRN_INFO_PTR(arg); 6336 RADEONInfoPtr info = RADEONPTR(pScrn); 6337 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 6338 int i; 6339 6340 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6341 "RADEONLeaveVT\n"); 6342 #ifdef XF86DRI 6343 if (RADEONPTR(pScrn)->directRenderingInited) { 6344 6345 RADEONDRISetVBlankInterrupt (pScrn, FALSE); 6346 DRILock(pScrn->pScreen, 0); 6347 RADEONCP_STOP(pScrn, info); 6348 6349 if (info->cardType == CARD_PCIE && 6350 info->dri->pKernelDRMVersion->version_minor >= 19 && 6351 info->FbSecureSize) { 6352 #if X_BYTE_ORDER == X_BIG_ENDIAN 6353 unsigned char *RADEONMMIO = info->MMIO; 6354 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); 6355 6356 /* we need to backup the PCIE GART TABLE from fb memory */ 6357 OUTREG(RADEON_SURFACE_CNTL, 0); 6358 #endif 6359 memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize); 6360 #if X_BYTE_ORDER == X_BIG_ENDIAN 6361 OUTREG(RADEON_SURFACE_CNTL, sctrl); 6362 #endif 6363 } 6364 6365 /* Make sure 3D clients will re-upload textures to video RAM */ 6366 if (info->dri->textureSize) { 6367 drm_radeon_sarea_t *pSAREAPriv = 6368 (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScrn->pScreen); 6369 struct drm_tex_region *list = pSAREAPriv->tex_list[0]; 6370 int age = ++pSAREAPriv->tex_age[0]; 6371 6372 i = 0; 6373 6374 do { 6375 list[i].age = age; 6376 i = list[i].next; 6377 } while (i != 0); 6378 } 6379 } 6380 #endif 6381 6382 6383 for (i = 0; i < config->num_crtc; i++) { 6384 xf86CrtcPtr crtc = config->crtc[i]; 6385 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 6386 6387 radeon_crtc->initialized = FALSE; 6388 6389 #ifndef HAVE_FREE_SHADOW 6390 if (crtc->rotatedPixmap || crtc->rotatedData) { 6391 crtc->funcs->shadow_destroy(crtc, crtc->rotatedPixmap, 6392 crtc->rotatedData); 6393 crtc->rotatedPixmap = NULL; 6394 crtc->rotatedData = NULL; 6395 } 6396 #endif 6397 } 6398 6399 #ifdef HAVE_FREE_SHADOW 6400 xf86RotateFreeShadow(pScrn); 6401 #endif 6402 6403 xf86_hide_cursors (pScrn); 6404 6405 RADEONPMLeaveVT(pScrn); 6406 6407 RADEONRestore(pScrn); 6408 6409 for (i = 0; i < config->num_crtc; i++) 6410 radeon_crtc_modeset_ioctl(config->crtc[i], FALSE); 6411 6412 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6413 "Ok, leaving now...\n"); 6414 } 6415 6416 /* Called at the end of each server generation. Restore the original 6417 * text mode, unmap video memory, and unwrap and call the saved 6418 * CloseScreen function. 6419 */ 6420 static Bool RADEONCloseScreen(CLOSE_SCREEN_ARGS_DECL) 6421 { 6422 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 6423 RADEONInfoPtr info = RADEONPTR(pScrn); 6424 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 6425 int i; 6426 6427 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6428 "RADEONCloseScreen\n"); 6429 6430 RADEONPMFini(pScrn); 6431 6432 /* Mark acceleration as stopped or we might try to access the engine at 6433 * wrong times, especially if we had DRI, after DRI has been stopped 6434 */ 6435 info->accelOn = FALSE; 6436 6437 for (i = 0; i < config->num_crtc; i++) { 6438 xf86CrtcPtr crtc = config->crtc[i]; 6439 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 6440 6441 radeon_crtc->initialized = FALSE; 6442 } 6443 6444 #ifdef XF86DRI 6445 #ifdef DAMAGE 6446 if (info->dri && info->dri->pDamage) { 6447 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 6448 6449 #if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,15,0,0,0) 6450 DamageUnregister(info->dri->pDamage); 6451 #else 6452 DamageUnregister(&pPix->drawable, info->dri->pDamage); 6453 #endif 6454 DamageDestroy(info->dri->pDamage); 6455 info->dri->pDamage = NULL; 6456 } 6457 #endif 6458 6459 RADEONDRIStop(pScreen); 6460 #endif 6461 6462 #ifdef USE_XAA 6463 if(!info->useEXA && info->accel_state->RenderTex) { 6464 xf86FreeOffscreenLinear(info->accel_state->RenderTex); 6465 info->accel_state->RenderTex = NULL; 6466 } 6467 #endif /* USE_XAA */ 6468 6469 if (pScrn->vtSema) { 6470 RADEONRestore(pScrn); 6471 } 6472 6473 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6474 "Disposing accel...\n"); 6475 #ifdef USE_EXA 6476 if (info->accel_state->exa) { 6477 exaDriverFini(pScreen); 6478 free(info->accel_state->exa); 6479 info->accel_state->exa = NULL; 6480 } 6481 #endif /* USE_EXA */ 6482 #ifdef USE_XAA 6483 if (!info->useEXA) { 6484 if (info->accel_state->accel) 6485 XAADestroyInfoRec(info->accel_state->accel); 6486 info->accel_state->accel = NULL; 6487 6488 if (info->accel_state->scratch_save) 6489 free(info->accel_state->scratch_save); 6490 info->accel_state->scratch_save = NULL; 6491 } 6492 #endif /* USE_XAA */ 6493 6494 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6495 "Disposing cursor info\n"); 6496 if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); 6497 info->cursor = NULL; 6498 6499 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6500 "Unmapping memory\n"); 6501 RADEONUnmapMem(pScrn); 6502 6503 pScrn->vtSema = FALSE; 6504 6505 xf86ClearPrimInitDone(info->pEnt->index); 6506 6507 pScreen->BlockHandler = info->BlockHandler; 6508 pScreen->CloseScreen = info->CloseScreen; 6509 return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS); 6510 } 6511 6512 void RADEONFreeScreen(FREE_SCREEN_ARGS_DECL) 6513 { 6514 SCRN_INFO_PTR(arg); 6515 RADEONInfoPtr info = RADEONPTR(pScrn); 6516 6517 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6518 "RADEONFreeScreen\n"); 6519 6520 /* when server quits at PreInit, we don't need do this anymore*/ 6521 if (!info) return; 6522 6523 #ifdef WITH_VGAHW 6524 if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec")) 6525 vgaHWFreeHWRec(pScrn); 6526 #endif 6527 RADEONFreeRec(pScrn); 6528 } 6529
Indexes created Sun Jul 19 00:25:04 UTC 2026