1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation on the rights to use, copy, modify, merge, 10 * publish, distribute, sublicense, and/or sell copies of the Software, 11 * and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial 16 * portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 21 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR 22 * AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Author: Alex Deucher <alexander.deucher (at) amd.com> 28 * 29 */ 30 31 #ifdef HAVE_CONFIG_H 32 #include "config.h" 33 #endif 34 35 /* Driver data structures */ 36 #include "radeon.h" 37 #include "radeon_reg.h" 38 #include "radeon_macros.h" 39 #include "radeon_atombios.h" 40 41 #include "ati_pciids_gen.h" 42 43 /* 10 khz */ 44 static uint32_t calc_eng_mem_clock(ScrnInfoPtr pScrn, 45 uint32_t req_clock, 46 int ref_div, 47 int *fb_div, 48 int *post_div) 49 { 50 RADEONInfoPtr info = RADEONPTR(pScrn); 51 RADEONPLLPtr pll = &info->pll; 52 53 if (req_clock < 15000) { 54 *post_div = 8; 55 req_clock *= 8; 56 } else if (req_clock < 30000) { 57 *post_div = 4; 58 req_clock *= 4; 59 } else if (req_clock < 60000) { 60 *post_div = 2; 61 req_clock *= 2; 62 } else 63 *post_div = 1; 64 65 req_clock *= ref_div; 66 req_clock += pll->reference_freq; 67 req_clock /= (2 * pll->reference_freq); 68 69 *fb_div = req_clock & 0xff; 70 71 req_clock = (req_clock & 0xffff) << 1; 72 req_clock *= pll->reference_freq; 73 req_clock /= ref_div; 74 req_clock /= *post_div; 75 76 return req_clock; 77 78 } 79 80 static void 81 RADEONSetEngineClock(ScrnInfoPtr pScrn, uint32_t eng_clock) 82 { 83 uint32_t tmp; 84 int ref_div, fb_div, post_div; 85 86 RADEONWaitForIdleMMIO(pScrn); 87 88 tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV); 89 ref_div = tmp & RADEON_M_SPLL_REF_DIV_MASK; 90 91 eng_clock = calc_eng_mem_clock(pScrn, eng_clock, ref_div, &fb_div, &post_div); 92 93 tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL); 94 tmp &= ~RADEON_DONT_USE_XTALIN; 95 OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp); 96 97 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 98 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; 99 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 100 101 usleep(10); 102 103 tmp = INPLL(pScrn, RADEON_SPLL_CNTL); 104 tmp |= RADEON_SPLL_SLEEP; 105 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); 106 107 usleep(2); 108 109 tmp = INPLL(pScrn, RADEON_SPLL_CNTL); 110 tmp |= RADEON_SPLL_RESET; 111 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); 112 113 usleep(200); 114 115 tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV); 116 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); 117 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; 118 OUTPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV, tmp); 119 120 /* XXX: verify on different asics */ 121 tmp = INPLL(pScrn, RADEON_SPLL_CNTL); 122 tmp &= ~RADEON_SPLL_PVG_MASK; 123 if ((eng_clock * post_div) >= 90000) 124 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); 125 else 126 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); 127 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); 128 129 tmp = INPLL(pScrn, RADEON_SPLL_CNTL); 130 tmp &= ~RADEON_SPLL_SLEEP; 131 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); 132 133 usleep(2); 134 135 tmp = INPLL(pScrn, RADEON_SPLL_CNTL); 136 tmp &= ~RADEON_SPLL_RESET; 137 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); 138 139 usleep(200); 140 141 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 142 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; 143 switch (post_div) { 144 case 1: 145 default: 146 tmp |= 1; 147 break; 148 case 2: 149 tmp |= 2; 150 break; 151 case 4: 152 tmp |= 3; 153 break; 154 case 8: 155 tmp |= 4; 156 break; 157 } 158 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 159 160 usleep(20); 161 162 tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL); 163 tmp |= RADEON_DONT_USE_XTALIN; 164 OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp); 165 166 usleep(10); 167 168 } 169 170 static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable) 171 { 172 RADEONInfoPtr info = RADEONPTR(pScrn); 173 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 174 unsigned char *RADEONMMIO = info->MMIO; 175 uint32_t tmp; 176 177 if (enable) { 178 if (!pRADEONEnt->HasCRTC2) { 179 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 180 if ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) > 181 RADEON_CFG_ATI_REV_A13) { 182 tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB); 183 } 184 tmp &= ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 185 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | 186 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | 187 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | 188 RADEON_SCLK_FORCE_TDM); 189 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 190 } else if (IS_R300_VARIANT) { 191 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 192 (info->ChipFamily == CHIP_FAMILY_RS480)) { 193 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 194 tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 195 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 196 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 197 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 198 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 199 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 200 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 201 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 202 tmp |= RADEON_DYN_STOP_LAT_MASK; 203 tmp |= RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_VIP; 204 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 205 206 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 207 tmp &= ~RADEON_SCLK_MORE_FORCEON; 208 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; 209 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 210 211 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 212 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 213 RADEON_PIXCLK_DAC_ALWAYS_ONb); 214 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 215 216 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 217 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 218 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 219 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 220 R300_DVOCLK_ALWAYS_ONb | 221 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 222 RADEON_PIXCLK_GV_ALWAYS_ONb | 223 R300_PIXCLK_DVO_ALWAYS_ONb | 224 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 225 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 226 R300_PIXCLK_TRANS_ALWAYS_ONb | 227 R300_PIXCLK_TVO_ALWAYS_ONb | 228 R300_P2G2CLK_ALWAYS_ONb | 229 R300_P2G2CLK_DAC_ALWAYS_ONb); 230 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 231 } else if (info->ChipFamily >= CHIP_FAMILY_RV350) { 232 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 233 tmp &= ~(R300_SCLK_FORCE_TCL | 234 R300_SCLK_FORCE_GA | 235 R300_SCLK_FORCE_CBA); 236 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | 237 R300_SCLK_GA_MAX_DYN_STOP_LAT | 238 R300_SCLK_CBA_MAX_DYN_STOP_LAT); 239 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 240 241 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 242 tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 243 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 244 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 245 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 246 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 247 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 248 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 249 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 250 tmp |= RADEON_DYN_STOP_LAT_MASK; 251 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 252 253 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 254 tmp &= ~RADEON_SCLK_MORE_FORCEON; 255 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; 256 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 257 258 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 259 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 260 RADEON_PIXCLK_DAC_ALWAYS_ONb); 261 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 262 263 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 264 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 265 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 266 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 267 R300_DVOCLK_ALWAYS_ONb | 268 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 269 RADEON_PIXCLK_GV_ALWAYS_ONb | 270 R300_PIXCLK_DVO_ALWAYS_ONb | 271 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 272 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 273 R300_PIXCLK_TRANS_ALWAYS_ONb | 274 R300_PIXCLK_TVO_ALWAYS_ONb | 275 R300_P2G2CLK_ALWAYS_ONb | 276 R300_P2G2CLK_DAC_ALWAYS_ONb); 277 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 278 279 tmp = INPLL(pScrn, RADEON_MCLK_MISC); 280 tmp |= (RADEON_MC_MCLK_DYN_ENABLE | 281 RADEON_IO_MCLK_DYN_ENABLE); 282 OUTPLL(pScrn, RADEON_MCLK_MISC, tmp); 283 284 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 285 tmp |= (RADEON_FORCEON_MCLKA | 286 RADEON_FORCEON_MCLKB); 287 288 tmp &= ~(RADEON_FORCEON_YCLKA | 289 RADEON_FORCEON_YCLKB | 290 RADEON_FORCEON_MC); 291 292 /* Some releases of vbios have set DISABLE_MC_MCLKA 293 and DISABLE_MC_MCLKB bits in the vbios table. Setting these 294 bits will cause H/W hang when reading video memory with dynamic clocking 295 enabled. */ 296 if ((tmp & R300_DISABLE_MC_MCLKA) && 297 (tmp & R300_DISABLE_MC_MCLKB)) { 298 /* If both bits are set, then check the active channels */ 299 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 300 if (info->RamWidth == 64) { 301 if (INREG(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) 302 tmp &= ~R300_DISABLE_MC_MCLKB; 303 else 304 tmp &= ~R300_DISABLE_MC_MCLKA; 305 } else { 306 tmp &= ~(R300_DISABLE_MC_MCLKA | 307 R300_DISABLE_MC_MCLKB); 308 } 309 } 310 311 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); 312 } else { 313 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 314 tmp &= ~(R300_SCLK_FORCE_VAP); 315 tmp |= RADEON_SCLK_FORCE_CP; 316 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 317 usleep(15000); 318 319 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 320 tmp &= ~(R300_SCLK_FORCE_TCL | 321 R300_SCLK_FORCE_GA | 322 R300_SCLK_FORCE_CBA); 323 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 324 } 325 } else { 326 tmp = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); 327 328 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | 329 RADEON_DISP_DYN_STOP_LAT_MASK | 330 RADEON_DYN_STOP_MODE_MASK); 331 332 tmp |= (RADEON_ENGIN_DYNCLK_MODE | 333 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); 334 OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, tmp); 335 usleep(15000); 336 337 tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL); 338 tmp |= RADEON_SCLK_DYN_START_CNTL; 339 OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp); 340 usleep(15000); 341 342 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 343 to lockup randomly, leave them as set by BIOS. 344 */ 345 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 346 /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/ 347 tmp &= ~RADEON_SCLK_FORCEON_MASK; 348 349 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/ 350 if (((info->ChipFamily == CHIP_FAMILY_RV250) && 351 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < 352 RADEON_CFG_ATI_REV_A13)) || 353 ((info->ChipFamily == CHIP_FAMILY_RV100) && 354 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <= 355 RADEON_CFG_ATI_REV_A13))) { 356 tmp |= RADEON_SCLK_FORCE_CP; 357 tmp |= RADEON_SCLK_FORCE_VIP; 358 } 359 360 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 361 362 if ((info->ChipFamily == CHIP_FAMILY_RV200) || 363 (info->ChipFamily == CHIP_FAMILY_RV250) || 364 (info->ChipFamily == CHIP_FAMILY_RV280)) { 365 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 366 tmp &= ~RADEON_SCLK_MORE_FORCEON; 367 368 /* RV200::A11 A12 RV250::A11 A12 */ 369 if (((info->ChipFamily == CHIP_FAMILY_RV200) || 370 (info->ChipFamily == CHIP_FAMILY_RV250)) && 371 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < 372 RADEON_CFG_ATI_REV_A13)) { 373 tmp |= RADEON_SCLK_MORE_FORCEON; 374 } 375 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 376 usleep(15000); 377 } 378 379 /* RV200::A11 A12, RV250::A11 A12 */ 380 if (((info->ChipFamily == CHIP_FAMILY_RV200) || 381 (info->ChipFamily == CHIP_FAMILY_RV250)) && 382 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < 383 RADEON_CFG_ATI_REV_A13)) { 384 tmp = INPLL(pScrn, RADEON_PLL_PWRMGT_CNTL); 385 tmp |= RADEON_TCL_BYPASS_DISABLE; 386 OUTPLL(pScrn, RADEON_PLL_PWRMGT_CNTL, tmp); 387 } 388 usleep(15000); 389 390 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/ 391 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 392 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 393 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 394 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 395 RADEON_PIXCLK_GV_ALWAYS_ONb | 396 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | 397 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 398 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 399 400 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 401 usleep(15000); 402 403 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 404 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 405 RADEON_PIXCLK_DAC_ALWAYS_ONb); 406 407 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 408 usleep(15000); 409 } 410 } else { 411 /* Turn everything OFF (ForceON to everything)*/ 412 if ( !pRADEONEnt->HasCRTC2 ) { 413 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 414 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | 415 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP | 416 RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | 417 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | 418 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | 419 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | 420 RADEON_SCLK_FORCE_RB); 421 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 422 } else if ((info->ChipFamily == CHIP_FAMILY_RS400) || 423 (info->ChipFamily == CHIP_FAMILY_RS480)) { 424 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 425 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 426 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 427 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 428 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 429 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 430 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 431 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 432 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 433 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 434 435 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 436 tmp |= RADEON_SCLK_MORE_FORCEON; 437 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 438 439 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 440 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 441 RADEON_PIXCLK_DAC_ALWAYS_ONb | 442 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); 443 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 444 445 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 446 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 447 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 448 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 449 R300_DVOCLK_ALWAYS_ONb | 450 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 451 RADEON_PIXCLK_GV_ALWAYS_ONb | 452 R300_PIXCLK_DVO_ALWAYS_ONb | 453 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 454 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 455 R300_PIXCLK_TRANS_ALWAYS_ONb | 456 R300_PIXCLK_TVO_ALWAYS_ONb | 457 R300_P2G2CLK_ALWAYS_ONb | 458 R300_P2G2CLK_DAC_ALWAYS_ONb | 459 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); 460 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 461 } else if (info->ChipFamily >= CHIP_FAMILY_RV350) { 462 /* for RV350/M10, no delays are required. */ 463 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 464 tmp |= (R300_SCLK_FORCE_TCL | 465 R300_SCLK_FORCE_GA | 466 R300_SCLK_FORCE_CBA); 467 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 468 469 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 470 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 471 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 472 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 473 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 474 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 475 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 476 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 477 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 478 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 479 480 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 481 tmp |= RADEON_SCLK_MORE_FORCEON; 482 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 483 484 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 485 tmp |= (RADEON_FORCEON_MCLKA | 486 RADEON_FORCEON_MCLKB | 487 RADEON_FORCEON_YCLKA | 488 RADEON_FORCEON_YCLKB | 489 RADEON_FORCEON_MC); 490 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); 491 492 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 493 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 494 RADEON_PIXCLK_DAC_ALWAYS_ONb | 495 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); 496 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 497 498 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 499 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 500 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 501 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 502 R300_DVOCLK_ALWAYS_ONb | 503 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 504 RADEON_PIXCLK_GV_ALWAYS_ONb | 505 R300_PIXCLK_DVO_ALWAYS_ONb | 506 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 507 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 508 R300_PIXCLK_TRANS_ALWAYS_ONb | 509 R300_PIXCLK_TVO_ALWAYS_ONb | 510 R300_P2G2CLK_ALWAYS_ONb | 511 R300_P2G2CLK_DAC_ALWAYS_ONb | 512 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); 513 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 514 } else { 515 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 516 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); 517 tmp |= RADEON_SCLK_FORCE_SE; 518 519 if ( !pRADEONEnt->HasCRTC2 ) { 520 tmp |= ( RADEON_SCLK_FORCE_RB | 521 RADEON_SCLK_FORCE_TDM | 522 RADEON_SCLK_FORCE_TAM | 523 RADEON_SCLK_FORCE_PB | 524 RADEON_SCLK_FORCE_RE | 525 RADEON_SCLK_FORCE_VIP | 526 RADEON_SCLK_FORCE_IDCT | 527 RADEON_SCLK_FORCE_TOP | 528 RADEON_SCLK_FORCE_DISP1 | 529 RADEON_SCLK_FORCE_DISP2 | 530 RADEON_SCLK_FORCE_HDP ); 531 } else if ((info->ChipFamily == CHIP_FAMILY_R300) || 532 (info->ChipFamily == CHIP_FAMILY_R350)) { 533 tmp |= ( RADEON_SCLK_FORCE_HDP | 534 RADEON_SCLK_FORCE_DISP1 | 535 RADEON_SCLK_FORCE_DISP2 | 536 RADEON_SCLK_FORCE_TOP | 537 RADEON_SCLK_FORCE_IDCT | 538 RADEON_SCLK_FORCE_VIP); 539 } 540 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 541 542 usleep(16000); 543 544 if ((info->ChipFamily == CHIP_FAMILY_R300) || 545 (info->ChipFamily == CHIP_FAMILY_R350)) { 546 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 547 tmp |= ( R300_SCLK_FORCE_TCL | 548 R300_SCLK_FORCE_GA | 549 R300_SCLK_FORCE_CBA); 550 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 551 usleep(16000); 552 } 553 554 if (info->IsIGP) { 555 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 556 tmp &= ~(RADEON_FORCEON_MCLKA | 557 RADEON_FORCEON_YCLKA); 558 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); 559 usleep(16000); 560 } 561 562 if ((info->ChipFamily == CHIP_FAMILY_RV200) || 563 (info->ChipFamily == CHIP_FAMILY_RV250) || 564 (info->ChipFamily == CHIP_FAMILY_RV280)) { 565 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 566 tmp |= RADEON_SCLK_MORE_FORCEON; 567 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 568 usleep(16000); 569 } 570 571 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 572 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 573 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 574 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 575 RADEON_PIXCLK_GV_ALWAYS_ONb | 576 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | 577 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 578 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 579 580 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 581 usleep(16000); 582 583 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 584 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 585 RADEON_PIXCLK_DAC_ALWAYS_ONb); 586 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 587 } 588 } 589 } 590 591 static void RADEONPMQuirks(ScrnInfoPtr pScrn) 592 { 593 RADEONInfoPtr info = RADEONPTR(pScrn); 594 uint32_t tmp; 595 596 RADEONWaitForIdleMMIO(pScrn); 597 598 if (info->ChipFamily < CHIP_FAMILY_RV515) { 599 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 600 if (IS_R300_VARIANT || IS_RV100_VARIANT) 601 tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; 602 if ((info->ChipFamily == CHIP_FAMILY_RV250) || (info->ChipFamily == CHIP_FAMILY_RV280)) 603 tmp |= RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2; 604 if ((info->ChipFamily == CHIP_FAMILY_RV350) || (info->ChipFamily == CHIP_FAMILY_RV380)) 605 tmp |= R300_SCLK_FORCE_VAP; 606 if (info->ChipFamily == CHIP_FAMILY_R420) 607 tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX; 608 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 609 } else if (info->ChipFamily < CHIP_FAMILY_R600) { 610 tmp = INPLL(pScrn, AVIVO_CP_DYN_CNTL); 611 tmp |= AVIVO_CP_FORCEON; 612 OUTPLL(pScrn, AVIVO_CP_DYN_CNTL, tmp); 613 614 tmp = INPLL(pScrn, AVIVO_E2_DYN_CNTL); 615 tmp |= AVIVO_E2_FORCEON; 616 OUTPLL(pScrn, AVIVO_E2_DYN_CNTL, tmp); 617 618 tmp = INPLL(pScrn, AVIVO_IDCT_DYN_CNTL); 619 tmp |= AVIVO_IDCT_FORCEON; 620 OUTPLL(pScrn, AVIVO_IDCT_DYN_CNTL, tmp); 621 } 622 } 623 624 static void 625 RADEONSetPCIELanes(ScrnInfoPtr pScrn, int lanes) 626 { 627 RADEONInfoPtr info = RADEONPTR(pScrn); 628 unsigned char *RADEONMMIO = info->MMIO; 629 uint32_t link_width_cntl, mask, target_reg; 630 631 if (info->IsIGP) 632 return; 633 634 /* don't change lanes on multi-gpu cards for now */ 635 if ((info->Chipset == PCI_CHIP_RV770_9441) || 636 (info->Chipset == PCI_CHIP_RV770_9443) || 637 (info->Chipset == PCI_CHIP_RV770_944B) || 638 (info->Chipset == PCI_CHIP_RV670_9506) || 639 (info->Chipset == PCI_CHIP_RV670_9509) || 640 (info->Chipset == PCI_CHIP_RV670_950F)) 641 return; 642 643 RADEONWaitForIdleMMIO(pScrn); 644 645 switch (lanes) { 646 case 0: 647 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 648 break; 649 case 1: 650 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 651 break; 652 case 2: 653 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 654 break; 655 case 4: 656 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 657 break; 658 case 8: 659 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 660 break; 661 case 12: 662 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 663 break; 664 case 16: 665 default: 666 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 667 break; 668 } 669 670 if (info->ChipFamily >= CHIP_FAMILY_R600) { 671 link_width_cntl = INPCIE_P(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL); 672 673 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 674 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 675 return; 676 677 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 678 RADEON_PCIE_LC_RECONFIG_NOW | 679 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE | 680 R600_PCIE_LC_SHORT_RECONFIG_EN | 681 R600_PCIE_LC_RENEGOTIATE_EN); 682 link_width_cntl |= mask; 683 684 #if 0 685 /* some northbridges can renegotiate the link rather than requiring 686 * a complete re-config. 687 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) 688 */ 689 if (northbridge can renegotiate) 690 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN; 691 else 692 #endif 693 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; 694 695 OUTPCIE_P(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 696 OUTPCIE_P(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW); 697 698 if (info->ChipFamily >= CHIP_FAMILY_RV770) 699 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; 700 else 701 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; 702 703 /* wait for lane set to complete */ 704 link_width_cntl = INREG(target_reg); 705 while (link_width_cntl == 0xffffffff) 706 link_width_cntl = INREG(target_reg); 707 708 } else { 709 link_width_cntl = INPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL); 710 711 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 712 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 713 return; 714 715 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 716 RADEON_PCIE_LC_RECONFIG_NOW | 717 RADEON_PCIE_LC_RECONFIG_LATER | 718 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 719 link_width_cntl |= mask; 720 OUTPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 721 OUTPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW); 722 723 /* wait for lane set to complete */ 724 link_width_cntl = INPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL); 725 while (link_width_cntl == 0xffffffff) 726 link_width_cntl = INPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL); 727 728 } 729 730 } 731 732 static void 733 RADEONSetClockGating(ScrnInfoPtr pScrn, Bool enable) 734 { 735 RADEONInfoPtr info = RADEONPTR(pScrn); 736 737 RADEONWaitForIdleMMIO(pScrn); 738 739 if (info->ChipFamily >= CHIP_FAMILY_R600) 740 atombios_static_pwrmgt_setup(pScrn, enable); 741 else { 742 if (info->IsAtomBios) { 743 atombios_static_pwrmgt_setup(pScrn, enable); 744 atombios_clk_gating_setup(pScrn, enable); 745 } else if (info->IsMobility) 746 LegacySetClockGating(pScrn, enable); 747 } 748 749 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Gating %sabled\n", 750 enable ? "En" : "Dis"); 751 } 752 753 static void RADEONSetStaticPowerMode(ScrnInfoPtr pScrn, RADEONPMType type) 754 { 755 RADEONInfoPtr info = RADEONPTR(pScrn); 756 int i; 757 758 for (i = 0; i < info->pm.num_modes; i++) { 759 if (info->pm.mode[i].type == type) 760 break; 761 } 762 763 if (i == info->pm.num_modes) 764 return; 765 766 if (i == info->pm.current_mode) 767 return; 768 769 RADEONWaitForIdleMMIO(pScrn); 770 771 if (info->IsAtomBios) 772 atombios_set_engine_clock(pScrn, info->pm.mode[i].sclk); 773 else 774 RADEONSetEngineClock(pScrn, info->pm.mode[i].sclk); 775 776 if (info->cardType == CARD_PCIE) 777 RADEONSetPCIELanes(pScrn, info->pm.mode[i].pcie_lanes); 778 779 info->pm.current_mode = i; 780 781 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Power Mode Switch\n"); 782 } 783 784 785 void RADEONPMInit(ScrnInfoPtr pScrn) 786 { 787 RADEONInfoPtr info = RADEONPTR(pScrn); 788 789 if (xf86ReturnOptValBool(info->Options, OPTION_CLOCK_GATING, FALSE)) { 790 info->pm.clock_gating_enabled = TRUE; 791 RADEONSetClockGating(pScrn, info->pm.clock_gating_enabled); 792 } else 793 info->pm.clock_gating_enabled = FALSE; 794 795 info->pm.mode[0].type = POWER_DEFAULT; 796 info->pm.mode[0].sclk = (uint32_t)info->sclk * 100; /* 10 khz */ 797 info->pm.mode[0].mclk = (uint32_t)info->mclk * 100; /* 10 khz */ 798 info->pm.mode[0].pcie_lanes = 16; /* XXX: read back current lane config */ 799 info->pm.current_mode = 0; 800 info->pm.num_modes = 1; 801 802 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_PM, FALSE)) { 803 info->pm.dynamic_mode_enabled = TRUE; 804 info->pm.mode[1].type = POWER_LOW; 805 info->pm.mode[1].sclk = info->pm.mode[0].sclk / 4; 806 info->pm.mode[1].mclk = info->pm.mode[0].mclk / 4; 807 info->pm.mode[1].pcie_lanes = 1; 808 809 info->pm.mode[2].type = POWER_HIGH; 810 info->pm.mode[2].sclk = info->pm.mode[0].sclk; 811 info->pm.mode[2].mclk = info->pm.mode[0].mclk; 812 info->pm.mode[2].pcie_lanes = 16; 813 814 info->pm.num_modes += 2; 815 816 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Power Management Enabled\n"); 817 } else { 818 info->pm.dynamic_mode_enabled = FALSE; 819 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Power Management Disabled\n"); 820 } 821 822 if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_LOW_POWER, FALSE)) { 823 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Force Low Power Mode Enabled\n"); 824 info->pm.force_low_power_enabled = TRUE; 825 if (info->pm.dynamic_mode_enabled) { 826 info->pm.mode[2].type = POWER_HIGH; 827 info->pm.mode[2].sclk = info->pm.mode[0].sclk / 2; 828 info->pm.mode[2].mclk = info->pm.mode[0].mclk / 2; 829 info->pm.mode[2].pcie_lanes = 4; 830 } else { 831 info->pm.mode[1].type = POWER_HIGH; 832 info->pm.mode[1].sclk = info->pm.mode[0].sclk / 2; 833 info->pm.mode[1].mclk = info->pm.mode[0].mclk / 2; 834 info->pm.mode[1].pcie_lanes = 4; 835 info->pm.num_modes += 1; 836 } 837 RADEONSetStaticPowerMode(pScrn, POWER_HIGH); 838 } else 839 info->pm.force_low_power_enabled = FALSE; 840 841 RADEONPMQuirks(pScrn); 842 } 843 844 void RADEONPMEnterVT(ScrnInfoPtr pScrn) 845 { 846 RADEONInfoPtr info = RADEONPTR(pScrn); 847 848 if (info->pm.clock_gating_enabled) 849 RADEONSetClockGating(pScrn, info->pm.clock_gating_enabled); 850 RADEONPMQuirks(pScrn); 851 if (info->pm.force_low_power_enabled || info->pm.dynamic_mode_enabled) 852 RADEONSetStaticPowerMode(pScrn, POWER_HIGH); 853 } 854 855 void RADEONPMLeaveVT(ScrnInfoPtr pScrn) 856 { 857 RADEONInfoPtr info = RADEONPTR(pScrn); 858 859 if (info->pm.clock_gating_enabled) 860 RADEONSetClockGating(pScrn, FALSE); 861 if (info->pm.force_low_power_enabled || info->pm.dynamic_mode_enabled) 862 RADEONSetStaticPowerMode(pScrn, POWER_DEFAULT); 863 } 864 865 void RADEONPMFini(ScrnInfoPtr pScrn) 866 { 867 RADEONInfoPtr info = RADEONPTR(pScrn); 868 869 if (info->pm.clock_gating_enabled) 870 RADEONSetClockGating(pScrn, FALSE); 871 if (info->pm.force_low_power_enabled || info->pm.dynamic_mode_enabled) 872 RADEONSetStaticPowerMode(pScrn, POWER_DEFAULT); 873 } 874 875 void RADEONPMBlockHandler(ScrnInfoPtr pScrn) 876 { 877 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 878 879 if ((!pRADEONEnt->Controller[0]->enabled) && 880 (!pRADEONEnt->Controller[1]->enabled)) 881 RADEONSetStaticPowerMode(pScrn, POWER_LOW); 882 else 883 RADEONSetStaticPowerMode(pScrn, POWER_HIGH); 884 885 } 886 887
Indexes created Mon Jul 20 00:27:07 UTC 2026