1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29 #ifdef HAVE_CONFIG_H 30 #include "config.h" 31 #endif 32 33 #include <string.h> 34 #include <stdio.h> 35 36 /* X and server generic header files */ 37 #include "xf86.h" 38 #include "xf86_OSproc.h" 39 #include "vgaHW.h" 40 #include "xf86Modes.h" 41 42 /* Driver data structures */ 43 #include "radeon.h" 44 #include "radeon_reg.h" 45 #include "radeon_macros.h" 46 #include "radeon_probe.h" 47 #include "radeon_version.h" 48 #include "radeon_atombios.h" 49 50 #ifdef XF86DRI 51 #define _XF86DRI_SERVER_ 52 #include "radeon_drm.h" 53 #include "sarea.h" 54 #ifdef DRM_IOCTL_MODESET_CTL 55 #include <sys/ioctl.h> 56 #endif 57 #endif 58 59 /* Write common registers */ 60 void 61 RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, 62 RADEONSavePtr restore) 63 { 64 RADEONInfoPtr info = RADEONPTR(pScrn); 65 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 66 unsigned char *RADEONMMIO = info->MMIO; 67 68 if (info->IsSecondary) 69 return; 70 71 OUTREG(RADEON_OVR_CLR, restore->ovr_clr); 72 OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right); 73 OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom); 74 OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl); 75 OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl); 76 OUTREG(RADEON_VIPH_CONTROL, restore->viph_control); 77 OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1); 78 OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl); 79 OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl); 80 OUTREG(RADEON_CAP1_TRIG_CNTL, restore->cap1_trig_cntl); 81 OUTREG(RADEON_BUS_CNTL, restore->bus_cntl); 82 OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl); 83 84 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 85 (info->ChipFamily == CHIP_FAMILY_RS480)) { 86 OUTREG(RS400_DISP2_REQ_CNTL1, restore->disp2_req_cntl1); 87 OUTREG(RS400_DISP2_REQ_CNTL2, restore->disp2_req_cntl2); 88 OUTREG(RS400_DMIF_MEM_CNTL1, restore->dmif_mem_cntl1); 89 OUTREG(RS400_DISP1_REQ_CNTL1, restore->disp1_req_cntl1); 90 } 91 92 /* Workaround for the VT switching problem in dual-head mode. This 93 * problem only occurs on RV style chips, typically when a FP and 94 * CRT are connected. 95 */ 96 if (pRADEONEnt->HasCRTC2 && 97 info->ChipFamily != CHIP_FAMILY_R200 && 98 !IS_R300_VARIANT) { 99 uint32_t tmp; 100 101 tmp = INREG(RADEON_DAC_CNTL2); 102 OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL); 103 usleep(100000); 104 } 105 } 106 107 void 108 RADEONRestoreCrtcBase(ScrnInfoPtr pScrn, 109 RADEONSavePtr restore) 110 { 111 RADEONInfoPtr info = RADEONPTR(pScrn); 112 unsigned char *RADEONMMIO = info->MMIO; 113 114 if (IS_R300_VARIANT) 115 OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0); 116 OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl); 117 OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset); 118 } 119 120 void 121 RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn, 122 RADEONSavePtr restore) 123 { 124 RADEONInfoPtr info = RADEONPTR(pScrn); 125 unsigned char *RADEONMMIO = info->MMIO; 126 127 if (IS_R300_VARIANT) 128 OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0); 129 OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl); 130 OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset); 131 } 132 133 /* Write CRTC registers */ 134 void 135 RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, 136 RADEONSavePtr restore) 137 { 138 RADEONInfoPtr info = RADEONPTR(pScrn); 139 unsigned char *RADEONMMIO = info->MMIO; 140 141 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 142 "Programming CRTC1, offset: 0x%08x\n", 143 (unsigned)restore->crtc_offset); 144 145 /* We prevent the CRTC from hitting the memory controller until 146 * fully programmed 147 */ 148 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl | 149 RADEON_CRTC_DISP_REQ_EN_B); 150 151 OUTREGP(RADEON_CRTC_EXT_CNTL, 152 restore->crtc_ext_cntl, 153 RADEON_CRTC_VSYNC_DIS | 154 RADEON_CRTC_HSYNC_DIS | 155 RADEON_CRTC_DISPLAY_DIS); 156 157 OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp); 158 OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid); 159 OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp); 160 OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid); 161 162 RADEONRestoreCrtcBase(pScrn, restore); 163 164 OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch); 165 OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl); 166 167 if (info->IsDellServer) { 168 OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); 169 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug); 170 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); 171 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); 172 } 173 174 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl); 175 } 176 177 /* Write CRTC2 registers */ 178 void 179 RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, 180 RADEONSavePtr restore) 181 { 182 RADEONInfoPtr info = RADEONPTR(pScrn); 183 unsigned char *RADEONMMIO = info->MMIO; 184 /* uint32_t crtc2_gen_cntl;*/ 185 186 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 187 "Programming CRTC2, offset: 0x%08x\n", 188 (unsigned)restore->crtc2_offset); 189 190 /* We prevent the CRTC from hitting the memory controller until 191 * fully programmed 192 */ 193 OUTREG(RADEON_CRTC2_GEN_CNTL, 194 restore->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS | 195 RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS | 196 RADEON_CRTC2_DISP_REQ_EN_B); 197 198 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp); 199 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid); 200 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp); 201 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid); 202 203 OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp_h2_sync_strt_wid); 204 OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp_v2_sync_strt_wid); 205 206 RADEONRestoreCrtc2Base(pScrn, restore); 207 208 OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); 209 OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); 210 211 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); 212 213 } 214 215 static void 216 RADEONPLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn) 217 { 218 int i = 0; 219 220 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 221 the cause yet, but this workaround will mask the problem for now. 222 Other chips usually will pass at the very first test, so the 223 workaround shouldn't have any effect on them. */ 224 for (i = 0; 225 (i < 10000 && 226 INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 227 i++); 228 } 229 230 static void 231 RADEONPLLWriteUpdate(ScrnInfoPtr pScrn) 232 { 233 while (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 234 235 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 236 RADEON_PPLL_ATOMIC_UPDATE_W, 237 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 238 } 239 240 static void 241 RADEONPLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn) 242 { 243 int i = 0; 244 245 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 246 the cause yet, but this workaround will mask the problem for now. 247 Other chips usually will pass at the very first test, so the 248 workaround shouldn't have any effect on them. */ 249 for (i = 0; 250 (i < 10000 && 251 INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 252 i++); 253 } 254 255 static void 256 RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) 257 { 258 while (INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 259 260 OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, 261 RADEON_P2PLL_ATOMIC_UPDATE_W, 262 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 263 } 264 265 static uint8_t 266 RADEONComputePLLGain(uint16_t reference_freq, uint16_t ref_div, 267 uint16_t fb_div) 268 { 269 unsigned vcoFreq; 270 271 if (!ref_div) 272 return 1; 273 274 vcoFreq = ((unsigned)reference_freq * fb_div) / ref_div; 275 276 /* 277 * This is horribly crude: the VCO frequency range is divided into 278 * 3 parts, each part having a fixed PLL gain value. 279 */ 280 if (vcoFreq >= 30000) 281 /* 282 * [300..max] MHz : 7 283 */ 284 return 7; 285 else if (vcoFreq >= 18000) 286 /* 287 * [180..300) MHz : 4 288 */ 289 return 4; 290 else 291 /* 292 * [0..180) MHz : 1 293 */ 294 return 1; 295 } 296 297 /* Write PLL registers */ 298 void 299 RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, 300 RADEONSavePtr restore) 301 { 302 RADEONInfoPtr info = RADEONPTR(pScrn); 303 unsigned char *RADEONMMIO = info->MMIO; 304 uint8_t pllGain; 305 306 #if defined(__powerpc__) 307 /* apparently restoring the pll causes a hang??? */ 308 if ((info->MacModel == RADEON_MAC_IBOOK) || 309 (info->MacModel == RADEON_MAC_MINI_INTERNAL)) 310 return; 311 #endif 312 313 pllGain = RADEONComputePLLGain(info->pll.reference_freq, 314 restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, 315 restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK); 316 317 if (info->IsMobility) { 318 /* A temporal workaround for the occational blanking on certain laptop panels. 319 This appears to related to the PLL divider registers (fail to lock?). 320 It occurs even when all dividers are the same with their old settings. 321 In this case we really don't need to fiddle with PLL registers. 322 By doing this we can avoid the blanking problem with some panels. 323 */ 324 if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 325 (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) & 326 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 327 OUTREGP(RADEON_CLOCK_CNTL_INDEX, 328 RADEON_PLL_DIV_SEL, 329 ~(RADEON_PLL_DIV_SEL)); 330 RADEONPllErrataAfterIndex(info); 331 return; 332 } 333 } 334 335 OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, 336 RADEON_VCLK_SRC_SEL_CPUCLK, 337 ~(RADEON_VCLK_SRC_SEL_MASK)); 338 339 OUTPLLP(pScrn, 340 RADEON_PPLL_CNTL, 341 RADEON_PPLL_RESET 342 | RADEON_PPLL_ATOMIC_UPDATE_EN 343 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 344 | ((uint32_t)pllGain << RADEON_PPLL_PVG_SHIFT), 345 ~(RADEON_PPLL_RESET 346 | RADEON_PPLL_ATOMIC_UPDATE_EN 347 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 348 | RADEON_PPLL_PVG_MASK)); 349 350 OUTREGP(RADEON_CLOCK_CNTL_INDEX, 351 RADEON_PLL_DIV_SEL, 352 ~(RADEON_PLL_DIV_SEL)); 353 RADEONPllErrataAfterIndex(info); 354 355 if (IS_R300_VARIANT || 356 (info->ChipFamily == CHIP_FAMILY_RS300) || 357 (info->ChipFamily == CHIP_FAMILY_RS400) || 358 (info->ChipFamily == CHIP_FAMILY_RS480)) { 359 if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 360 /* When restoring console mode, use saved PPLL_REF_DIV 361 * setting. 362 */ 363 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 364 restore->ppll_ref_div, 365 0); 366 } else { 367 /* R300 uses ref_div_acc field as real ref divider */ 368 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 369 (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 370 ~R300_PPLL_REF_DIV_ACC_MASK); 371 } 372 } else { 373 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 374 restore->ppll_ref_div, 375 ~RADEON_PPLL_REF_DIV_MASK); 376 } 377 378 OUTPLLP(pScrn, RADEON_PPLL_DIV_3, 379 restore->ppll_div_3, 380 ~RADEON_PPLL_FB3_DIV_MASK); 381 382 OUTPLLP(pScrn, RADEON_PPLL_DIV_3, 383 restore->ppll_div_3, 384 ~RADEON_PPLL_POST3_DIV_MASK); 385 386 RADEONPLLWriteUpdate(pScrn); 387 RADEONPLLWaitForReadUpdateComplete(pScrn); 388 389 OUTPLL(pScrn, RADEON_HTOTAL_CNTL, restore->htotal_cntl); 390 391 OUTPLLP(pScrn, RADEON_PPLL_CNTL, 392 0, 393 ~(RADEON_PPLL_RESET 394 | RADEON_PPLL_SLEEP 395 | RADEON_PPLL_ATOMIC_UPDATE_EN 396 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 397 398 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 399 "Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 400 restore->ppll_ref_div, 401 restore->ppll_div_3, 402 (unsigned)restore->htotal_cntl, 403 INPLL(pScrn, RADEON_PPLL_CNTL)); 404 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 405 "Wrote: rd=%d, fd=%d, pd=%d\n", 406 restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, 407 restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, 408 (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); 409 410 usleep(50000); /* Let the clock to lock */ 411 412 OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, 413 RADEON_VCLK_SRC_SEL_PPLLCLK, 414 ~(RADEON_VCLK_SRC_SEL_MASK)); 415 416 /*OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);*/ 417 418 ErrorF("finished PLL1\n"); 419 420 } 421 422 /* Write PLL2 registers */ 423 void 424 RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 425 RADEONSavePtr restore) 426 { 427 RADEONInfoPtr info = RADEONPTR(pScrn); 428 uint8_t pllGain; 429 430 pllGain = RADEONComputePLLGain(info->pll.reference_freq, 431 restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 432 restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK); 433 434 435 OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 436 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 437 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 438 439 OUTPLLP(pScrn, 440 RADEON_P2PLL_CNTL, 441 RADEON_P2PLL_RESET 442 | RADEON_P2PLL_ATOMIC_UPDATE_EN 443 | ((uint32_t)pllGain << RADEON_P2PLL_PVG_SHIFT), 444 ~(RADEON_P2PLL_RESET 445 | RADEON_P2PLL_ATOMIC_UPDATE_EN 446 | RADEON_P2PLL_PVG_MASK)); 447 448 449 OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, 450 restore->p2pll_ref_div, 451 ~RADEON_P2PLL_REF_DIV_MASK); 452 453 OUTPLLP(pScrn, RADEON_P2PLL_DIV_0, 454 restore->p2pll_div_0, 455 ~RADEON_P2PLL_FB0_DIV_MASK); 456 457 OUTPLLP(pScrn, RADEON_P2PLL_DIV_0, 458 restore->p2pll_div_0, 459 ~RADEON_P2PLL_POST0_DIV_MASK); 460 461 RADEONPLL2WriteUpdate(pScrn); 462 RADEONPLL2WaitForReadUpdateComplete(pScrn); 463 464 OUTPLL(pScrn, RADEON_HTOTAL2_CNTL, restore->htotal_cntl2); 465 466 OUTPLLP(pScrn, RADEON_P2PLL_CNTL, 467 0, 468 ~(RADEON_P2PLL_RESET 469 | RADEON_P2PLL_SLEEP 470 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 471 472 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 473 "Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 474 (unsigned)restore->p2pll_ref_div, 475 (unsigned)restore->p2pll_div_0, 476 (unsigned)restore->htotal_cntl2, 477 INPLL(pScrn, RADEON_P2PLL_CNTL)); 478 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 479 "Wrote2: rd=%u, fd=%u, pd=%u\n", 480 (unsigned)restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 481 (unsigned)restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, 482 (unsigned)((restore->p2pll_div_0 & 483 RADEON_P2PLL_POST0_DIV_MASK) >>16)); 484 485 usleep(5000); /* Let the clock to lock */ 486 487 OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 488 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 489 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 490 491 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); 492 493 ErrorF("finished PLL2\n"); 494 495 } 496 497 /* Read common registers */ 498 void 499 RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 500 { 501 RADEONInfoPtr info = RADEONPTR(pScrn); 502 unsigned char *RADEONMMIO = info->MMIO; 503 504 save->ovr_clr = INREG(RADEON_OVR_CLR); 505 save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT); 506 save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM); 507 save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); 508 save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL); 509 save->viph_control = INREG(RADEON_VIPH_CONTROL); 510 save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1); 511 save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL); 512 save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNTL); 513 save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL); 514 save->bus_cntl = INREG(RADEON_BUS_CNTL); 515 save->surface_cntl = INREG(RADEON_SURFACE_CNTL); 516 save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL); 517 save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL); 518 519 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 520 (info->ChipFamily == CHIP_FAMILY_RS480)) { 521 save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1); 522 save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2); 523 save->dmif_mem_cntl1 = INREG(RS400_DMIF_MEM_CNTL1); 524 save->disp1_req_cntl1 = INREG(RS400_DISP1_REQ_CNTL1); 525 } 526 } 527 528 /* Read CRTC registers */ 529 void 530 RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 531 { 532 RADEONInfoPtr info = RADEONPTR(pScrn); 533 unsigned char *RADEONMMIO = info->MMIO; 534 535 save->crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 536 save->crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 537 save->crtc_h_total_disp = INREG(RADEON_CRTC_H_TOTAL_DISP); 538 save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID); 539 save->crtc_v_total_disp = INREG(RADEON_CRTC_V_TOTAL_DISP); 540 save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID); 541 542 save->crtc_offset = INREG(RADEON_CRTC_OFFSET); 543 save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); 544 save->crtc_pitch = INREG(RADEON_CRTC_PITCH); 545 save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL); 546 547 if (IS_R300_VARIANT) 548 save->crtc_tile_x0_y0 = INREG(R300_CRTC_TILE_X0_Y0); 549 550 if (info->IsDellServer) { 551 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); 552 save->dac2_cntl = INREG(RADEON_DAC_CNTL2); 553 save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG); 554 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 555 } 556 557 /* track if the crtc is enabled for text restore */ 558 if (save->crtc_ext_cntl & RADEON_CRTC_DISPLAY_DIS) 559 info->crtc_on = FALSE; 560 else 561 info->crtc_on = TRUE; 562 563 } 564 565 /* Read CRTC2 registers */ 566 void 567 RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) 568 { 569 RADEONInfoPtr info = RADEONPTR(pScrn); 570 unsigned char *RADEONMMIO = info->MMIO; 571 572 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 573 save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP); 574 save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID); 575 save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP); 576 save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID); 577 578 save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET); 579 save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL); 580 save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH); 581 582 if (IS_R300_VARIANT) 583 save->crtc2_tile_x0_y0 = INREG(R300_CRTC2_TILE_X0_Y0); 584 585 save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); 586 save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); 587 588 save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); 589 590 /* track if the crtc is enabled for text restore */ 591 if (save->crtc2_gen_cntl & RADEON_CRTC2_DISP_DIS) 592 info->crtc2_on = FALSE; 593 else 594 info->crtc2_on = TRUE; 595 596 } 597 598 /* Read PLL registers */ 599 void 600 RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 601 { 602 save->ppll_ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV); 603 save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3); 604 save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL); 605 save->vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 606 607 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 608 "Read: 0x%08x 0x%08x 0x%08x\n", 609 save->ppll_ref_div, 610 save->ppll_div_3, 611 (unsigned)save->htotal_cntl); 612 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 613 "Read: rd=%d, fd=%d, pd=%d\n", 614 save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, 615 save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, 616 (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); 617 } 618 619 /* Read PLL registers */ 620 void 621 RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) 622 { 623 save->p2pll_ref_div = INPLL(pScrn, RADEON_P2PLL_REF_DIV); 624 save->p2pll_div_0 = INPLL(pScrn, RADEON_P2PLL_DIV_0); 625 save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL); 626 save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 627 628 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 629 "Read: 0x%08x 0x%08x 0x%08x\n", 630 (unsigned)save->p2pll_ref_div, 631 (unsigned)save->p2pll_div_0, 632 (unsigned)save->htotal_cntl2); 633 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 634 "Read: rd=%u, fd=%u, pd=%u\n", 635 (unsigned)(save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK), 636 (unsigned)(save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK), 637 (unsigned)((save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) 638 >> 16)); 639 } 640 641 void 642 radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post) 643 { 644 #if defined(XF86DRI) && defined(DRM_IOCTL_MODESET_CTL) 645 RADEONInfoPtr info = RADEONPTR(crtc->scrn); 646 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 647 struct drm_modeset_ctl modeset; 648 unsigned char *RADEONMMIO = info->MMIO; 649 650 if (!info->directRenderingEnabled) 651 return; 652 653 if (info->ChipFamily >= CHIP_FAMILY_R600) 654 return; 655 656 modeset.crtc = radeon_crtc->crtc_id; 657 modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET; 658 659 ioctl(info->dri->drmFD, DRM_IOCTL_MODESET_CTL, &modeset); 660 661 info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); 662 #endif 663 } 664 665 void 666 legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) 667 { 668 uint32_t mask; 669 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 670 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 671 unsigned char *RADEONMMIO = pRADEONEnt->MMIO; 672 673 if (radeon_crtc->crtc_id) 674 mask = (RADEON_CRTC2_DISP_DIS | 675 RADEON_CRTC2_VSYNC_DIS | 676 RADEON_CRTC2_HSYNC_DIS | 677 RADEON_CRTC2_DISP_REQ_EN_B); 678 else 679 mask = (RADEON_CRTC_DISPLAY_DIS | 680 RADEON_CRTC_HSYNC_DIS | 681 RADEON_CRTC_VSYNC_DIS); 682 683 switch(mode) { 684 case DPMSModeOn: 685 if (radeon_crtc->crtc_id) { 686 OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 687 } else { 688 OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | RADEON_CRTC_DISP_REQ_EN_B)); 689 OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask); 690 } 691 break; 692 case DPMSModeStandby: 693 case DPMSModeSuspend: 694 case DPMSModeOff: 695 if (radeon_crtc->crtc_id) { 696 OUTREGP(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 697 } else { 698 OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | RADEON_CRTC_DISP_REQ_EN_B)); 699 OUTREGP(RADEON_CRTC_EXT_CNTL, mask, ~mask); 700 } 701 break; 702 } 703 } 704 705 706 /* Define common registers for requested video mode */ 707 void 708 RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) 709 { 710 save->ovr_clr = 0; 711 save->ovr_wid_left_right = 0; 712 save->ovr_wid_top_bottom = 0; 713 save->ov0_scale_cntl = 0; 714 save->subpic_cntl = 0; 715 save->viph_control = 0; 716 save->i2c_cntl_1 = 0; 717 save->rbbm_soft_reset = 0; 718 save->cap0_trig_cntl = 0; 719 save->cap1_trig_cntl = 0; 720 save->bus_cntl = info->BusCntl; 721 722 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 723 (info->ChipFamily == CHIP_FAMILY_RS480)) { 724 save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1; 725 save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2; 726 save->dmif_mem_cntl1 = info->SavedReg->dmif_mem_cntl1; 727 save->disp1_req_cntl1 = info->SavedReg->disp1_req_cntl1; 728 } 729 730 /* 731 * If bursts are enabled, turn on discards 732 * Radeon doesn't have write bursts 733 */ 734 if (save->bus_cntl & (RADEON_BUS_READ_BURST)) 735 save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN; 736 } 737 738 void 739 RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) 740 { 741 save->surface_cntl = 0; 742 743 #if X_BYTE_ORDER == X_BIG_ENDIAN 744 /* We must set both apertures as they can be both used to map the entire 745 * video memory. -BenH. 746 */ 747 switch (crtc->scrn->bitsPerPixel) { 748 case 16: 749 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP; 750 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP; 751 break; 752 753 case 32: 754 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP; 755 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP; 756 break; 757 } 758 #endif 759 760 } 761 762 void 763 RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, 764 int x, int y) 765 { 766 ScrnInfoPtr pScrn = crtc->scrn; 767 RADEONInfoPtr info = RADEONPTR(pScrn); 768 int Base; 769 #ifdef XF86DRI 770 drm_radeon_sarea_t *pSAREAPriv; 771 XF86DRISAREAPtr pSAREA; 772 #endif 773 774 save->crtc_offset = pScrn->fbOffset; 775 #ifdef XF86DRI 776 if (info->dri && info->dri->allowPageFlip) 777 save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; 778 else 779 #endif 780 save->crtc_offset_cntl = 0; 781 782 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 783 if (IS_R300_VARIANT) 784 save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 785 R300_CRTC_MICRO_TILE_BUFFER_DIS | 786 R300_CRTC_MACRO_TILE_EN); 787 else 788 save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 789 } 790 else { 791 if (IS_R300_VARIANT) 792 save->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 793 R300_CRTC_MICRO_TILE_BUFFER_DIS | 794 R300_CRTC_MACRO_TILE_EN); 795 else 796 save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 797 } 798 799 Base = pScrn->fbOffset; 800 801 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 802 if (IS_R300_VARIANT) { 803 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 804 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 805 * Makes tiling MUCH easier. 806 */ 807 save->crtc_tile_x0_y0 = x | (y << 16); 808 Base &= ~0x7ff; 809 } else { 810 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 811 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 812 flickering when scrolling vertically in a virtual screen, possibly because crtc will 813 pick up the new offset value at the end of each scanline, but the new offset_cntl value 814 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 815 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 816 /*save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL) & ~0xf;*/ 817 #if 0 818 /* try to get rid of flickering when scrolling at least for 2d */ 819 #ifdef XF86DRI 820 if (!info->have3DWindows) 821 #endif 822 save->crtc_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 823 #endif 824 825 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 826 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 827 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 828 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 829 save->crtc_offset_cntl = save->crtc_offset_cntl | (y % 16); 830 } 831 } 832 else { 833 int offset = y * info->CurrentLayout.displayWidth + x; 834 switch (info->CurrentLayout.pixel_code) { 835 case 15: 836 case 16: offset *= 2; break; 837 case 24: offset *= 3; break; 838 case 32: offset *= 4; break; 839 } 840 Base += offset; 841 } 842 843 if (crtc->rotatedData != NULL) { 844 Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; 845 } 846 847 Base &= ~7; /* 3 lower bits are always 0 */ 848 849 850 #ifdef XF86DRI 851 if (info->directRenderingInited) { 852 /* note cannot use pScrn->pScreen since this is unitialized when called from 853 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 854 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 855 *** pageflipping! 856 ***/ 857 pSAREAPriv = DRIGetSAREAPrivate(xf86ScrnToScreen(pScrn)); 858 /* can't get at sarea in a semi-sane way? */ 859 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 860 861 pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) 862 % info->CurrentLayout.displayWidth; 863 pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) 864 / info->CurrentLayout.displayWidth; 865 pSAREA->frame.width = pScrn->frameX1 - x + 1; 866 pSAREA->frame.height = pScrn->frameY1 - y + 1; 867 868 if (pSAREAPriv->pfCurrentPage == 1) { 869 Base += info->dri->backOffset - info->dri->frontOffset; 870 } 871 } 872 #endif 873 save->crtc_offset = Base; 874 875 } 876 877 /* Define CRTC registers for requested video mode */ 878 static Bool 879 RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, 880 DisplayModePtr mode) 881 { 882 ScrnInfoPtr pScrn = crtc->scrn; 883 RADEONInfoPtr info = RADEONPTR(pScrn); 884 int format; 885 int hsync_start; 886 int hsync_wid; 887 int vsync_wid; 888 889 switch (info->CurrentLayout.pixel_code) { 890 case 4: format = 1; break; 891 case 8: format = 2; break; 892 case 15: format = 3; break; /* 555 */ 893 case 16: format = 4; break; /* 565 */ 894 case 24: format = 5; break; /* RGB */ 895 case 32: format = 6; break; /* xRGB */ 896 default: 897 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 898 "Unsupported pixel depth (%d)\n", 899 info->CurrentLayout.bitsPerPixel); 900 return FALSE; 901 } 902 903 /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/ 904 save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN 905 | (format << 8) 906 | ((mode->Flags & V_DBLSCAN) 907 ? RADEON_CRTC_DBL_SCAN_EN 908 : 0) 909 | ((mode->Flags & V_CSYNC) 910 ? RADEON_CRTC_CSYNC_EN 911 : 0) 912 | ((mode->Flags & V_INTERLACE) 913 ? RADEON_CRTC_INTERLACE_EN 914 : 0)); 915 916 /* 200M freezes on VT switch sometimes if CRTC is disabled */ 917 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 918 (info->ChipFamily == CHIP_FAMILY_RS480)) 919 save->crtc_gen_cntl |= RADEON_CRTC_EN; 920 921 save->crtc_ext_cntl |= (RADEON_XCRT_CNT_EN| 922 RADEON_CRTC_VSYNC_DIS | 923 RADEON_CRTC_HSYNC_DIS | 924 RADEON_CRTC_DISPLAY_DIS); 925 926 save->disp_merge_cntl = info->SavedReg->disp_merge_cntl; 927 save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 928 929 save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) 930 | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) 931 << 16)); 932 933 hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; 934 if (!hsync_wid) hsync_wid = 1; 935 hsync_start = mode->CrtcHSyncStart - 8; 936 937 save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 938 | ((hsync_wid & 0x3f) << 16) 939 | ((mode->Flags & V_NHSYNC) 940 ? RADEON_CRTC_H_SYNC_POL 941 : 0)); 942 943 /* This works for double scan mode. */ 944 save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) 945 | ((mode->CrtcVDisplay - 1) << 16)); 946 947 vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; 948 if (!vsync_wid) vsync_wid = 1; 949 950 save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) 951 | ((vsync_wid & 0x1f) << 16) 952 | ((mode->Flags & V_NVSYNC) 953 ? RADEON_CRTC_V_SYNC_POL 954 : 0)); 955 956 save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + 957 ((pScrn->bitsPerPixel * 8) -1)) / 958 (pScrn->bitsPerPixel * 8)); 959 save->crtc_pitch |= save->crtc_pitch << 16; 960 961 if (info->IsDellServer) { 962 save->dac2_cntl = info->SavedReg->dac2_cntl; 963 save->tv_dac_cntl = info->SavedReg->tv_dac_cntl; 964 save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl; 965 save->disp_hw_debug = info->SavedReg->disp_hw_debug; 966 967 save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 968 save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 969 970 /* For CRT on DAC2, don't turn it on if BIOS didn't 971 enable it, even it's detected. 972 */ 973 save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 974 save->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); 975 save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); 976 } 977 978 return TRUE; 979 } 980 981 982 void 983 RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, 984 int x, int y) 985 { 986 ScrnInfoPtr pScrn = crtc->scrn; 987 RADEONInfoPtr info = RADEONPTR(pScrn); 988 int Base; 989 #ifdef XF86DRI 990 drm_radeon_sarea_t *pSAREAPriv; 991 XF86DRISAREAPtr pSAREA; 992 #endif 993 994 /* It seems all fancy options apart from pflip can be safely disabled 995 */ 996 save->crtc2_offset = pScrn->fbOffset; 997 #ifdef XF86DRI 998 if (info->dri && info->dri->allowPageFlip) 999 save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; 1000 else 1001 #endif 1002 save->crtc2_offset_cntl = 0; 1003 1004 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 1005 if (IS_R300_VARIANT) 1006 save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 1007 R300_CRTC_MICRO_TILE_BUFFER_DIS | 1008 R300_CRTC_MACRO_TILE_EN); 1009 else 1010 save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN; 1011 } 1012 else { 1013 if (IS_R300_VARIANT) 1014 save->crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 1015 R300_CRTC_MICRO_TILE_BUFFER_DIS | 1016 R300_CRTC_MACRO_TILE_EN); 1017 else 1018 save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN; 1019 } 1020 1021 Base = pScrn->fbOffset; 1022 1023 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 1024 if (IS_R300_VARIANT) { 1025 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 1026 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 1027 * Makes tiling MUCH easier. 1028 */ 1029 save->crtc2_tile_x0_y0 = x | (y << 16); 1030 Base &= ~0x7ff; 1031 } else { 1032 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 1033 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 1034 flickering when scrolling vertically in a virtual screen, possibly because crtc will 1035 pick up the new offset value at the end of each scanline, but the new offset_cntl value 1036 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 1037 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 1038 /*save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & ~0xf;*/ 1039 #if 0 1040 /* try to get rid of flickering when scrolling at least for 2d */ 1041 #ifdef XF86DRI 1042 if (!info->have3DWindows) 1043 #endif 1044 save->crtc2_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 1045 #endif 1046 1047 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 1048 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 1049 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 1050 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 1051 save->crtc2_offset_cntl = save->crtc_offset_cntl | (y % 16); 1052 } 1053 } 1054 else { 1055 int offset = y * info->CurrentLayout.displayWidth + x; 1056 switch (info->CurrentLayout.pixel_code) { 1057 case 15: 1058 case 16: offset *= 2; break; 1059 case 24: offset *= 3; break; 1060 case 32: offset *= 4; break; 1061 } 1062 Base += offset; 1063 } 1064 1065 if (crtc->rotatedData != NULL) { 1066 Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; 1067 } 1068 1069 Base &= ~7; /* 3 lower bits are always 0 */ 1070 1071 #ifdef XF86DRI 1072 if (info->directRenderingInited) { 1073 /* note cannot use pScrn->pScreen since this is unitialized when called from 1074 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 1075 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 1076 *** pageflipping! 1077 ***/ 1078 pSAREAPriv = DRIGetSAREAPrivate(xf86ScrnToScreen(pScrn)); 1079 /* can't get at sarea in a semi-sane way? */ 1080 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 1081 1082 pSAREAPriv->crtc2_base = Base; 1083 1084 if (pSAREAPriv->pfCurrentPage == 1) { 1085 Base += info->dri->backOffset - info->dri->frontOffset; 1086 } 1087 } 1088 #endif 1089 save->crtc2_offset = Base; 1090 1091 } 1092 1093 1094 /* Define CRTC2 registers for requested video mode */ 1095 static Bool 1096 RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, 1097 DisplayModePtr mode) 1098 { 1099 ScrnInfoPtr pScrn = crtc->scrn; 1100 RADEONInfoPtr info = RADEONPTR(pScrn); 1101 int format; 1102 int hsync_start; 1103 int hsync_wid; 1104 int vsync_wid; 1105 1106 switch (info->CurrentLayout.pixel_code) { 1107 case 4: format = 1; break; 1108 case 8: format = 2; break; 1109 case 15: format = 3; break; /* 555 */ 1110 case 16: format = 4; break; /* 565 */ 1111 case 24: format = 5; break; /* RGB */ 1112 case 32: format = 6; break; /* xRGB */ 1113 default: 1114 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1115 "Unsupported pixel depth (%d)\n", 1116 info->CurrentLayout.bitsPerPixel); 1117 return FALSE; 1118 } 1119 1120 save->crtc2_h_total_disp = 1121 ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) 1122 | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) << 16)); 1123 1124 hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; 1125 if (!hsync_wid) hsync_wid = 1; 1126 hsync_start = mode->CrtcHSyncStart - 8; 1127 1128 save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff) 1129 | ((hsync_wid & 0x3f) << 16) 1130 | ((mode->Flags & V_NHSYNC) 1131 ? RADEON_CRTC_H_SYNC_POL 1132 : 0)); 1133 1134 /* This works for double scan mode. */ 1135 save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) 1136 | ((mode->CrtcVDisplay - 1) << 16)); 1137 1138 vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; 1139 if (!vsync_wid) vsync_wid = 1; 1140 1141 save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) 1142 | ((vsync_wid & 0x1f) << 16) 1143 | ((mode->Flags & V_NVSYNC) 1144 ? RADEON_CRTC2_V_SYNC_POL 1145 : 0)); 1146 1147 save->crtc2_pitch = ((pScrn->displayWidth * pScrn->bitsPerPixel) + 1148 ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8); 1149 save->crtc2_pitch |= save->crtc2_pitch << 16; 1150 1151 /* check to see if TV DAC is enabled for another crtc and keep it enabled */ 1152 if (save->crtc2_gen_cntl & RADEON_CRTC2_CRT2_ON) 1153 save->crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; 1154 else 1155 save->crtc2_gen_cntl = 0; 1156 1157 save->crtc2_gen_cntl |= ((format << 8) 1158 | RADEON_CRTC2_VSYNC_DIS 1159 | RADEON_CRTC2_HSYNC_DIS 1160 | RADEON_CRTC2_DISP_DIS 1161 | ((mode->Flags & V_DBLSCAN) 1162 ? RADEON_CRTC2_DBL_SCAN_EN 1163 : 0) 1164 | ((mode->Flags & V_CSYNC) 1165 ? RADEON_CRTC2_CSYNC_EN 1166 : 0) 1167 | ((mode->Flags & V_INTERLACE) 1168 ? RADEON_CRTC2_INTERLACE_EN 1169 : 0)); 1170 1171 /* 200M freezes on VT switch sometimes if CRTC is disabled */ 1172 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1173 (info->ChipFamily == CHIP_FAMILY_RS480)) 1174 save->crtc2_gen_cntl |= RADEON_CRTC2_EN; 1175 1176 save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl; 1177 save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN); 1178 1179 save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; 1180 save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid; 1181 1182 return TRUE; 1183 } 1184 1185 1186 /* Define PLL registers for requested video mode */ 1187 static void 1188 RADEONInitPLLRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, 1189 RADEONPLLPtr pll, DisplayModePtr mode, 1190 int flags) 1191 { 1192 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 1193 ScrnInfoPtr pScrn = crtc->scrn; 1194 RADEONInfoPtr info = RADEONPTR(pScrn); 1195 uint32_t feedback_div = 0; 1196 uint32_t frac_fb_div = 0; 1197 uint32_t reference_div = 0; 1198 uint32_t post_divider = 0; 1199 uint32_t freq = 0; 1200 1201 struct { 1202 int divider; 1203 int bitvalue; 1204 } *post_div, post_divs[] = { 1205 /* From RAGE 128 VR/RAGE 128 GL Register 1206 * Reference Manual (Technical Reference 1207 * Manual P/N RRG-G04100-C Rev. 0.04), page 1208 * 3-17 (PLL_DIV_[3:0]). 1209 */ 1210 { 1, 0 }, /* VCLK_SRC */ 1211 { 2, 1 }, /* VCLK_SRC/2 */ 1212 { 4, 2 }, /* VCLK_SRC/4 */ 1213 { 8, 3 }, /* VCLK_SRC/8 */ 1214 { 3, 4 }, /* VCLK_SRC/3 */ 1215 { 16, 5 }, /* VCLK_SRC/16 */ 1216 { 6, 6 }, /* VCLK_SRC/6 */ 1217 { 12, 7 }, /* VCLK_SRC/12 */ 1218 { 0, 0 } 1219 }; 1220 1221 1222 if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { 1223 save->ppll_ref_div = info->RefDivider; 1224 save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16); 1225 save->htotal_cntl = 0; 1226 return; 1227 } 1228 1229 if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE)) 1230 radeon_crtc->pll_algo = RADEON_PLL_NEW; 1231 else 1232 radeon_crtc->pll_algo = RADEON_PLL_OLD; 1233 1234 RADEONComputePLL(crtc, pll, mode->Clock, &freq, 1235 &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags); 1236 1237 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 1238 if (post_div->divider == post_divider) 1239 break; 1240 } 1241 1242 if (!post_div->divider) { 1243 save->pll_output_freq = freq; 1244 post_div = &post_divs[0]; 1245 } 1246 1247 save->dot_clock_freq = freq; 1248 save->feedback_div = feedback_div; 1249 save->reference_div = reference_div; 1250 save->post_div = post_divider; 1251 1252 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1253 "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", 1254 (unsigned)save->dot_clock_freq, 1255 (unsigned)save->pll_output_freq, 1256 save->feedback_div, 1257 save->reference_div, 1258 save->post_div); 1259 1260 save->ppll_ref_div = save->reference_div; 1261 1262 #if defined(__powerpc__) 1263 /* apparently programming this otherwise causes a hang??? */ 1264 if ((info->MacModel == RADEON_MAC_IBOOK) || 1265 (info->MacModel == RADEON_MAC_MINI_INTERNAL)) 1266 save->ppll_div_3 = 0x000600ad; 1267 else 1268 #endif 1269 save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); 1270 1271 save->htotal_cntl = mode->HTotal & 0x7; 1272 1273 save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl & 1274 ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; 1275 } 1276 1277 /* Define PLL2 registers for requested video mode */ 1278 static void 1279 RADEONInitPLL2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, 1280 RADEONPLLPtr pll, DisplayModePtr mode, 1281 int flags) 1282 { 1283 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 1284 ScrnInfoPtr pScrn = crtc->scrn; 1285 RADEONInfoPtr info = RADEONPTR(pScrn); 1286 uint32_t feedback_div = 0; 1287 uint32_t frac_fb_div = 0; 1288 uint32_t reference_div = 0; 1289 uint32_t post_divider = 0; 1290 uint32_t freq = 0; 1291 1292 struct { 1293 int divider; 1294 int bitvalue; 1295 } *post_div, post_divs[] = { 1296 /* From RAGE 128 VR/RAGE 128 GL Register 1297 * Reference Manual (Technical Reference 1298 * Manual P/N RRG-G04100-C Rev. 0.04), page 1299 * 3-17 (PLL_DIV_[3:0]). 1300 */ 1301 { 1, 0 }, /* VCLK_SRC */ 1302 { 2, 1 }, /* VCLK_SRC/2 */ 1303 { 4, 2 }, /* VCLK_SRC/4 */ 1304 { 8, 3 }, /* VCLK_SRC/8 */ 1305 { 3, 4 }, /* VCLK_SRC/3 */ 1306 { 6, 6 }, /* VCLK_SRC/6 */ 1307 { 12, 7 }, /* VCLK_SRC/12 */ 1308 { 0, 0 } 1309 }; 1310 1311 if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { 1312 save->p2pll_ref_div = info->RefDivider; 1313 save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16); 1314 save->htotal_cntl2 = 0; 1315 return; 1316 } 1317 1318 if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE)) 1319 radeon_crtc->pll_algo = RADEON_PLL_NEW; 1320 else 1321 radeon_crtc->pll_algo = RADEON_PLL_OLD; 1322 1323 RADEONComputePLL(crtc, pll, mode->Clock, &freq, 1324 &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags); 1325 1326 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 1327 if (post_div->divider == post_divider) 1328 break; 1329 } 1330 1331 if (!post_div->divider) { 1332 save->pll_output_freq_2 = freq; 1333 post_div = &post_divs[0]; 1334 } 1335 1336 save->dot_clock_freq_2 = freq; 1337 save->feedback_div_2 = feedback_div; 1338 save->reference_div_2 = reference_div; 1339 save->post_div_2 = post_divider; 1340 1341 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1342 "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", 1343 (unsigned)save->dot_clock_freq_2, 1344 (unsigned)save->pll_output_freq_2, 1345 save->feedback_div_2, 1346 save->reference_div_2, 1347 save->post_div_2); 1348 1349 save->p2pll_ref_div = save->reference_div_2; 1350 1351 save->p2pll_div_0 = (save->feedback_div_2 | 1352 (post_div->bitvalue << 16)); 1353 1354 save->htotal_cntl2 = mode->HTotal & 0x7; 1355 1356 save->pixclks_cntl = ((info->SavedReg->pixclks_cntl & 1357 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 1358 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 1359 } 1360 1361 static void 1362 radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) 1363 { 1364 /* pixclks_cntl controls tv clock routing */ 1365 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); 1366 } 1367 1368 /* Calculate display buffer watermark to prevent buffer underflow */ 1369 void 1370 RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, 1371 DisplayModePtr mode1, int pixel_bytes1, 1372 DisplayModePtr mode2, int pixel_bytes2) 1373 { 1374 RADEONInfoPtr info = RADEONPTR(pScrn); 1375 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1376 unsigned char *RADEONMMIO = info->MMIO; 1377 1378 uint32_t temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; 1379 float mem_tcas; 1380 int k1, c; 1381 1382 float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0.0}; 1383 float MemTcas_rs480[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 3.5}; 1384 float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7}; 1385 float MemTrbs[8] = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5}; 1386 float MemTrbs_r4xx[8] = {4, 5, 6, 7, 8, 9, 10, 11}; 1387 1388 float mem_bw, peak_disp_bw; 1389 float min_mem_eff = 0.8; 1390 float sclk_eff, sclk_delay; 1391 float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk; 1392 float disp_latency, disp_latency_overhead, disp_drain_rate = 0, disp_drain_rate2; 1393 float pix_clk, pix_clk2; /* in MHz */ 1394 int cur_size = 16; /* in octawords */ 1395 int critical_point = 0, critical_point2; 1396 int stop_req, max_stop_req; 1397 float read_return_rate, time_disp1_drop_priority; 1398 1399 /* 1400 * Set display0/1 priority up on r3/4xx in the memory controller for 1401 * high res modes if the user specifies HIGH for displaypriority 1402 * option. 1403 */ 1404 if ((info->DispPriority == 2) && IS_R300_VARIANT) { 1405 uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); 1406 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 1407 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 1408 if (pRADEONEnt->pCrtc[1]->enabled) 1409 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */ 1410 if (pRADEONEnt->pCrtc[0]->enabled) 1411 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */ 1412 OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 1413 } 1414 1415 /* 1416 * Determine if there is enough bandwidth for current display mode 1417 */ 1418 mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); 1419 1420 pix_clk = 0; 1421 pix_clk2 = 0; 1422 peak_disp_bw = 0; 1423 if (mode1) { 1424 pix_clk = mode1->Clock/1000.0; 1425 peak_disp_bw += (pix_clk * pixel_bytes1); 1426 } 1427 if (mode2) { 1428 pix_clk2 = mode2->Clock/1000.0; 1429 peak_disp_bw += (pix_clk2 * pixel_bytes2); 1430 } 1431 1432 if (peak_disp_bw >= mem_bw * min_mem_eff) { 1433 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1434 "You may not have enough display bandwidth for current mode\n" 1435 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 1436 } 1437 1438 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 1439 temp = INREG(RADEON_MEM_TIMING_CNTL); 1440 if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ 1441 mem_trcd = ((temp >> 2) & 0x3) + 1; 1442 mem_trp = ((temp & 0x3)) + 1; 1443 mem_tras = ((temp & 0x70) >> 4) + 1; 1444 } else if (info->ChipFamily == CHIP_FAMILY_R300 || 1445 info->ChipFamily == CHIP_FAMILY_R350) { /* r300, r350 */ 1446 mem_trcd = (temp & 0x7) + 1; 1447 mem_trp = ((temp >> 8) & 0x7) + 1; 1448 mem_tras = ((temp >> 11) & 0xf) + 4; 1449 } else if (info->ChipFamily == CHIP_FAMILY_RV350 || 1450 info->ChipFamily <= CHIP_FAMILY_RV380) { 1451 /* rv3x0 */ 1452 mem_trcd = (temp & 0x7) + 3; 1453 mem_trp = ((temp >> 8) & 0x7) + 3; 1454 mem_tras = ((temp >> 11) & 0xf) + 6; 1455 } else if (info->ChipFamily == CHIP_FAMILY_R420 || 1456 info->ChipFamily == CHIP_FAMILY_RV410) { 1457 /* r4xx */ 1458 mem_trcd = (temp & 0xf) + 3; 1459 if (mem_trcd > 15) 1460 mem_trcd = 15; 1461 mem_trp = ((temp >> 8) & 0xf) + 3; 1462 if (mem_trp > 15) 1463 mem_trp = 15; 1464 mem_tras = ((temp >> 12) & 0x1f) + 6; 1465 if (mem_tras > 31) 1466 mem_tras = 31; 1467 } else { /* RV200, R200 */ 1468 mem_trcd = (temp & 0x7) + 1; 1469 mem_trp = ((temp >> 8) & 0x7) + 1; 1470 mem_tras = ((temp >> 12) & 0xf) + 4; 1471 } 1472 1473 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 1474 temp = INREG(RADEON_MEM_SDRAM_MODE_REG); 1475 data = (temp & (7<<20)) >> 20; 1476 if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ 1477 if (info->ChipFamily == CHIP_FAMILY_RS480) /* don't think rs400 */ 1478 mem_tcas = MemTcas_rs480[data]; 1479 else 1480 mem_tcas = MemTcas[data]; 1481 } else { 1482 mem_tcas = MemTcas2 [data]; 1483 } 1484 if (info->ChipFamily == CHIP_FAMILY_RS400 || 1485 info->ChipFamily == CHIP_FAMILY_RS480) { 1486 /* extra cas latency stored in bits 23-25 0-4 clocks */ 1487 data = (temp >> 23) & 0x7; 1488 if (data < 5) 1489 mem_tcas += data; 1490 } 1491 1492 if (IS_R300_VARIANT && !info->IsIGP) { 1493 /* on the R300, Tcas is included in Trbs. 1494 */ 1495 temp = INREG(RADEON_MEM_CNTL); 1496 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 1497 if (data == 1) { 1498 if (R300_MEM_USE_CD_CH_ONLY & temp) { 1499 temp = INREG(R300_MC_IND_INDEX); 1500 temp &= ~R300_MC_IND_ADDR_MASK; 1501 temp |= R300_MC_READ_CNTL_CD_mcind; 1502 OUTREG(R300_MC_IND_INDEX, temp); 1503 temp = INREG(R300_MC_IND_DATA); 1504 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 1505 } else { 1506 temp = INREG(R300_MC_READ_CNTL_AB); 1507 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 1508 } 1509 } else { 1510 temp = INREG(R300_MC_READ_CNTL_AB); 1511 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 1512 } 1513 1514 if (info->ChipFamily == CHIP_FAMILY_RV410 || 1515 info->ChipFamily == CHIP_FAMILY_R420) 1516 mem_trbs = MemTrbs_r4xx[data]; 1517 else 1518 mem_trbs = MemTrbs[data]; 1519 mem_tcas += mem_trbs; 1520 } 1521 1522 if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ 1523 /* DDR64 SCLK_EFF = SCLK for analysis */ 1524 sclk_eff = info->sclk; 1525 } else { 1526 #ifdef XF86DRI 1527 if (info->directRenderingEnabled) 1528 sclk_eff = info->sclk - (info->dri->agpMode * 50.0 / 3.0); 1529 else 1530 #endif 1531 sclk_eff = info->sclk; 1532 } 1533 1534 /* 1535 Find the memory controller latency for the display client. 1536 */ 1537 if (IS_R300_VARIANT) { 1538 /*not enough for R350 ???*/ 1539 /* 1540 if (!mode2) sclk_delay = 150; 1541 else { 1542 if (info->RamWidth == 256) sclk_delay = 87; 1543 else sclk_delay = 97; 1544 } 1545 */ 1546 sclk_delay = 250; 1547 } else { 1548 if ((info->ChipFamily == CHIP_FAMILY_RV100) || 1549 info->IsIGP) { 1550 if (info->IsDDR) sclk_delay = 41; 1551 else sclk_delay = 33; 1552 } else { 1553 if (info->RamWidth == 128) sclk_delay = 57; 1554 else sclk_delay = 41; 1555 } 1556 } 1557 1558 mc_latency_sclk = sclk_delay / sclk_eff; 1559 1560 if (info->IsDDR) { 1561 if (info->RamWidth == 32) { 1562 k1 = 40; 1563 c = 3; 1564 } else { 1565 k1 = 20; 1566 c = 1; 1567 } 1568 } else { 1569 k1 = 40; 1570 c = 3; 1571 } 1572 mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) / 1573 info->mclk) + (4.0 / sclk_eff); 1574 1575 /* 1576 HW cursor time assuming worst case of full size colour cursor. 1577 */ 1578 cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (info->IsDDR+1))))) / info->mclk; 1579 cur_latency_sclk = cur_size / sclk_eff; 1580 1581 /* 1582 Find the total latency for the display data. 1583 */ 1584 disp_latency_overhead = 8.0 / info->sclk; 1585 mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk; 1586 mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk; 1587 disp_latency = MAX(mc_latency_mclk, mc_latency_sclk); 1588 1589 /* setup Max GRPH_STOP_REQ default value */ 1590 if (IS_RV100_VARIANT) 1591 max_stop_req = 0x5c; 1592 else 1593 max_stop_req = 0x7c; 1594 1595 if (mode1) { 1596 /* CRTC1 1597 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 1598 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 1599 */ 1600 stop_req = mode1->HDisplay * pixel_bytes1 / 16; 1601 1602 if (stop_req > max_stop_req) 1603 stop_req = max_stop_req; 1604 1605 /* 1606 Find the drain rate of the display buffer. 1607 */ 1608 disp_drain_rate = pix_clk / (16.0/pixel_bytes1); 1609 1610 /* 1611 Find the critical point of the display buffer. 1612 */ 1613 critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5); 1614 1615 /* ???? */ 1616 /* 1617 temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT; 1618 if (critical_point < temp) critical_point = temp; 1619 */ 1620 if (info->DispPriority == 2) { 1621 critical_point = 0; 1622 } 1623 1624 /* 1625 The critical point should never be above max_stop_req-4. Setting 1626 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 1627 */ 1628 if (max_stop_req - critical_point < 4) critical_point = 0; 1629 1630 if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { 1631 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 1632 critical_point = 0x10; 1633 } 1634 1635 temp = info->SavedReg->grph_buffer_cntl; 1636 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 1637 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 1638 temp &= ~(RADEON_GRPH_START_REQ_MASK); 1639 if ((info->ChipFamily == CHIP_FAMILY_R350) && 1640 (stop_req > 0x15)) { 1641 stop_req -= 0x10; 1642 } 1643 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 1644 1645 temp |= RADEON_GRPH_BUFFER_SIZE; 1646 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 1647 RADEON_GRPH_CRITICAL_AT_SOF | 1648 RADEON_GRPH_STOP_CNTL); 1649 /* 1650 Write the result into the register. 1651 */ 1652 OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 1653 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 1654 1655 #if 0 1656 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1657 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1658 /* attempt to program RS400 disp regs correctly ??? */ 1659 temp = info->SavedReg->disp1_req_cntl1; 1660 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 1661 RS400_DISP1_STOP_REQ_LEVEL_MASK); 1662 OUTREG(RS400_DISP1_REQ_CNTL1, (temp | 1663 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 1664 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 1665 temp = info->SavedReg->dmif_mem_cntl1; 1666 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 1667 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 1668 OUTREG(RS400_DMIF_MEM_CNTL1, (temp | 1669 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 1670 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 1671 } 1672 #endif 1673 1674 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1675 "GRPH_BUFFER_CNTL from %x to %x\n", 1676 (unsigned int)info->SavedReg->grph_buffer_cntl, 1677 (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); 1678 } 1679 1680 if (mode2) { 1681 stop_req = mode2->HDisplay * pixel_bytes2 / 16; 1682 1683 if (stop_req > max_stop_req) stop_req = max_stop_req; 1684 1685 /* 1686 Find the drain rate of the display buffer. 1687 */ 1688 disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2); 1689 1690 temp = info->SavedReg->grph2_buffer_cntl; 1691 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 1692 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 1693 temp &= ~(RADEON_GRPH_START_REQ_MASK); 1694 if ((info->ChipFamily == CHIP_FAMILY_R350) && 1695 (stop_req > 0x15)) { 1696 stop_req -= 0x10; 1697 } 1698 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 1699 temp |= RADEON_GRPH_BUFFER_SIZE; 1700 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 1701 RADEON_GRPH_CRITICAL_AT_SOF | 1702 RADEON_GRPH_STOP_CNTL); 1703 1704 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 1705 (info->ChipFamily == CHIP_FAMILY_RS200)) 1706 critical_point2 = 0; 1707 else { 1708 read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); 1709 if (mode1) 1710 time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); 1711 else 1712 time_disp1_drop_priority = 0; 1713 1714 critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority + 1715 disp_latency) * disp_drain_rate2 + 0.5); 1716 1717 if (info->DispPriority == 2) { 1718 critical_point2 = 0; 1719 } 1720 1721 if (max_stop_req - critical_point2 < 4) critical_point2 = 0; 1722 1723 } 1724 1725 if (critical_point2 == 0 && info->ChipFamily == CHIP_FAMILY_R300) { 1726 /* some R300 cards have problem with this set to 0 */ 1727 critical_point2 = 0x10; 1728 } 1729 1730 OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 1731 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 1732 1733 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1734 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1735 #if 0 1736 /* attempt to program RS400 disp2 regs correctly ??? */ 1737 temp = info->SavedReg->disp2_req_cntl1; 1738 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 1739 RS400_DISP2_STOP_REQ_LEVEL_MASK); 1740 OUTREG(RS400_DISP2_REQ_CNTL1, (temp | 1741 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 1742 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 1743 temp = info->SavedReg->disp2_req_cntl2; 1744 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 1745 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 1746 OUTREG(RS400_DISP2_REQ_CNTL2, (temp | 1747 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 1748 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 1749 #endif 1750 OUTREG(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 1751 OUTREG(RS400_DISP2_REQ_CNTL2, 0x2749D000); 1752 OUTREG(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 1753 OUTREG(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 1754 } 1755 1756 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1757 "GRPH2_BUFFER_CNTL from %x to %x\n", 1758 (unsigned int)info->SavedReg->grph2_buffer_cntl, 1759 (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL)); 1760 } 1761 } 1762 1763 void 1764 legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 1765 DisplayModePtr adjusted_mode, int x, int y) 1766 { 1767 ScrnInfoPtr pScrn = crtc->scrn; 1768 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1769 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 1770 RADEONInfoPtr info = RADEONPTR(pScrn); 1771 int i = 0; 1772 double dot_clock = 0; 1773 int pll_flags = RADEON_PLL_LEGACY; 1774 Bool update_tv_routing = FALSE; 1775 Bool tilingChanged = FALSE; 1776 1777 if (adjusted_mode->Clock > 200000) /* range limits??? */ 1778 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 1779 else 1780 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 1781 1782 if (info->allowColorTiling) { 1783 radeon_crtc->can_tile = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 1784 tilingChanged = RADEONSetTiling(pScrn); 1785 } 1786 1787 for (i = 0; i < xf86_config->num_output; i++) { 1788 xf86OutputPtr output = xf86_config->output[i]; 1789 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1790 1791 if (output->crtc == crtc) { 1792 if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT | 1793 ATOM_DEVICE_DFP_SUPPORT)) 1794 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 1795 if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 1796 pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV); 1797 } 1798 } 1799 1800 1801 ErrorF("init memmap\n"); 1802 RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); 1803 ErrorF("init common\n"); 1804 RADEONInitCommonRegisters(info->ModeReg, info); 1805 1806 RADEONInitSurfaceCntl(crtc, info->ModeReg); 1807 1808 switch (radeon_crtc->crtc_id) { 1809 case 0: 1810 ErrorF("init crtc1\n"); 1811 RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode); 1812 RADEONInitCrtcBase(crtc, info->ModeReg, x, y); 1813 dot_clock = adjusted_mode->Clock / 1000.0; 1814 if (dot_clock) { 1815 ErrorF("init pll1\n"); 1816 RADEONInitPLLRegisters(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags); 1817 } else { 1818 info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div; 1819 info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3; 1820 info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl; 1821 } 1822 break; 1823 case 1: 1824 ErrorF("init crtc2\n"); 1825 RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode); 1826 RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); 1827 dot_clock = adjusted_mode->Clock / 1000.0; 1828 if (dot_clock) { 1829 ErrorF("init pll2\n"); 1830 RADEONInitPLL2Registers(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags); 1831 } 1832 break; 1833 } 1834 1835 for (i = 0; i < xf86_config->num_output; i++) { 1836 xf86OutputPtr output = xf86_config->output[i]; 1837 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1838 1839 if (output->crtc == crtc) { 1840 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 1841 switch (radeon_crtc->crtc_id) { 1842 case 0: 1843 RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1844 RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1845 update_tv_routing = TRUE; 1846 break; 1847 case 1: 1848 RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1849 RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1850 break; 1851 } 1852 } 1853 } 1854 } 1855 1856 ErrorF("restore memmap\n"); 1857 RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); 1858 ErrorF("restore common\n"); 1859 RADEONRestoreCommonRegisters(pScrn, info->ModeReg); 1860 1861 switch (radeon_crtc->crtc_id) { 1862 case 0: 1863 ErrorF("restore crtc1\n"); 1864 RADEONRestoreCrtcRegisters(pScrn, info->ModeReg); 1865 ErrorF("restore pll1\n"); 1866 RADEONRestorePLLRegisters(pScrn, info->ModeReg); 1867 break; 1868 case 1: 1869 ErrorF("restore crtc2\n"); 1870 RADEONRestoreCrtc2Registers(pScrn, info->ModeReg); 1871 ErrorF("restore pll2\n"); 1872 RADEONRestorePLL2Registers(pScrn, info->ModeReg); 1873 break; 1874 } 1875 1876 /* pixclks_cntl handles tv-out clock routing */ 1877 if (update_tv_routing) 1878 radeon_update_tv_routing(pScrn, info->ModeReg); 1879 1880 if (info->DispPriority) 1881 RADEONInitDispBandwidth(pScrn); 1882 1883 radeon_crtc->initialized = TRUE; 1884 1885 if (tilingChanged) { 1886 /* need to redraw front buffer, I guess this can be considered a hack ? */ 1887 /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ 1888 if (pScrn->pScreen) 1889 xf86EnableDisableFBAccess(XF86_ENABLEDISABLEFB_ARG(pScrn), FALSE); 1890 RADEONChangeSurfaces(pScrn); 1891 if (pScrn->pScreen) 1892 xf86EnableDisableFBAccess(XF86_ENABLEDISABLEFB_ARG(pScrn), TRUE); 1893 /* xf86SetRootClip would do, but can't access that here */ 1894 } 1895 1896 /* reset ecp_div for Xv */ 1897 info->ecp_div = -1; 1898 1899 } 1900 1901
Indexes created Mon Jul 20 00:27:07 UTC 2026