| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/GISel/ |
| PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI;
67 const PPCRegisterBankInfo &RBI)
69 TRI(*STI.getRegisterInfo()), RBI(RBI),
89 const PPCRegisterBankInfo &RBI) {
90 return new PPCInstructionSelector(TM, Subtarget, RBI);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVInstructionSelector.cpp | 36 const RISCVRegisterBankInfo &RBI);
47 const RISCVRegisterBankInfo &RBI;
71 const RISCVRegisterBankInfo &RBI)
73 TRI(*STI.getRegisterInfo()), RBI(RBI),
101 RISCVRegisterBankInfo &RBI) {
102 return new RISCVInstructionSelector(TM, Subtarget, RBI);
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| RISCVSubtarget.cpp | 86 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
87 RegBankInfo.reset(RBI);
89 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64Subtarget.cpp | 228 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
230 // FIXME: At this point, we can't rely on Subtarget having RBI.
231 // It's awkward to mix passing RBI and the Subtarget; should we pass
234 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
236 RegBankInfo.reset(RBI);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64PostSelectOptimize.cpp | 101 auto RBI = Subtarget.getRegBankInfo();
156 constrainOperandRegClass(MF, *TRI, MRI, *TII, *RBI, II, II.getDesc(),
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| AArch64InstructionSelector.cpp | 69 const AArch64RegisterBankInfo &RBI);
438 const AArch64RegisterBankInfo &RBI;
468 const AArch64RegisterBankInfo &RBI)
470 TRI(*STI.getRegisterInfo()), RBI(RBI),
484 const RegisterBankInfo &RBI,
619 const AArch64RegisterBankInfo &RBI,
645 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
774 const RegisterBankInfo &RBI) {
777 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstructionSelector.h | 59 const AMDGPURegisterBankInfo &RBI,
308 const AMDGPURegisterBankInfo &RBI;
|
| AMDGPURegBankCombiner.cpp | 37 const RegisterBankInfo &RBI;
44 RBI(*MF.getSubtarget().getRegBankInfo()),
69 return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID;
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| AMDGPURegisterBankInfo.cpp | 99 const AMDGPURegisterBankInfo &RBI;
107 : RBI(RBI_), MRI(MRI_), NewBank(RB) {}
124 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI);
150 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI);
1331 const AMDGPURegisterBankInfo &RBI,
1340 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget,
1360 &RBI.Subtarget, Alignment)) {
1361 if (RBI.getRegBank(Base, *MRI, *RBI.TRI) == &AMDGPU::VGPRRegBank)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCSubtarget.cpp | 63 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
64 RegBankInfo.reset(RBI);
67 *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
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| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86Subtarget.cpp | 320 auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
321 RegBankInfo.reset(RBI);
322 InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
|
| X86InstructionSelector.cpp | 63 const X86RegisterBankInfo &RBI);
136 const X86RegisterBankInfo &RBI;
155 const X86RegisterBankInfo &RBI)
157 TRI(*STI.getRegisterInfo()), RBI(RBI),
200 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
235 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
236 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
239 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
240 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSubtarget.cpp | 214 auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo());
215 RegBankInfo.reset(RBI);
217 *static_cast<const MipsTargetMachine *>(&TM), *this, *RBI));
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| MipsLegalizerInfo.cpp | 506 const RegisterBankInfo &RBI = *ST.getRegBankInfo();
512 return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
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| MipsRegisterBankInfo.cpp | 371 const RegisterBankInfo &RBI =
374 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI);
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| MipsInstructionSelector.cpp | 36 const MipsRegisterBankInfo &RBI);
63 const MipsRegisterBankInfo &RBI;
82 const MipsRegisterBankInfo &RBI)
84 TRI(*STI.getRegisterInfo()), RBI(RBI),
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID;
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID;
112 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| RegBankSelect.h | 487 const RegisterBankInfo *RBI = nullptr;
649 /// RBI = MF.subtarget.getRegBankInfo()
654 /// MappingCosts = RBI.getMapping(inst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMSubtarget.cpp | 116 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
118 // FIXME: At this point, we can't rely on Subtarget having RBI.
119 // It's awkward to mix passing RBI and the Subtarget; should we pass
122 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
124 RegBankInfo.reset(RBI);
|
| ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI;
162 const ARMRegisterBankInfo &RBI) {
163 return new ARMInstructionSelector(TM, STI, RBI);
173 const ARMRegisterBankInfo &RBI)
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI),
188 const RegisterBankInfo &RBI) {
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
213 const RegisterBankInfo &RBI) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/bugpoint/ |
| ExtractFunction.cpp | 96 Function::iterator RBI = RFI->begin(); // Get iterator to corresponding BB
97 std::advance(RBI, std::distance(PF->begin(), Function::const_iterator(PBB)));
99 BasicBlock::iterator RI = RBI->begin(); // Get iterator to corresponding inst
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBankInfo.cpp | 605 const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
606 (void)RBI;
624 assert(MOMapping.verify(RBI->getSizeInBits(
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| MIParser.cpp | 291 const RegisterBankInfo *RBI = Subtarget.getRegBankInfo();
294 if (!RBI)
297 for (unsigned I = 0, E = RBI->getNumRegBanks(); I < E; ++I) {
298 const auto &RegBank = RBI->getRegBank(I);
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